Add a driver for the AVM Fritz!Card PCI version 2 ISDN controller.

MFC after:	4 weeks

8 files changed, 3452 insertions, 0 deletions

diff --git a/sys/i4b/layer1/i4b_l1.h b/sys/i4b/layer1/i4b_l1.h
index ba4402cb..ab42894 100644
--- a/sys/i4b/layer1/i4b_l1.h
+++ b/sys/i4b/layer1/i4b_l1.h
@@ -58,6 +58,7 @@
 #define L0IFPNPUNIT(u) ( (((L1DRVR_IFPNP) << 8) & 0xff00) | ((u) & 0xff))
 #define L0ICCHPUNIT(u) ( (((L1DRVR_ICCHP) << 8) & 0xff00) | ((u) & 0xff))
 #define L0ITJCUNIT(u) ( (((L1DRVR_ITJC) << 8) & 0xff00) | ((u) & 0xff))
+#define L0IFPI2UNIT(u) ( (((L1DRVR_IFPI2) << 8) & 0xff00) | ((u) & 0xff))
 
 /* jump table for the multiplex functions */
 struct i4b_l1mux_func {
diff --git a/sys/i4b/layer1/i4b_l1dmux.c b/sys/i4b/layer1/i4b_l1dmux.c
index 9df32b5..2b310fe 100644
--- a/sys/i4b/layer1/i4b_l1dmux.c
+++ b/sys/i4b/layer1/i4b_l1dmux.c
@@ -36,6 +36,7 @@
 #include "isic.h"
 #include "iwic.h"
 #include "ifpi.h"
+#include "ifpi2.h"
 #include "ifpnp.h"
 #include "ihfc.h"
 #include "itjc.h"
@@ -95,6 +96,10 @@ static int l1iwicunittab[MAXL1UNITS];
 static int l1ifpiunittab[MAXL1UNITS];
 #endif
 
+#if NIFPI2 > 0
+static int l1ifpi2unittab[MAXL1UNITS];
+#endif
+
 #if NIHFC > 0
 static int l1ihfcunittab[MAXL1UNITS];
 #endif
@@ -177,6 +182,11 @@ getl1tab(int drv)
 			return(l1ifpiunittab);
 			break;
 #endif
+#if NIFPI2 > 0
+		case L1DRVR_IFPI2:
+			return(l1ifpi2unittab);
+			break;
+#endif
 #if NIHFC > 0
 		case L1DRVR_IHFC:
 			return(l1ihfcunittab);
@@ -315,6 +325,11 @@ i4b_l1_mph_status_ind(int drv_unit, int status, int parm, struct i4b_l1mux_func
 					printf("ifpi%d: passive stack unit %d\n", L0UNIT(drv_unit), numl1units);
 					break;
 #endif
+#if NIFPI2 > 0
+				case L1DRVR_IFPI2:
+					printf("ifpi2-%d: passive stack unit %d\n", L0UNIT(drv_unit), numl1units);
+					break;
+#endif
 #if NIFPNP > 0
 				case L1DRVR_IFPNP:
 					printf("ifpnp%d: passive stack unit %d\n", L0UNIT(drv_unit), numl1units);
diff --git a/sys/i4b/layer1/ifpi2/i4b_ifpi2_ext.h b/sys/i4b/layer1/ifpi2/i4b_ifpi2_ext.h
new file mode 100644
index 0000000..8656924
--- /dev/null
+++ b/sys/i4b/layer1/ifpi2/i4b_ifpi2_ext.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2001 Gary Jennejohn. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *---------------------------------------------------------------------------
+ *
+ *      i4b_ifpi2 - Fritz!Card PCI Version 2 for split layers
+ *      ------------------------------------------
+ *
+ *	$Id$
+ *
+ * $FreeBSD$
+ *
+ *
+ *---------------------------------------------------------------------------*/
+
+#ifndef _I4B_IFPI2_EXT_H_
+#define _I4B_IFPI2_EXT_H_
+
+#include <i4b/include/i4b_l3l4.h>
+
+void ifpi2_set_linktab(int , int , drvr_link_t * );
+isdn_link_t *ifpi2_ret_linktab(int , int );
+
+int ifpi2_ph_data_req(int , struct mbuf *, int );
+int ifpi2_ph_activate_req(int );
+int ifpi2_mph_command_req(int , int , void *);
+
+void ifpi2_isacsx_irq(struct l1_softc *, int );
+void ifpi2_isacsx_l1_cmd(struct l1_softc *, int );
+int ifpi2_isacsx_init(struct l1_softc *);
+
+void ifpi2_recover(struct l1_softc *);
+char * ifpi2_printstate(struct l1_softc *);
+void ifpi2_next_state(struct l1_softc *, int );
+
+#define IFPI2_MAXUNIT 4
+extern struct l1_softc *ifpi2_scp[IFPI2_MAXUNIT];
+
+/* the ISACSX has 2 mask registers of interest - cannot use ISAC_IMASK */
+extern unsigned char isacsx_imaskd;
+extern unsigned char isacsx_imask;
+
+#endif /* _I4B_IFPI2_EXT_H_ */
diff --git a/sys/i4b/layer1/ifpi2/i4b_ifpi2_isacsx.c b/sys/i4b/layer1/ifpi2/i4b_ifpi2_isacsx.c
new file mode 100644
index 0000000..288acf2
--- /dev/null
+++ b/sys/i4b/layer1/ifpi2/i4b_ifpi2_isacsx.c
@@ -0,0 +1,600 @@
+/*
+ * Copyright (c) 1997, 2000 Hellmuth Michaelis. All rights reserved.
+ * Copyright (c) 2001 Gary Jennejohn. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *---------------------------------------------------------------------------
+ *
+ *	i4b_ifpi2_isac.c - i4b Fritz PCI Version 2 ISACSX handler
+ *	--------------------------------------------
+ *
+ *	$Id$ 
+ *
+ * $FreeBSD$
+ *
+ *
+ *---------------------------------------------------------------------------*/
+
+#include "ifpi2.h"
+#include "pci.h"
+
+#if (NIFPI2 > 0) && (NPCI > 0)
+
+#include "opt_i4b.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/mbuf.h>
+#include <sys/socket.h>
+
+
+#include <net/if.h>
+
+#include <machine/i4b_debug.h>
+#include <machine/i4b_ioctl.h>
+#include <machine/i4b_trace.h>
+
+#include <i4b/layer1/i4b_l1.h>
+
+#include <i4b/layer1/isic/i4b_isic.h>
+#include <i4b/layer1/isic/i4b_hscx.h>
+
+#include <i4b/layer1/ifpi2/i4b_ifpi2_ext.h>
+#include <i4b/layer1/ifpi2/i4b_ifpi2_isacsx.h>
+
+#include <i4b/include/i4b_global.h>
+#include <i4b/include/i4b_mbuf.h>
+
+static u_char ifpi2_isacsx_exir_hdlr(register struct l1_softc *sc, u_char exir);
+static void ifpi2_isacsx_ind_hdlr(register struct l1_softc *sc, int ind);
+
+/* the ISACSX has 2 mask registers of interest - cannot use ISAC_IMASK */
+unsigned char isacsx_imaskd;
+unsigned char isacsx_imask;
+
+/*---------------------------------------------------------------------------*
+ *	ISACSX interrupt service routine
+ *---------------------------------------------------------------------------*/
+void
+ifpi2_isacsx_irq(struct l1_softc *sc, int ista)
+{
+	register u_char c = 0;
+	register u_char istad = 0;
+
+	NDBGL1(L1_F_MSG, "unit %d: ista = 0x%02x", sc->sc_unit, ista);
+
+	/* was it an HDLC interrupt ? */
+	if (ista & ISACSX_ISTA_ICD)
+	{
+		istad = ISAC_READ(I_ISTAD);
+		NDBGL1(L1_F_MSG, "unit %d: istad = 0x%02x", sc->sc_unit, istad);
+
+		if(istad & (ISACSX_ISTAD_RFO|ISACSX_ISTAD_XMR|ISACSX_ISTAD_XDU))
+		{
+			/* not really EXIR, but very similar */
+			c |= ifpi2_isacsx_exir_hdlr(sc, istad);
+		}
+	}
+	
+	if(istad & ISACSX_ISTAD_RME)	/* receive message end */
+	{
+		register int rest;
+		u_char rsta;
+
+		/* get rx status register */
+		
+		rsta = ISAC_READ(I_RSTAD);
+
+		/* Check for Frame and CRC valid */
+		if((rsta & ISACSX_RSTAD_MASK) != (ISACSX_RSTAD_VFR|ISACSX_RSTAD_CRC))
+		{
+			int error = 0;
+			
+			if(!(rsta & ISACSX_RSTAD_VFR))	/* VFR error */
+			{
+				error++;
+				NDBGL1(L1_I_ERR, "unit %d: Frame not valid error", sc->sc_unit);
+			}
+	
+			if(!(rsta & ISACSX_RSTAD_CRC))	/* CRC error */
+			{
+				error++;
+				NDBGL1(L1_I_ERR, "unit %d: CRC error", sc->sc_unit);
+			}
+	
+			if(rsta & ISACSX_RSTAD_RDO)	/* ReceiveDataOverflow */
+			{
+				error++;
+				NDBGL1(L1_I_ERR, "unit %d: Data Overrun error", sc->sc_unit);
+			}
+	
+			if(rsta & ISACSX_RSTAD_RAB)	/* ReceiveABorted */
+			{
+				error++;
+				NDBGL1(L1_I_ERR, "unit %d: Receive Aborted error", sc->sc_unit);
+			}
+
+			if(error == 0)			
+				NDBGL1(L1_I_ERR, "unit %d: RME unknown error, RSTAD = 0x%02x!", sc->sc_unit, rsta);
+
+			i4b_Dfreembuf(sc->sc_ibuf);
+
+			c |= ISACSX_CMDRD_RMC|ISACSX_CMDRD_RRES;
+
+			sc->sc_ibuf = NULL;
+			sc->sc_ib = NULL;
+			sc->sc_ilen = 0;
+
+			ISAC_WRITE(I_CMDRD, ISACSX_CMDRD_RMC|ISACSX_CMDRD_RRES);
+
+			return;
+		}
+
+		rest = (ISAC_READ(I_RBCLD) & (ISACSX_FIFO_LEN-1));
+
+		if(rest == 0)
+			rest = ISACSX_FIFO_LEN;
+
+		if(sc->sc_ibuf == NULL)
+		{
+			if((sc->sc_ibuf = i4b_Dgetmbuf(rest)) != NULL)
+				sc->sc_ib = sc->sc_ibuf->m_data;
+			else
+				panic("ifpi2_isacsx_irq: RME, i4b_Dgetmbuf returns NULL!\n");
+			sc->sc_ilen = 0;
+		}
+
+		if(sc->sc_ilen <= (MAX_DFRAME_LEN - rest))
+		{
+			ISAC_RDFIFO(sc->sc_ib, rest);
+			 /* the  last byte contains status, strip it */
+			sc->sc_ilen += rest - 1;
+			
+			sc->sc_ibuf->m_pkthdr.len =
+				sc->sc_ibuf->m_len = sc->sc_ilen;
+
+			if(sc->sc_trace & TRACE_D_RX)
+			{
+				i4b_trace_hdr_t hdr;
+				hdr.unit = L0IFPI2UNIT(sc->sc_unit);
+				hdr.type = TRC_CH_D;
+				hdr.dir = FROM_NT;
+				hdr.count = ++sc->sc_trace_dcount;
+				MICROTIME(hdr.time);
+				i4b_l1_trace_ind(&hdr, sc->sc_ibuf->m_len, sc->sc_ibuf->m_data);
+			}
+
+			c |= ISACSX_CMDRD_RMC;
+
+			if(sc->sc_enabled &&
+			   (ctrl_desc[sc->sc_unit].protocol != PROTOCOL_D64S))
+			{
+				i4b_l1_ph_data_ind(L0IFPI2UNIT(sc->sc_unit), sc->sc_ibuf);
+			}
+			else
+			{
+				i4b_Dfreembuf(sc->sc_ibuf);
+			}
+		}
+		else
+		{
+			NDBGL1(L1_I_ERR, "RME, input buffer overflow!");
+			i4b_Dfreembuf(sc->sc_ibuf);
+			c |= ISACSX_CMDRD_RMC|ISACSX_CMDRD_RRES;
+		}
+
+		sc->sc_ibuf = NULL;
+		sc->sc_ib = NULL;
+		sc->sc_ilen = 0;
+	}
+
+	if(istad & ISACSX_ISTAD_RPF)	/* receive fifo full */
+	{
+		if(sc->sc_ibuf == NULL)
+		{
+			if((sc->sc_ibuf = i4b_Dgetmbuf(MAX_DFRAME_LEN)) != NULL)
+				sc->sc_ib= sc->sc_ibuf->m_data;
+			else
+				panic("ifpi2_isacsx_irq: RPF, i4b_Dgetmbuf returns NULL!\n");
+			sc->sc_ilen = 0;
+		}
+
+		if(sc->sc_ilen <= (MAX_DFRAME_LEN - ISACSX_FIFO_LEN))
+		{
+			ISAC_RDFIFO(sc->sc_ib, ISACSX_FIFO_LEN);
+			sc->sc_ilen += ISACSX_FIFO_LEN;			
+			sc->sc_ib += ISACSX_FIFO_LEN;
+			c |= ISACSX_CMDRD_RMC;
+		}
+		else
+		{
+			NDBGL1(L1_I_ERR, "RPF, input buffer overflow!");
+			i4b_Dfreembuf(sc->sc_ibuf);
+			sc->sc_ibuf = NULL;
+			sc->sc_ib = NULL;
+			sc->sc_ilen = 0;
+			c |= ISACSX_CMDRD_RMC|ISACSX_CMDRD_RRES;			
+		}
+	}
+
+	if(istad & ISACSX_ISTAD_XPR)	/* transmit fifo empty (XPR bit set) */
+	{
+		if((sc->sc_obuf2 != NULL) && (sc->sc_obuf == NULL))
+		{
+			sc->sc_freeflag = sc->sc_freeflag2;
+			sc->sc_obuf = sc->sc_obuf2;
+			sc->sc_op = sc->sc_obuf->m_data;
+			sc->sc_ol = sc->sc_obuf->m_len;
+			sc->sc_obuf2 = NULL;
+#ifdef NOTDEF			
+			printf("ob2=%x, op=%x, ol=%d, f=%d #",
+				sc->sc_obuf,
+				sc->sc_op,
+				sc->sc_ol,
+				sc->sc_state);
+#endif				
+		}
+		else
+		{
+#ifdef NOTDEF
+			printf("ob=%x, op=%x, ol=%d, f=%d #",
+				sc->sc_obuf,
+				sc->sc_op,
+				sc->sc_ol,
+				sc->sc_state);
+#endif
+		}			
+		
+		if(sc->sc_obuf)
+		{			
+			ISAC_WRFIFO(sc->sc_op, min(sc->sc_ol, ISACSX_FIFO_LEN));
+	
+			if(sc->sc_ol > ISACSX_FIFO_LEN)	/* length > 32 ? */
+			{
+				sc->sc_op += ISACSX_FIFO_LEN; /* bufferptr+32 */
+				sc->sc_ol -= ISACSX_FIFO_LEN; /* length - 32 */
+				c |= ISACSX_CMDRD_XTF;	    /* set XTF bit */
+			}
+			else
+			{
+				if(sc->sc_freeflag)
+				{
+					i4b_Dfreembuf(sc->sc_obuf);
+					sc->sc_freeflag = 0;
+				}
+				sc->sc_obuf = NULL;
+				sc->sc_op = NULL;
+				sc->sc_ol = 0;
+	
+				c |= ISACSX_CMDRD_XTF | ISACSX_CMDRD_XME;
+			}
+		}
+		else
+		{
+			sc->sc_state &= ~ISAC_TX_ACTIVE;
+		}
+	}
+	
+	if(ista & ISACSX_ISTA_CIC)	/* channel status change CISQ */
+	{
+		register u_char ci;
+	
+		/* get command/indication rx register*/
+	
+		ci = ISAC_READ(I_CIR0);
+
+		/* C/I code change IRQ (flag already cleared by CIR0 read) */
+	
+		if(ci & ISACSX_CIR0_CIC0)
+			ifpi2_isacsx_ind_hdlr(sc, (ci >> 4) & 0xf);
+	}
+	
+	if(c)
+	{
+		ISAC_WRITE(I_CMDRD, c);
+	}
+}
+
+/*---------------------------------------------------------------------------*
+ *	ISACSX L1 Extended IRQ handler
+ *---------------------------------------------------------------------------*/
+static u_char
+ifpi2_isacsx_exir_hdlr(register struct l1_softc *sc, u_char exir)
+{
+	u_char c = 0;
+	
+	if(exir & ISACSX_ISTAD_XMR)
+	{
+		NDBGL1(L1_I_ERR, "EXIRQ Tx Message Repeat");
+
+		c |= ISACSX_CMDRD_XRES;
+	}
+	
+	if(exir & ISACSX_ISTAD_XDU)
+	{
+		NDBGL1(L1_I_ERR, "EXIRQ Tx Data Underrun");
+
+		c |= ISACSX_CMDRD_XRES;
+	}
+
+	if(exir & ISACSX_ISTAD_RFO)
+	{
+		NDBGL1(L1_I_ERR, "EXIRQ Rx Frame Overflow");
+
+		c |= ISACSX_CMDRD_RMC;
+	}
+
+#if 0 /* all blocked per default */
+	if(exir & ISACSX_EXIR_SOV)
+	{
+		NDBGL1(L1_I_ERR, "EXIRQ Sync Xfer Overflow");
+	}
+
+	if(exir & ISACSX_EXIR_MOS)
+	{
+		NDBGL1(L1_I_ERR, "EXIRQ Monitor Status");
+	}
+
+	if(exir & ISACSX_EXIR_SAW)
+	{
+		/* cannot happen, STCR:TSF is set to 0 */
+		
+		NDBGL1(L1_I_ERR, "EXIRQ Subscriber Awake");
+	}
+
+	if(exir & ISACSX_EXIR_WOV)
+	{
+		/* cannot happen, STCR:TSF is set to 0 */
+
+		NDBGL1(L1_I_ERR, "EXIRQ Watchdog Timer Overflow");
+	}
+#endif
+
+	return(c);
+}
+
+/*---------------------------------------------------------------------------*
+ *	ISACSX L1 Indication handler
+ *---------------------------------------------------------------------------*/
+static void
+ifpi2_isacsx_ind_hdlr(register struct l1_softc *sc, int ind)
+{
+	register int event;
+	
+	switch(ind)
+	{
+		case ISACSX_CIR0_IAI8:
+			NDBGL1(L1_I_CICO, "rx AI8 in state %s", ifpi2_printstate(sc));
+			if(sc->sc_bustyp == BUS_TYPE_IOM2)
+				ifpi2_isacsx_l1_cmd(sc, CMD_AR8);
+			event = EV_INFO48;
+			i4b_l1_mph_status_ind(L0IFPI2UNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
+			break;
+			
+		case ISACSX_CIR0_IAI10:
+			NDBGL1(L1_I_CICO, "rx AI10 in state %s", ifpi2_printstate(sc));
+			if(sc->sc_bustyp == BUS_TYPE_IOM2)
+				ifpi2_isacsx_l1_cmd(sc, CMD_AR10);
+			event = EV_INFO410;
+			i4b_l1_mph_status_ind(L0IFPI2UNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
+			break;
+
+		case ISACSX_CIR0_IRSY:
+			NDBGL1(L1_I_CICO, "rx RSY in state %s", ifpi2_printstate(sc));
+			event = EV_RSY;
+			break;
+
+		case ISACSX_CIR0_IPU:
+			NDBGL1(L1_I_CICO, "rx PU in state %s", ifpi2_printstate(sc));
+			event = EV_PU;
+			break;
+
+		case ISACSX_CIR0_IDR:
+			NDBGL1(L1_I_CICO, "rx DR in state %s", ifpi2_printstate(sc));
+			ifpi2_isacsx_l1_cmd(sc, CMD_DIU);
+			event = EV_DR;			
+			break;
+			
+		case ISACSX_CIR0_IDID:
+			NDBGL1(L1_I_CICO, "rx DID in state %s", ifpi2_printstate(sc));
+			event = EV_INFO0;
+			i4b_l1_mph_status_ind(L0IFPI2UNIT(sc->sc_unit), STI_L1STAT, LAYER_IDLE, NULL);
+			break;
+
+		case ISACSX_CIR0_IDIS:
+			NDBGL1(L1_I_CICO, "rx DIS in state %s", ifpi2_printstate(sc));
+			event = EV_DIS;
+			break;
+
+		case ISACSX_CIR0_IEI:
+			NDBGL1(L1_I_CICO, "rx EI in state %s", ifpi2_printstate(sc));
+			ifpi2_isacsx_l1_cmd(sc, CMD_DIU);
+			event = EV_EI;
+			break;
+
+		case ISACSX_CIR0_IARD:
+			NDBGL1(L1_I_CICO, "rx ARD in state %s", ifpi2_printstate(sc));
+			event = EV_INFO2;
+			break;
+
+		case ISACSX_CIR0_ITI:
+			NDBGL1(L1_I_CICO, "rx TI in state %s", ifpi2_printstate(sc));
+			event = EV_INFO0;
+			break;
+
+		case ISACSX_CIR0_IATI:
+			NDBGL1(L1_I_CICO, "rx ATI in state %s", ifpi2_printstate(sc));
+			event = EV_INFO0;
+			break;
+
+		case ISACSX_CIR0_ISD:
+			NDBGL1(L1_I_CICO, "rx SD in state %s", ifpi2_printstate(sc));
+			event = EV_INFO0;
+			break;
+		
+		default:
+			NDBGL1(L1_I_ERR, "UNKNOWN Indication 0x%x in state %s", ind, ifpi2_printstate(sc));
+			event = EV_INFO0;
+			break;
+	}
+	ifpi2_next_state(sc, event);
+}
+
+/*---------------------------------------------------------------------------*
+ *	execute a layer 1 command
+ *---------------------------------------------------------------------------*/	
+void
+ifpi2_isacsx_l1_cmd(struct l1_softc *sc, int command)
+{
+	u_char cmd;
+
+#ifdef I4B_SMP_WORKAROUND
+
+	/* XXXXXXXXXXXXXXXXXXX */
+	
+	/*
+	 * patch from Wolfgang Helbig:
+	 *
+	 * Here is a patch that makes i4b work on an SMP:
+	 * The card (TELES 16.3) didn't interrupt on an SMP machine.
+	 * This is a gross workaround, but anyway it works *and* provides
+	 * some information as how to finally fix this problem.
+	 */
+	
+	HSCX_WRITE(0, H_MASK, 0xff);
+	HSCX_WRITE(1, H_MASK, 0xff);
+	ISAC_WRITE(I_MASKD, 0xff);
+	ISAC_WRITE(I_MASK, 0xff);
+	DELAY(100);
+	HSCX_WRITE(0, H_MASK, HSCX_A_IMASK);
+	HSCX_WRITE(1, H_MASK, HSCX_B_IMASK);
+	ISAC_WRITE(I_MASKD, isacsx_imaskd);
+	ISAC_WRITE(I_MASK, isacsx_imask);
+
+	/* XXXXXXXXXXXXXXXXXXX */
+	
+#endif /* I4B_SMP_WORKAROUND */
+
+	if(command < 0 || command > CMD_ILL)
+	{
+		NDBGL1(L1_I_ERR, "illegal cmd 0x%x in state %s", command, ifpi2_printstate(sc));
+		return;
+	}
+                                           
+	cmd = ISACSX_CIX0_LOW;
+
+	switch(command)
+	{
+		case CMD_TIM:
+			NDBGL1(L1_I_CICO, "tx TIM in state %s", ifpi2_printstate(sc));
+			cmd |= (ISACSX_CIX0_CTIM << 4);
+			break;
+
+		case CMD_RS:
+			NDBGL1(L1_I_CICO, "tx RS in state %s", ifpi2_printstate(sc));
+			cmd |= (ISACSX_CIX0_CRS << 4);
+			break;
+
+		case CMD_AR8:
+			NDBGL1(L1_I_CICO, "tx AR8 in state %s", ifpi2_printstate(sc));
+			cmd |= (ISACSX_CIX0_CAR8 << 4);
+			break;
+
+		case CMD_AR10:
+			NDBGL1(L1_I_CICO, "tx AR10 in state %s", ifpi2_printstate(sc));
+			cmd |= (ISACSX_CIX0_CAR10 << 4);
+			break;
+
+		case CMD_DIU:
+			NDBGL1(L1_I_CICO, "tx DIU in state %s", ifpi2_printstate(sc));
+			cmd |= (ISACSX_CIX0_CDIU << 4);
+			break;
+	}
+	ISAC_WRITE(I_CIX0, cmd);
+}
+
+/*---------------------------------------------------------------------------*
+ *	L1 ISACSX initialization
+ *---------------------------------------------------------------------------*/
+int
+ifpi2_isacsx_init(struct l1_softc *sc)
+{
+	isacsx_imaskd = 0xff;		/* disable all irqs */
+	isacsx_imask = 0xff;		/* disable all irqs */
+
+	ISAC_WRITE(I_MASKD, isacsx_imaskd);
+	ISAC_WRITE(I_MASK, isacsx_imask);
+
+	/* the ISACSX only runs in IOM-2 mode */
+	NDBGL1(L1_I_SETUP, "configuring for IOM-2 mode");
+
+	/* TR_CONF0: Transceiver Configuration Register 0:
+	 *	DIS_TR - transceiver enabled
+	 *	EN_ICV - normal operation
+	 *	EXLP - no external loop
+	 *	LDD - automatic clock generation
+	 */
+	ISAC_WRITE(I_WTR_CONF0, 0);
+
+	/* TR_CONF2: Transceiver Configuration Register 1:
+	 *	DIS_TX - transmitter enabled
+	 *	PDS - phase deviation 2 S-bits
+	 *	RLP - remote line loop open
+	 */
+	ISAC_WRITE(I_WTR_CONF2, 0);
+
+	/* MODED: Mode Register:
+	 *	MDSx - transparent mode 0
+	 *	TMD  - timer mode = external
+	 *	RAC  - Receiver enabled
+	 *	DIMx - digital i/f mode
+	 */
+	ISAC_WRITE(I_WMODED, ISACSX_MODED_MDS2|ISACSX_MODED_MDS1|ISACSX_MODED_RAC|ISACSX_MODED_DIM0);
+
+	/* enabled interrupts:
+	 * ===================
+	 * RME  - receive message end
+	 * RPF  - receive pool full
+	 * RPO  - receive pool overflow
+	 * XPR  - transmit pool ready
+	 * XMR  - transmit message repeat
+	 * XDU  - transmit data underrun
+	 */
+
+	isacsx_imaskd = ISACSX_MASKD_LOW;
+	ISAC_WRITE(I_MASKD, isacsx_imaskd);
+
+	/* enabled interrupts:
+	 * ===================
+	 * ICD - HDLC interrupt from D-channel
+	 * CIC - C/I channel change
+	 */
+
+	isacsx_imask = ~(ISACSX_MASK_ICD | ISACSX_MASK_CIC);
+
+	ISAC_WRITE(I_MASK, isacsx_imask);
+
+	return(0);
+}
+
+#endif /* NIFPI2 > 0 */
diff --git a/sys/i4b/layer1/ifpi2/i4b_ifpi2_isacsx.h b/sys/i4b/layer1/ifpi2/i4b_ifpi2_isacsx.h
new file mode 100644
index 0000000..3747674
--- /dev/null
+++ b/sys/i4b/layer1/ifpi2/i4b_ifpi2_isacsx.h
@@ -0,0 +1,573 @@
+/*
+ *   Copyright (c) 2001 Gary Jennejohn. All rights reserved. 
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *   1. Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *   3. Neither the name of the author nor the names of any co-contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *   4. Altered versions must be plainly marked as such, and must not be
+ *      misrepresented as being the original software and/or documentation.
+ *   
+ *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *   SUCH DAMAGE.
+ *
+ *---------------------------------------------------------------------------
+ *
+ * $FreeBSD$
+ *
+ *
+ *---------------------------------------------------------------------------*/
+ 
+#ifndef I4B_ISACSX_H_
+#define I4B_ISACSX_H_
+
+#define ISACSX_FIFO_LEN	32	/* 32 bytes FIFO on chip */
+
+#define ISACSX_V13 0x01
+
+/*
+ * definitions of registers and bits for the ISAC-SX ISDN chip.
+ */
+ 
+typedef struct isacsx_reg {
+
+	/* 32 byte deep FIFO always first */
+
+	unsigned char isacsx_fifo [ISACSX_FIFO_LEN];
+
+	/* most registers can be read/written, but have different names */
+	/* so define a union with read/write names to make that clear */
+
+	union {
+		struct {
+			unsigned char isacsx_istad;
+			unsigned char isacsx_stard;
+			unsigned char isacsx_moded;
+			unsigned char isacsx_exmd1;
+			unsigned char isacsx_timr1;
+			unsigned char dummy_25;
+			unsigned char isacsx_rbcld;
+			unsigned char isacsx_rbchd;
+			unsigned char isacsx_rstad;
+			unsigned char isacsx_tmd;
+			unsigned char dummy_2a;
+			unsigned char dummy_2b;
+			unsigned char dummy_2c;
+			unsigned char dummy_2d;
+			unsigned char isacsx_cir0;
+			unsigned char isacsx_codr1;
+			unsigned char isacsx_tr_conf0;
+			unsigned char isacsx_tr_conf1;
+			unsigned char isacsx_tr_conf2;
+			unsigned char isacsx_tr_sta;
+			unsigned char dummy_34;
+			unsigned char isacsx_sqrr1;
+			unsigned char isacsx_sqrr2;
+			unsigned char isacsx_sqrr3;
+			unsigned char isacsx_istatr;
+			unsigned char isacsx_masktr;
+			unsigned char dummy_3a;
+			unsigned char dummy_3b;
+			unsigned char isacsx_acgf2;
+			unsigned char dummy_3d;
+			unsigned char dummy_3e;
+			unsigned char dummy_3f;
+			unsigned char isacsx_cda10;
+			unsigned char isacsx_cda11;
+			unsigned char isacsx_cda20;
+			unsigned char isacsx_cda21;
+			unsigned char isacsx_cda_tsdp10;
+			unsigned char isacsx_cda_tsdp11;
+			unsigned char isacsx_cda_tsdp20;
+			unsigned char isacsx_cda_tsdp21;
+			unsigned char dummy_48;
+			unsigned char dummy_49;
+			unsigned char dummy_4a;
+			unsigned char dummy_4b;
+			unsigned char isacsx_tr_tsdp_bc1;
+			unsigned char isacsx_tr_tsdp_bc2;
+			unsigned char isacsx_cda1_cr;
+			unsigned char isacsx_cda2_cr;
+			unsigned char isacsx_tr_cr;
+			unsigned char dummy_51;
+			unsigned char dummy_52;
+			unsigned char isacsx_dci_cr;
+			unsigned char isacsx_mon_cr;
+			unsigned char isacsx_sds_cr;
+			unsigned char dummy_56;
+			unsigned char isacsx_iom_cr;
+			unsigned char isacsx_sti;
+			unsigned char isacsx_msti;
+			unsigned char isacsx_sds_conf;
+			unsigned char isacsx_mcda;
+			unsigned char isacsx_mor;
+			unsigned char isacsx_mosr;
+			unsigned char isacsx_mocr;
+			unsigned char isacsx_msta;
+			unsigned char isacsx_ista;
+			unsigned char isacsx_auxi;
+			unsigned char isacsx_mode1;
+			unsigned char isacsx_mode2;
+			unsigned char isacsx_id;
+			unsigned char isacsx_timr2;
+			unsigned char dummy_66;
+			unsigned char dummy_67;
+			unsigned char dummy_68;
+			unsigned char dummy_69;
+			unsigned char dummy_6a;
+			unsigned char dummy_6b;
+			unsigned char dummy_6c;
+			unsigned char dummy_6d;
+			unsigned char dummy_6e;
+			unsigned char dummy_6f;
+		} isacsx_r;
+		struct {
+			unsigned char isacsx_maskd;
+			unsigned char isacsx_cmdrd;
+			unsigned char isacsx_moded;
+			unsigned char isacsx_exmd1;
+			unsigned char isacsx_timr1;
+			unsigned char isacsx_sap1;
+			unsigned char isacsx_sap2;
+			unsigned char isacsx_tei1;
+			unsigned char isacsx_tei2;
+			unsigned char isacsx_tmd;
+			unsigned char dummy_2a;
+			unsigned char dummy_2b;
+			unsigned char dummy_2c;
+			unsigned char dummy_2d;
+			unsigned char isacsx_cix0;
+			unsigned char isacsx_codx1;
+			unsigned char isacsx_tr_conf0;
+			unsigned char isacsx_tr_conf1;
+			unsigned char isacsx_tr_conf2;
+			unsigned char dummy_33;
+			unsigned char dummy_34;
+			unsigned char isacsx_sqrx1;
+			unsigned char dummy_36;
+			unsigned char dummy_37;
+			unsigned char dummy_38;
+			unsigned char isacsx_masktr;
+			unsigned char dummy_3a;
+			unsigned char dummy_3b;
+			unsigned char isacsx_acgf2;
+			unsigned char dummy_3d;
+			unsigned char dummy_3e;
+			unsigned char dummy_3f;
+			unsigned char isacsx_cda10;
+			unsigned char isacsx_cda11;
+			unsigned char isacsx_cda20;
+			unsigned char isacsx_cda21;
+			unsigned char isacsx_cda_tsdp10;
+			unsigned char isacsx_cda_tsdp11;
+			unsigned char isacsx_cda_tsdp20;
+			unsigned char isacsx_cda_tsdp21;
+			unsigned char dummy_48;
+			unsigned char dummy_49;
+			unsigned char dummy_4a;
+			unsigned char dummy_4b;
+			unsigned char isacsx_tr_tsdp_bc1;
+			unsigned char isacsx_tr_tsdp_bc2;
+			unsigned char isacsx_cda1_cr;
+			unsigned char isacsx_cda2_cr;
+			unsigned char isacsx_tr_cr;
+			unsigned char dummy_51;
+			unsigned char dummy_52;
+			unsigned char isacsx_dci_cr;
+			unsigned char isacsx_mon_cr;
+			unsigned char isacsx_sds_cr;
+			unsigned char dummy_56;
+			unsigned char isacsx_iom_cr;
+			unsigned char isacsx_asti;
+			unsigned char isacsx_msti;
+			unsigned char isacsx_sds_conf;
+			unsigned char dummy_5b;
+			unsigned char isacsx_mox;
+			unsigned char dummy_5d;
+			unsigned char isacsx_mocr;
+			unsigned char isacsx_mconf;
+			unsigned char isacsx_mask;
+			unsigned char isacsx_auxm;
+			unsigned char isacsx_mode1;
+			unsigned char isacsx_mode2;
+			unsigned char isacsx_sres;
+			unsigned char isacsx_timr2;
+			unsigned char dummy_66;
+			unsigned char dummy_67;
+			unsigned char dummy_68;
+			unsigned char dummy_69;
+			unsigned char dummy_6a;
+			unsigned char dummy_6b;
+			unsigned char dummy_6c;
+			unsigned char dummy_6d;
+			unsigned char dummy_6e;
+			unsigned char dummy_6f;
+		} isacsx_w;
+	} isacsx_rw;
+} isacsx_reg_t;
+
+#define REG_OFFSET(type, field) (int)(&(((type *)0)->field))
+
+/* ISACSX read registers */
+
+#define i_istad isacsx_rw.isacsx_r.isacsx_istad
+#define I_ISTAD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_istad)
+#define i_stard isacsx_rw.isacsx_r.isacsx_stard
+#define I_STARD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_stard)
+#define i_rmoded isacsx_rw.isacsx_r.isacsx_moded
+#define I_RMODED REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_moded)
+#define i_rexmd1 isacsx_rw.isacsx_r.isacsx_exmd1
+#define I_REXMD1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_exmd1)
+#define i_rtimr1 isacsx_rw.isacsx_r.isacsx_timr1
+#define I_RTIMR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_timr1)
+#define i_rbcld isacsx_rw.isacsx_r.isacsx_rbcld
+#define I_RBCLD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_rbcld)
+#define i_rbchd isacsx_rw.isacsx_r.isacsx_rbchd
+#define I_RBCHD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_rbchd)
+#define i_rstad isacsx_rw.isacsx_r.isacsx_rstad
+#define I_RSTAD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_rstad)
+#define i_rtmd isacsx_rw.isacsx_r.isacsx_tmd
+#define I_RTMD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tmd)
+#define i_cir0 isacsx_rw.isacsx_r.isacsx_cir0
+#define I_CIR0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cir0)
+#define i_codr1 isacsx_rw.isacsx_r.isacsx_codr1
+#define I_CODR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_codr1)
+#define i_rtr_conf0 isacsx_rw.isacsx_r.isacsx_tr_conf0
+#define I_RTR_CONF0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_conf0)
+#define i_rtr_conf1 isacsx_rw.isacsx_r.isacsx_tr_conf1
+#define I_RTR_CONF1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_conf1)
+#define i_rtr_conf2 isacsx_rw.isacsx_r.isacsx_tr_conf2
+#define I_RTR_CONF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_conf2)
+#define i_sta isacsx_rw.isacsx_r.isacsx_sta
+#define I_STA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sta)
+#define i_sqrr1 isacsx_rw.isacsx_r.isacsx_sqrr1
+#define I_SQRR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sqrr1)
+#define i_sqrr2 isacsx_rw.isacsx_r.isacsx_sqrr2
+#define I_SQRR2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sqrr2)
+#define i_sqrr3 isacsx_rw.isacsx_r.isacsx_sqrr3
+#define I_SQRR3 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sqrr3)
+#define i_istatr isacsx_rw.isacsx_r.isacsx_istatr
+#define I_ISTATR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_istatr)
+#define i_rmasktr isacsx_rw.isacsx_r.isacsx_masktr
+#define I_RMASKTR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_masktr)
+#define i_racgf2 isacsx_rw.isacsx_r.isacsx_acgf2
+#define I_RACGF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_acgf2)
+#define i_rcda10 isacsx_rw.isacsx_r.isacsx_cda10
+#define I_RCDA10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda10)
+#define i_rcda11 isacsx_rw.isacsx_r.isacsx_cda11
+#define I_RCDA11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda11)
+#define i_rcda20 isacsx_rw.isacsx_r.isacsx_cda20
+#define I_RCDA20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda20)
+#define i_rcda21 isacsx_rw.isacsx_r.isacsx_cda21
+#define I_RCDA21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda21)
+#define i_cda_tsdp10 isacsx_rw.isacsx_r.isacsx_cda_tsdp10
+#define I_CDA_TSDP10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp10)
+#define i_cda_tsdp11 isacsx_rw.isacsx_r.isacsx_cda_tsdp11
+#define I_CDA_TSDP11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp11)
+#define i_cda_tsdp20 isacsx_rw.isacsx_r.isacsx_cda_tsdp20
+#define I_CDA_TSDP20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp20)
+#define i_cda_tsdp21 isacsx_rw.isacsx_r.isacsx_cda_tsdp21
+#define I_CDA_TSDP21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp21)
+#define i_tr_tsdp_bc1 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1
+#define I_TR_TSDP_BC1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1)
+#define i_tr_tsdp_bc2 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2
+#define I_TR_TSDP_BC2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2)
+#define i_cda1_cr isacsx_rw.isacsx_r.isacsx_cda1_cr
+#define I_CDA1_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda1_cr)
+#define i_cda2_cr isacsx_rw.isacsx_r.isacsx_cda2_cr
+#define I_CDA2_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda2_cr)
+#define i_tr_cr isacsx_rw.isacsx_r.isacsx_tr_cr
+#define I_TR_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_cr)
+#define i_dci_cr isacsx_rw.isacsx_r.isacsx_dci_cr
+#define I_DCI_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_dci_cr)
+#define i_mon_cr isacsx_rw.isacsx_r.isacsx_mon_cr
+#define I_MON_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mon_cr)
+#define i_sds_cr isacsx_rw.isacsx_r.isacsx_sds_cr
+#define I_SDS_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_cr)
+#define i_iom_cr isacsx_rw.isacsx_r.isacsx_iom_cr
+#define I_IOM_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_iom_cr)
+#define i_sti isacsx_rw.isacsx_r.isacsx_sti
+#define I_STI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sti)
+#define i_msti isacsx_rw.isacsx_r.isacsx_msti
+#define I_MSTI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_msti)
+#define i_sds_conf isacsx_rw.isacsx_r.isacsx_sds_conf
+#define I_SDS_CONF REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_conf)
+#define i_mcda isacsx_rw.isacsx_r.isacsx_mcda
+#define I_MCDA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mcda)
+#define i_mor isacsx_rw.isacsx_r.isacsx_mor
+#define I_MOR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mor)
+#define i_mosr isacsx_rw.isacsx_r.isacsx_mosr
+#define I_MOSR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mosr)
+#define i_rmocr isacsx_rw.isacsx_r.isacsx_mocr
+#define I_RMOCR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mocr)
+#define i_msta isacsx_rw.isacsx_r.isacsx_msta
+#define I_MSTA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_msta)
+#define i_ista isacsx_rw.isacsx_r.isacsx_ista
+#define I_ISTA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_ista)
+#define i_auxi isacsx_rw.isacsx_r.isacsx_auxi
+#define I_AUXI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_auxi)
+#define i_rmode1 isacsx_rw.isacsx_r.isacsx_mode1
+#define I_RMODE1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mode1)
+#define i_rmode2 isacsx_rw.isacsx_r.isacsx_mode2
+#define I_RMODE2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mode2)
+#define i_id isacsx_rw.isacsx_r.isacsx_id
+#define I_ID REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_id)
+#define i_rtimr2 isacsx_rw.isacsx_r.isacsx_timr2
+#define I_RTIMR2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_timr2)
+
+/* ISAC write registers - isacsx_mode, isacsx_timr, isacsx_star2, isacsx_spcr, */
+/* isacsx_c1r, isacsx_c2r, isacsx_adf2 see read registers */
+
+#define i_maskd isacsx_rw.isacsx_w.isacsx_maskd
+#define I_MASKD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_maskd)
+#define i_cmdrd isacsx_rw.isacsx_w.isacsx_cmdrd
+#define I_CMDRD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_cmdrd)
+#define i_wmoded isacsx_rw.isacsx_w.isacsx_moded
+#define I_WMODED REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_moded)
+#define i_wexmd1 isacsx_rw.isacsx_w.isacsx_exmd1
+#define I_WEXMD1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_exmd1)
+#define i_wtimr1 isacsx_rw.isacsx_w.isacsx_timr1
+#define I_WTIMR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_timr1)
+#define i_sap1 isacsx_rw.isacsx_w.isacsx_sap1
+#define I_SAP1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sap1)
+#define i_sap2 isacsx_rw.isacsx_w.isacsx_sap2
+#define I_SAP2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sap2)
+#define i_tei1 isacsx_rw.isacsx_w.isacsx_tei1
+#define i_tei2 isacsx_rw.isacsx_w.isacsx_tei2
+#define i_wtmd isacsx_rw.isacsx_w.isacsx_tmd
+#define I_WTMD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tmd)
+#define i_cix0 isacsx_rw.isacsx_w.isacsx_cix0
+#define I_CIX0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_cix0)
+#define i_codx1 isacsx_rw.isacsx_w.isacsx_codx1
+#define I_CODX1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_codx1)
+#define i_wtr_conf0 isacsx_rw.isacsx_w.isacsx_tr_conf0
+#define I_WTR_CONF0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tr_conf0)
+#define i_wtr_conf1 isacsx_rw.isacsx_w.isacsx_tr_conf1
+#define I_WTR_CONF1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tr_conf1)
+#define i_wtr_conf2 isacsx_rw.isacsx_w.isacsx_tr_conf2
+#define I_WTR_CONF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tr_conf2)
+#define i_sqrx1 isacsx_rw.isacsx_w.isacsx_sqrx1
+#define I_SQRX1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sqrx1)
+#define i_wmasktr isacsx_rw.isacsx_w.isacsx_masktr
+#define I_WMASKTR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_masktr)
+#define i_wacgf2 isacsx_rw.isacsx_w.isacsx_acgf2
+#define I_WACGF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_acgf2)
+#define i_wcda10 isacsx_rw.isacsx_w.isacsx_cda10
+#define I_WCDA10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_cda10)
+#define i_wcda11 isacsx_rw.isacsx_r.isacsx_cda11
+#define I_WCDA11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda11)
+#define i_wcda20 isacsx_rw.isacsx_r.isacsx_cda20
+#define I_WCDA20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda20)
+#define i_wcda21 isacsx_rw.isacsx_r.isacsx_cda21
+#define I_WCDA21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda21)
+#define i_cda_tsdp10 isacsx_rw.isacsx_r.isacsx_cda_tsdp10
+#define I_CDA_TSDP10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp10)
+#define i_cda_tsdp11 isacsx_rw.isacsx_r.isacsx_cda_tsdp11
+#define I_CDA_TSDP11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp11)
+#define i_cda_tsdp20 isacsx_rw.isacsx_r.isacsx_cda_tsdp20
+#define I_CDA_TSDP20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp20)
+#define i_cda_tsdp21 isacsx_rw.isacsx_r.isacsx_cda_tsdp21
+#define I_CDA_TSDP21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp21)
+#define i_tr_tsdp_bc1 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1
+#define I_TR_TSDP_BC1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1)
+#define i_tr_tsdp_bc2 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2
+#define I_TR_TSDP_BC2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2)
+#define i_cda1_cr isacsx_rw.isacsx_r.isacsx_cda1_cr
+#define I_CDA1_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda1_cr)
+#define i_cda2_cr isacsx_rw.isacsx_r.isacsx_cda2_cr
+#define I_CDA2_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda2_cr)
+#define i_tr_cr isacsx_rw.isacsx_r.isacsx_tr_cr
+#define I_TR_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_cr)
+#define i_dci_cr isacsx_rw.isacsx_r.isacsx_dci_cr
+#define I_DCI_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_dci_cr)
+#define i_mon_cr isacsx_rw.isacsx_r.isacsx_mon_cr
+#define I_MON_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mon_cr)
+#define i_sds_cr isacsx_rw.isacsx_r.isacsx_sds_cr
+#define I_SDS_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_cr)
+#define i_iom_cr isacsx_rw.isacsx_r.isacsx_iom_cr
+#define I_IOM_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_iom_cr)
+#define i_asti isacsx_rw.isacsx_r.isacsx_asti
+#define I_ASTI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_asti)
+#define i_msti isacsx_rw.isacsx_r.isacsx_msti
+#define I_MSTI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_msti)
+#define i_sds_conf isacsx_rw.isacsx_r.isacsx_sds_conf
+#define I_SDS_CONF REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_conf)
+#define i_mox isacsx_rw.isacsx_w.isacsx_mox
+#define I_MOX REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mox)
+#define i_wmocr isacsx_rw.isacsx_w.isacsx_mocr
+#define I_WMOCR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mocr)
+#define i_mconf isacsx_rw.isacsx_w.isacsx_mconf
+#define I_MCONF REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mconf)
+#define i_mask isacsx_rw.isacsx_w.isacsx_mask
+#define I_MASK REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mask)
+#define i_auxm isacsx_rw.isacsx_w.isacsx_auxm
+#define I_AUXM REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_auxm)
+#define i_wmode1 isacsx_rw.isacsx_w.isacsx_mode1
+#define I_WMODE1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mode1)
+#define i_wmode2 isacsx_rw.isacsx_w.isacsx_mode2
+#define I_WMODE2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mode2)
+#define i_sres isacsx_rw.isacsx_w.isacsx_sres
+#define I_SRES REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sres)
+#define i_wtimr2 isacsx_rw.isacsx_w.isacsx_timr2
+#define I_WTIMR2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_timr2)
+
+#define ISACSX_ISTAD_RME  0x80
+#define ISACSX_ISTAD_RPF  0x40
+#define ISACSX_ISTAD_RFO  0x20
+#define ISACSX_ISTAD_XPR  0x10
+#define ISACSX_ISTAD_XMR  0x08
+#define ISACSX_ISTAD_XDU  0x04
+
+#define ISACSX_MASKD_RME  0x80
+#define ISACSX_MASKD_RPF  0x40
+#define ISACSX_MASKD_RFO  0x20
+#define ISACSX_MASKD_XPR  0x10
+#define ISACSX_MASKD_XMR  0x08
+#define ISACSX_MASKD_XDU  0x04
+/* these must always be set */
+#define ISACSX_MASKD_LOW  0x03
+#define ISACSX_MASKD_ALL  0xff
+
+#define ISACSX_STARD_XDOV 0x80
+#define ISACSX_STARD_XFW  0x40
+#define ISACSX_STARD_RAC1 0x08
+#define ISACSX_STARD_XAC1 0x02
+
+#define ISACSX_CMDRD_RMC  0x80
+#define ISACSX_CMDRD_RRES 0x40
+#define ISACSX_CMDRD_STI  0x10
+#define ISACSX_CMDRD_XTF  0x08
+#define ISACSX_CMDRD_XME  0x02
+#define ISACSX_CMDRD_XRES 0x01
+
+#define ISACSX_MODED_MDS2 0x80
+#define ISACSX_MODED_MDS1 0x40
+#define ISACSX_MODED_MDS0 0x20
+#define ISACSX_MODED_RAC  0x08
+#define ISACSX_MODED_DIM2 0x04
+#define ISACSX_MODED_DIM1 0x02
+#define ISACSX_MODED_DIM0 0x01
+
+/* default */
+#define ISACSX_EXMD1_XFBS_32  0x00 /* XFIFO is 32 bytes */
+#define ISACSX_EXMD1_XFBS_16  0x80 /* XFIFO is 16 bytes */
+/* default */
+#define ISACSX_EXMD1_RFBS_32  0x00 /* XFIFO is 32 bytes */
+#define ISACSX_EXMD1_RFBS_16  0x20 /* XFIFO is 16 bytes */
+#define ISACSX_EXMD1_RFBS_08  0x40 /* XFIFO is 8 bytes */
+#define ISACSX_EXMD1_RFBS_04  0x60 /* XFIFO is 4 bytes */
+#define ISACSX_EXMD1_SRA      0x10
+#define ISACSX_EXMD1_XCRC     0x08
+#define ISACSX_EXMD1_RCRC     0x04
+#define ISACSX_EXMD1_ITF      0x01
+
+#define ISACSX_RSTAD_VFR  0x80
+#define ISACSX_RSTAD_RDO  0x40
+#define ISACSX_RSTAD_CRC  0x20
+#define ISACSX_RSTAD_RAB  0x10
+#define ISACSX_RSTAD_SA1  0x08
+#define ISACSX_RSTAD_SA0  0x04
+#define ISACSX_RSTAD_CR   0x02
+#define ISACSX_RSTAD_TA   0x01
+
+#define ISACSX_RSTAD_MASK 0xf0	/* the interesting bits */
+
+#define ISACSX_RBCHD_OV   0x10
+/* the other 4 bits are the high bits of the receive byte count */
+
+#define ISACSX_CIR0_CIC0  0x08
+/* CODR0 >> 4 */
+#define ISACSX_CIR0_IPU   0x07
+#define ISACSX_CIR0_IDR   0x00
+#define ISACSX_CIR0_ISD   0x02
+#define ISACSX_CIR0_IDIS  0x03
+#define ISACSX_CIR0_IEI   0x06
+#define ISACSX_CIR0_IRSY  0x04
+#define ISACSX_CIR0_IARD  0x08
+#define ISACSX_CIR0_ITI   0x0a
+#define ISACSX_CIR0_IATI  0x0b
+#define ISACSX_CIR0_IAI8  0x0c
+#define ISACSX_CIR0_IAI10 0x0d
+#define ISACSX_CIR0_IDID  0x0f
+
+#define ISACSX_IOM_CR_SPU      0x80
+#define ISACSX_IOM_CR_CI_CS    0x20
+#define ISACSX_IOM_CR_TIC_DIS  0x10
+#define ISACSX_IOM_CR_EN_BCL   0x08
+#define ISACSX_IOM_CR_CLKM     0x04
+#define ISACSX_IOM_CR_DIS_OD   0x02
+#define ISACSX_IOM_CR_DIS_IOM  0x01
+
+#define ISACSX_CI_MASK	0x0f
+
+#define ISACSX_CIX0_BAC  0x01
+/* in IOM-2 mode the low bits are always 1 */
+#define ISACSX_CIX0_LOW  0x0e
+/* C/I codes from bits 7-4 (>> 4 & 0xf) */
+/* the commands */
+#define ISACSX_CIX0_CTIM  0
+#define ISACSX_CIX0_CRS   0x01
+/* test mode only */
+#define ISACSX_CIX0_CSSSP  0x02
+/* test mode only */
+#define ISACSX_CIX0_CSSCP  0x03
+#define ISACSX_CIX0_CAR8  0x08
+#define ISACSX_CIX0_CAR10 0x09
+#define ISACSX_CIX0_CARL  0x0a
+#define ISACSX_CIX0_CDIU  0x0f
+
+/* Interrupt, General Configuration Registers */
+
+#define ISACSX_ISTA_ST    0x20
+#define ISACSX_ISTA_CIC   0x10
+#define ISACSX_ISTA_AUX   0x08
+#define ISACSX_ISTA_TRAN  0x04
+#define ISACSX_ISTA_MOS   0x02
+#define ISACSX_ISTA_ICD   0x01
+
+#define ISACSX_MASK_ST    0x20
+#define ISACSX_MASK_CIC   0x10
+#define ISACSX_MASK_AUX   0x08
+#define ISACSX_MASK_TRAN  0x04
+#define ISACSX_MASK_MOS   0x02
+#define ISACSX_MASK_ICD   0x01
+
+#define ISACSX_AUXI_EAW   0x20
+#define ISACSX_AUXI_WOV   0x10
+#define ISACSX_AUXI_TIN2  0x08
+#define ISACSX_AUXI_TIN1  0x04
+
+#define ISACSX_AUXM_EAW   0x20
+#define ISACSX_AUXM_WOV   0x10
+#define ISACSX_AUXM_TIN2  0x08
+#define ISACSX_AUXM_TIN1  0x04
+
+#define ISACSX_MODE1_WTC1 0x10
+#define ISACSX_MODE1_WTC2 0x08
+#define ISACSX_MODE1_CFS  0x04
+#define ISACSX_MODE1_RSS2 0x02
+#define ISACSX_MODE1_RSS1 0x01
+
+#define ISACSX_MODE2_INT_POL 0x08
+#define ISACSX_MODE2_PPSDX   0x01
+
+#define ISACSX_ID_MASK 0x2F /* 0x01 = Version 1.3 */
+
+#endif /* I4B_ISACSX_H_ */
diff --git a/sys/i4b/layer1/ifpi2/i4b_ifpi2_l1.c b/sys/i4b/layer1/ifpi2/i4b_ifpi2_l1.c
new file mode 100644
index 0000000..60838f6
--- /dev/null
+++ b/sys/i4b/layer1/ifpi2/i4b_ifpi2_l1.c
@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 1997, 2000 Hellmuth Michaelis. All rights reserved.
+ * Copyright (c) 2001 Gary Jennejohn. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *---------------------------------------------------------------------------
+ *
+ *	i4b_ifpi2_l1.c - AVM Fritz PCI Version 2 layer 1 handler
+ *	---------------------------------------------
+ *
+ *	$Id$ 
+ *
+ * $FreeBSD$
+ *
+ *
+ *---------------------------------------------------------------------------*/
+
+#include "ifpi2.h"
+#include "pci.h"
+
+#if (NIFPI2 > 0) && (NPCI > 0)
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/mbuf.h>
+#include <sys/socket.h>
+
+
+#include <net/if.h>
+
+#include <machine/i4b_debug.h>
+#include <machine/i4b_ioctl.h>
+#include <machine/i4b_trace.h>
+
+#include <i4b/layer1/isic/i4b_isic.h>
+#include <i4b/layer1/isic/i4b_isac.h>
+
+#include <i4b/layer1/ifpi2/i4b_ifpi2_ext.h>
+
+#include <i4b/layer1/i4b_l1.h>
+
+#include <i4b/include/i4b_mbuf.h>
+#include <i4b/include/i4b_global.h>
+
+/*---------------------------------------------------------------------------*
+ *
+ *	L2 -> L1: PH-DATA-REQUEST
+ *	=========================
+ *
+ *	parms:
+ *		unit		physical interface unit number
+ *		m		mbuf containing L2 frame to be sent out
+ *		freeflag	MBUF_FREE: free mbuf here after having sent
+ *						it out
+ *				MBUF_DONTFREE: mbuf is freed by Layer 2
+ *	returns:
+ *		==0	fail, nothing sent out
+ *		!=0	ok, frame sent out
+ *
+ *---------------------------------------------------------------------------*/
+int
+ifpi2_ph_data_req(int unit, struct mbuf *m, int freeflag)
+{
+	u_char cmd;
+	int s;
+	struct l1_softc *sc = ifpi2_scp[unit];
+
+#ifdef NOTDEF
+	NDBGL1(L1_PRIM, "PH-DATA-REQ, unit %d, freeflag=%d", unit, freeflag);
+#endif
+
+	if(m == NULL)			/* failsafe */
+		return (0);
+
+	s = SPLI4B();
+
+	if(sc->sc_I430state == ST_F3)	/* layer 1 not running ? */
+	{
+		NDBGL1(L1_I_ERR, "still in state F3!");
+		ifpi2_ph_activate_req(unit);
+	}
+
+	if(sc->sc_state & ISAC_TX_ACTIVE)
+	{
+		if(sc->sc_obuf2 == NULL)
+		{
+			sc->sc_obuf2 = m;		/* save mbuf ptr */
+
+			if(freeflag)
+				sc->sc_freeflag2 = 1;	/* IRQ must mfree */
+			else
+				sc->sc_freeflag2 = 0;	/* IRQ must not mfree */
+
+			NDBGL1(L1_I_MSG, "using 2nd ISAC TX buffer, state = %s", ifpi2_printstate(sc));
+
+			if(sc->sc_trace & TRACE_D_TX)
+			{
+				i4b_trace_hdr_t hdr;
+				hdr.unit = L0IFPIUNIT(unit);
+				hdr.type = TRC_CH_D;
+				hdr.dir = FROM_TE;
+				hdr.count = ++sc->sc_trace_dcount;
+				MICROTIME(hdr.time);
+				i4b_l1_trace_ind(&hdr, m->m_len, m->m_data);
+			}
+			splx(s);
+			return(1);
+		}
+
+		NDBGL1(L1_I_ERR, "No Space in TX FIFO, state = %s", ifpi2_printstate(sc));
+	
+		if(freeflag == MBUF_FREE)
+			i4b_Dfreembuf(m);			
+	
+		splx(s);
+		return (0);
+	}
+
+	if(sc->sc_trace & TRACE_D_TX)
+	{
+		i4b_trace_hdr_t hdr;
+		hdr.unit = L0IFPIUNIT(unit);
+		hdr.type = TRC_CH_D;
+		hdr.dir = FROM_TE;
+		hdr.count = ++sc->sc_trace_dcount;
+		MICROTIME(hdr.time);
+		i4b_l1_trace_ind(&hdr, m->m_len, m->m_data);
+	}
+	
+	sc->sc_state |= ISAC_TX_ACTIVE;	/* set transmitter busy flag */
+
+	NDBGL1(L1_I_MSG, "ISAC_TX_ACTIVE set");
+
+	sc->sc_freeflag = 0;		/* IRQ must NOT mfree */
+	
+	ISAC_WRFIFO(m->m_data, min(m->m_len, ISAC_FIFO_LEN)); /* output to TX fifo */
+
+	if(m->m_len > ISAC_FIFO_LEN)	/* message > 32 bytes ? */
+	{
+		sc->sc_obuf = m;	/* save mbuf ptr */
+		sc->sc_op = m->m_data + ISAC_FIFO_LEN; 	/* ptr for irq hdl */
+		sc->sc_ol = m->m_len - ISAC_FIFO_LEN;	/* length for irq hdl */
+
+		if(freeflag)
+			sc->sc_freeflag = 1;	/* IRQ must mfree */
+		
+		cmd = ISAC_CMDR_XTF;
+	}
+	else
+	{
+		sc->sc_obuf = NULL;
+		sc->sc_op = NULL;
+		sc->sc_ol = 0;
+
+		if(freeflag)
+			i4b_Dfreembuf(m);
+
+		cmd = ISAC_CMDR_XTF | ISAC_CMDR_XME;
+  	}
+
+	ISAC_WRITE(I_CMDR, cmd);
+	ISACCMDRWRDELAY();
+
+	splx(s);
+	
+	return(1);
+}
+
+/*---------------------------------------------------------------------------*
+ *
+ *	L2 -> L1: PH-ACTIVATE-REQUEST
+ *	=============================
+ *
+ *	parms:
+ *		unit	physical interface unit number
+ *
+ *	returns:
+ *		==0	
+ *		!=0	
+ *
+ *---------------------------------------------------------------------------*/
+int
+ifpi2_ph_activate_req(int unit)
+{
+	struct l1_softc *sc = ifpi2_scp[unit];
+	NDBGL1(L1_PRIM, "PH-ACTIVATE-REQ, unit %d", unit);
+	ifpi2_next_state(sc, EV_PHAR);
+	return(0);
+}
+
+/*---------------------------------------------------------------------------*
+ *	command from the upper layers
+ *---------------------------------------------------------------------------*/
+int
+ifpi2_mph_command_req(int unit, int command, void *parm)
+{
+	struct l1_softc *sc = ifpi2_scp[unit];
+
+	switch(command)
+	{
+		case CMR_DOPEN:		/* daemon running */
+			NDBGL1(L1_PRIM, "unit %d, command = CMR_DOPEN", unit);
+			sc->sc_enabled = 1;			
+			break;
+			
+		case CMR_DCLOSE:	/* daemon not running */
+			NDBGL1(L1_PRIM, "unit %d, command = CMR_DCLOSE", unit);
+			sc->sc_enabled = 0;
+			break;
+
+		case CMR_SETTRACE:
+			NDBGL1(L1_PRIM, "unit %d, command = CMR_SETTRACE, parm = %d", unit, (unsigned int)parm);
+			sc->sc_trace = (unsigned int)parm;
+			break;
+		
+		default:
+			NDBGL1(L1_ERROR, "ERROR, unknown command = %d, unit = %d, parm = %d", command, unit, (unsigned int)parm);
+			break;
+	}
+
+	return(0);
+}
+
+#endif /* NIFPI2 > 0 */
diff --git a/sys/i4b/layer1/ifpi2/i4b_ifpi2_l1fsm.c b/sys/i4b/layer1/ifpi2/i4b_ifpi2_l1fsm.c
new file mode 100644
index 0000000..399d413
--- /dev/null
+++ b/sys/i4b/layer1/ifpi2/i4b_ifpi2_l1fsm.c
@@ -0,0 +1,516 @@
+/*
+ * Copyright (c) 1997, 2000 Hellmuth Michaelis. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *---------------------------------------------------------------------------
+ *
+ *	i4b_ifpi2_l1fsm.c - AVM Fritz PCI layer 1 I.430 state machine
+ *	------------------------------------------------------------
+ *
+ *	$Id$ 
+ *
+ * $FreeBSD$
+ *
+ *
+ *---------------------------------------------------------------------------*/
+
+#include "ifpi2.h"
+#include "pci.h"
+
+#if (NIFPI2 > 0) && (NPCI > 0)
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/socket.h>
+
+
+#include <net/if.h>
+
+#include <machine/i4b_debug.h>
+#include <machine/i4b_ioctl.h>
+#include <machine/i4b_trace.h>
+
+#include <i4b/layer1/isic/i4b_isic.h>
+
+#include <i4b/layer1/i4b_l1.h>
+
+#include <i4b/include/i4b_global.h>
+
+#include <i4b/include/i4b_mbuf.h>
+
+#include <i4b/layer1/ifpi2/i4b_ifpi2_ext.h>
+
+#if DO_I4B_DEBUG
+static char *state_text[N_STATES] = {
+	"F3 Deactivated",
+	"F4 Awaiting Signal",
+	"F5 Identifying Input",
+	"F6 Synchronized",
+	"F7 Activated",
+	"F8 Lost Framing",
+	"Illegal State"	
+};
+
+static char *event_text[N_EVENTS] = {
+	"EV_PHAR PH_ACT_REQ",
+	"EV_T3 Timer 3 expired",
+	"EV_INFO0 INFO0 received",
+	"EV_RSY Level Detected",
+	"EV_INFO2 INFO2 received",
+	"EV_INFO48 INFO4 received",
+	"EV_INFO410 INFO4 received",
+	"EV_DR Deactivate Req",
+	"EV_PU Power UP",
+	"EV_DIS Disconnected",
+	"EV_EI Error Ind",
+	"Illegal Event"
+};
+#endif
+
+/* Function prototypes */
+
+static void timer3_expired (struct l1_softc *sc);
+static void T3_start (struct l1_softc *sc);
+static void T3_stop (struct l1_softc *sc);
+static void F_T3ex (struct l1_softc *sc);
+static void timer4_expired (struct l1_softc *sc);
+static void T4_start (struct l1_softc *sc);
+static void T4_stop (struct l1_softc *sc);
+static void F_AI8 (struct l1_softc *sc);
+static void F_AI10 (struct l1_softc *sc);
+static void F_I01 (struct l1_softc *sc);
+static void F_I02 (struct l1_softc *sc);
+static void F_I03 (struct l1_softc *sc);
+static void F_I2 (struct l1_softc *sc);
+static void F_ill (struct l1_softc *sc);
+static void F_NULL (struct l1_softc *sc);
+
+/*---------------------------------------------------------------------------*
+ *	I.430 Timer T3 expire function
+ *---------------------------------------------------------------------------*/	
+static void
+timer3_expired(struct l1_softc *sc)
+{
+	if(sc->sc_I430T3)
+	{
+		NDBGL1(L1_T_ERR, "state = %s", ifpi2_printstate(sc));
+		sc->sc_I430T3 = 0;
+
+		/* XXX try some recovery here XXX */
+
+		ifpi2_recover(sc);
+
+		sc->sc_init_tries++;	/* increment retry count */
+
+/*XXX*/		if(sc->sc_init_tries > 4)
+		{
+			int s = SPLI4B();
+
+			sc->sc_init_tries = 0;
+			
+			if(sc->sc_obuf2 != NULL)
+			{
+				i4b_Dfreembuf(sc->sc_obuf2);
+				sc->sc_obuf2 = NULL;
+			}
+			if(sc->sc_obuf != NULL)
+			{
+				i4b_Dfreembuf(sc->sc_obuf);
+				sc->sc_obuf = NULL;
+				sc->sc_freeflag = 0;
+				sc->sc_op = NULL;
+				sc->sc_ol = 0;
+			}
+
+			splx(s);
+
+			i4b_l1_mph_status_ind(L0IFPI2UNIT(sc->sc_unit), STI_NOL1ACC, 0, NULL);
+		}
+		
+		ifpi2_next_state(sc, EV_T3);		
+	}
+	else
+	{
+		NDBGL1(L1_T_ERR, "expired without starting it ....");
+	}
+}
+
+/*---------------------------------------------------------------------------*
+ *	I.430 Timer T3 start
+ *---------------------------------------------------------------------------*/	
+static void
+T3_start(struct l1_softc *sc)
+{
+	NDBGL1(L1_T_MSG, "state = %s", ifpi2_printstate(sc));
+	sc->sc_I430T3 = 1;
+	sc->sc_T3_callout = timeout((TIMEOUT_FUNC_T)timer3_expired,(struct l1_softc *)sc, 2*hz);
+}
+
+/*---------------------------------------------------------------------------*
+ *	I.430 Timer T3 stop
+ *---------------------------------------------------------------------------*/	
+static void
+T3_stop(struct l1_softc *sc)
+{
+	NDBGL1(L1_T_MSG, "state = %s", ifpi2_printstate(sc));
+
+	sc->sc_init_tries = 0;	/* init connect retry count */
+	
+	if(sc->sc_I430T3)
+	{
+		sc->sc_I430T3 = 0;
+		untimeout((TIMEOUT_FUNC_T)timer3_expired,(struct l1_softc *)sc, sc->sc_T3_callout);
+	}
+}
+
+/*---------------------------------------------------------------------------*
+ *	I.430 Timer T3 expiry
+ *---------------------------------------------------------------------------*/	
+static void
+F_T3ex(struct l1_softc *sc)
+{
+	NDBGL1(L1_F_MSG, "FSM function F_T3ex executing");
+	if(ctrl_desc[sc->sc_unit].protocol != PROTOCOL_D64S)
+		i4b_l1_ph_deactivate_ind(L0IFPI2UNIT(sc->sc_unit));
+}
+
+/*---------------------------------------------------------------------------*
+ *	Timer T4 expire function
+ *---------------------------------------------------------------------------*/	
+static void
+timer4_expired(struct l1_softc *sc)
+{
+	if(sc->sc_I430T4)
+	{
+		NDBGL1(L1_T_MSG, "state = %s", ifpi2_printstate(sc));
+		sc->sc_I430T4 = 0;
+		i4b_l1_mph_status_ind(L0IFPI2UNIT(sc->sc_unit), STI_PDEACT, 0, NULL);
+	}
+	else
+	{
+		NDBGL1(L1_T_ERR, "expired without starting it ....");
+	}
+}
+
+/*---------------------------------------------------------------------------*
+ *	Timer T4 start
+ *---------------------------------------------------------------------------*/	
+static void
+T4_start(struct l1_softc *sc)
+{
+	NDBGL1(L1_T_MSG, "state = %s", ifpi2_printstate(sc));
+	sc->sc_I430T4 = 1;
+	sc->sc_T4_callout = timeout((TIMEOUT_FUNC_T)timer4_expired,(struct l1_softc *)sc, hz);
+}
+
+/*---------------------------------------------------------------------------*
+ *	Timer T4 stop
+ *---------------------------------------------------------------------------*/	
+static void
+T4_stop(struct l1_softc *sc)
+{
+	NDBGL1(L1_T_MSG, "state = %s", ifpi2_printstate(sc));
+
+	if(sc->sc_I430T4)
+	{
+		sc->sc_I430T4 = 0;
+		untimeout((TIMEOUT_FUNC_T)timer4_expired,(struct l1_softc *)sc, sc->sc_T4_callout);
+	}
+}
+
+/*---------------------------------------------------------------------------*
+ *	FSM function: received AI8
+ *---------------------------------------------------------------------------*/	
+static void
+F_AI8(struct l1_softc *sc)
+{
+	T4_stop(sc);
+
+	NDBGL1(L1_F_MSG, "FSM function F_AI8 executing");
+
+	if(ctrl_desc[sc->sc_unit].protocol != PROTOCOL_D64S)
+		i4b_l1_ph_activate_ind(L0IFPI2UNIT(sc->sc_unit));
+
+	T3_stop(sc);
+
+	if(sc->sc_trace & TRACE_I)
+	{
+		i4b_trace_hdr_t hdr;
+		char info = INFO4_8;
+		
+		hdr.unit = L0IFPI2UNIT(sc->sc_unit);
+		hdr.type = TRC_CH_I;
+		hdr.dir = FROM_NT;
+		hdr.count = 0;
+		MICROTIME(hdr.time);
+		i4b_l1_trace_ind(&hdr, 1, &info);
+	}
+}
+
+/*---------------------------------------------------------------------------*
+ *	FSM function: received AI10
+ *---------------------------------------------------------------------------*/	
+static void
+F_AI10(struct l1_softc *sc)
+{
+	T4_stop(sc);
+	
+	NDBGL1(L1_F_MSG, "FSM function F_AI10 executing");
+
+	if(ctrl_desc[sc->sc_unit].protocol != PROTOCOL_D64S)
+		i4b_l1_ph_activate_ind(L0IFPI2UNIT(sc->sc_unit));
+
+	T3_stop(sc);
+
+	if(sc->sc_trace & TRACE_I)
+	{
+		i4b_trace_hdr_t hdr;
+		char info = INFO4_10;
+		
+		hdr.unit = L0IFPI2UNIT(sc->sc_unit);
+		hdr.type = TRC_CH_I;
+		hdr.dir = FROM_NT;
+		hdr.count = 0;
+		MICROTIME(hdr.time);
+		i4b_l1_trace_ind(&hdr, 1, &info);
+	}
+}
+
+/*---------------------------------------------------------------------------*
+ *	FSM function: received INFO 0 in states F3 .. F5
+ *---------------------------------------------------------------------------*/	
+static void
+F_I01(struct l1_softc *sc)
+{
+	NDBGL1(L1_F_MSG, "FSM function F_I01 executing");
+
+	if(sc->sc_trace & TRACE_I)
+	{
+		i4b_trace_hdr_t hdr;
+		char info = INFO0;
+		
+		hdr.unit = L0IFPI2UNIT(sc->sc_unit);
+		hdr.type = TRC_CH_I;
+		hdr.dir = FROM_NT;
+		hdr.count = 0;
+		MICROTIME(hdr.time);
+		i4b_l1_trace_ind(&hdr, 1, &info);
+	}
+}
+
+/*---------------------------------------------------------------------------*
+ *	FSM function: received INFO 0 in state F6
+ *---------------------------------------------------------------------------*/	
+static void
+F_I02(struct l1_softc *sc)
+{
+	NDBGL1(L1_F_MSG, "FSM function F_I02 executing");
+
+	if(ctrl_desc[sc->sc_unit].protocol != PROTOCOL_D64S)
+		i4b_l1_ph_deactivate_ind(L0IFPI2UNIT(sc->sc_unit));
+
+	if(sc->sc_trace & TRACE_I)
+	{
+		i4b_trace_hdr_t hdr;
+		char info = INFO0;
+		
+		hdr.unit = L0IFPI2UNIT(sc->sc_unit);
+		hdr.type = TRC_CH_I;
+		hdr.dir = FROM_NT;
+		hdr.count = 0;
+		MICROTIME(hdr.time);
+		i4b_l1_trace_ind(&hdr, 1, &info);
+	}
+}
+
+/*---------------------------------------------------------------------------*
+ *	FSM function: received INFO 0 in state F7 or F8
+ *---------------------------------------------------------------------------*/	
+static void
+F_I03(struct l1_softc *sc)
+{
+	NDBGL1(L1_F_MSG, "FSM function F_I03 executing");
+
+	if(ctrl_desc[sc->sc_unit].protocol != PROTOCOL_D64S)
+		i4b_l1_ph_deactivate_ind(L0IFPI2UNIT(sc->sc_unit));
+
+	T4_start(sc);
+	
+	if(sc->sc_trace & TRACE_I)
+	{
+		i4b_trace_hdr_t hdr;
+		char info = INFO0;
+		
+		hdr.unit = L0IFPI2UNIT(sc->sc_unit);
+		hdr.type = TRC_CH_I;
+		hdr.dir = FROM_NT;
+		hdr.count = 0;
+		MICROTIME(hdr.time);
+		i4b_l1_trace_ind(&hdr, 1, &info);
+	}
+}
+
+/*---------------------------------------------------------------------------*
+ *	FSM function: activate request
+ *---------------------------------------------------------------------------*/	
+static void
+F_AR(struct l1_softc *sc)
+{
+	NDBGL1(L1_F_MSG, "FSM function F_AR executing");
+
+	if(sc->sc_trace & TRACE_I)
+	{
+		i4b_trace_hdr_t hdr;
+		char info = INFO1_8;
+		
+		hdr.unit = L0IFPI2UNIT(sc->sc_unit);
+		hdr.type = TRC_CH_I;
+		hdr.dir = FROM_TE;
+		hdr.count = 0;
+		MICROTIME(hdr.time);
+		i4b_l1_trace_ind(&hdr, 1, &info);
+	}
+
+	ifpi2_isacsx_l1_cmd(sc, CMD_AR8);
+
+	T3_start(sc);
+}
+
+/*---------------------------------------------------------------------------*
+ *	FSM function: received INFO2
+ *---------------------------------------------------------------------------*/	
+static void
+F_I2(struct l1_softc *sc)
+{
+	NDBGL1(L1_F_MSG, "FSM function F_I2 executing");
+
+	if(sc->sc_trace & TRACE_I)
+	{
+		i4b_trace_hdr_t hdr;
+		char info = INFO2;
+		
+		hdr.unit = L0IFPI2UNIT(sc->sc_unit);
+		hdr.type = TRC_CH_I;
+		hdr.dir = FROM_NT;
+		hdr.count = 0;
+		MICROTIME(hdr.time);
+		i4b_l1_trace_ind(&hdr, 1, &info);
+	}		
+
+}
+
+/*---------------------------------------------------------------------------*
+ *	illegal state default action
+ *---------------------------------------------------------------------------*/	
+static void
+F_ill(struct l1_softc *sc)
+{
+	NDBGL1(L1_F_ERR, "FSM function F_ill executing");
+}
+
+/*---------------------------------------------------------------------------*
+ *	No action
+ *---------------------------------------------------------------------------*/	
+static void
+F_NULL(struct l1_softc *sc)
+{
+	NDBGL1(L1_F_MSG, "FSM function F_NULL executing");
+}
+
+
+/*---------------------------------------------------------------------------*
+ *	layer 1 state transition table
+ *---------------------------------------------------------------------------*/	
+struct ifpi2_state_tab {
+	void (*func) (struct l1_softc *sc);	/* function to execute */
+	int newstate;				/* next state */
+} ifpi2_state_tab[N_EVENTS][N_STATES] = {
+
+/* STATE:	F3			F4			F5			F6			F7			F8			ILLEGAL STATE     */
+/* -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
+/* EV_PHAR x*/	{{F_AR,   ST_F4},	{F_NULL, ST_F4},	{F_NULL, ST_F5},	{F_NULL, ST_F6},	{F_ill,  ST_ILL},	{F_NULL, ST_F8},	{F_ill, ST_ILL}},
+/* EV_T3   x*/	{{F_NULL, ST_F3},	{F_T3ex, ST_F3},	{F_T3ex, ST_F3},	{F_T3ex, ST_F3},	{F_NULL, ST_F7},	{F_NULL, ST_F8},	{F_ill, ST_ILL}},
+/* EV_INFO0 */	{{F_I01,  ST_F3},	{F_I01,  ST_F4},	{F_I01,  ST_F5},	{F_I02,  ST_F3},	{F_I03,  ST_F3},	{F_I03,  ST_F3},	{F_ill, ST_ILL}},
+/* EV_RSY  x*/	{{F_NULL, ST_F3},	{F_NULL, ST_F5},	{F_NULL, ST_F5}, 	{F_NULL, ST_F8},	{F_NULL, ST_F8},	{F_NULL, ST_F8},	{F_ill, ST_ILL}},
+/* EV_INFO2 */	{{F_I2,   ST_F6},	{F_I2,   ST_F6},	{F_I2,   ST_F6},	{F_I2,   ST_F6},	{F_I2,   ST_F6},	{F_I2,   ST_F6},	{F_ill, ST_ILL}},
+/* EV_INFO48*/	{{F_AI8,  ST_F7},	{F_AI8,  ST_F7},	{F_AI8,  ST_F7},	{F_AI8,  ST_F7},	{F_NULL, ST_F7},	{F_AI8,  ST_F7},	{F_ill, ST_ILL}},
+/* EV_INFO41*/	{{F_AI10, ST_F7},	{F_AI10, ST_F7},	{F_AI10, ST_F7},	{F_AI10, ST_F7},	{F_NULL, ST_F7},	{F_AI10, ST_F7},	{F_ill, ST_ILL}},
+/* EV_DR    */	{{F_NULL, ST_F3},	{F_NULL, ST_F4},	{F_NULL, ST_F5},	{F_NULL, ST_F6},	{F_NULL, ST_F7},	{F_NULL, ST_F8},	{F_ill, ST_ILL}},
+/* EV_PU    */	{{F_NULL, ST_F3},	{F_NULL, ST_F4},	{F_NULL, ST_F5},	{F_NULL, ST_F6},	{F_NULL, ST_F7},	{F_NULL, ST_F8},	{F_ill, ST_ILL}},
+/* EV_DIS   */	{{F_ill,  ST_ILL},	{F_ill,  ST_ILL},	{F_ill,  ST_ILL},	{F_ill,  ST_ILL},	{F_ill,  ST_ILL},	{F_ill,  ST_ILL},	{F_ill, ST_ILL}},
+/* EV_EI    */	{{F_NULL, ST_F3},	{F_NULL, ST_F3},	{F_NULL, ST_F3},	{F_NULL, ST_F3},	{F_NULL, ST_F3},	{F_NULL, ST_F3},	{F_ill, ST_ILL}},
+/* EV_ILL   */	{{F_ill,  ST_ILL},	{F_ill,  ST_ILL},	{F_ill,  ST_ILL},	{F_ill,  ST_ILL},	{F_ill,  ST_ILL},	{F_ill,  ST_ILL},	{F_ill, ST_ILL}}
+};
+
+/*---------------------------------------------------------------------------*
+ *	event handler
+ *---------------------------------------------------------------------------*/	
+void
+ifpi2_next_state(struct l1_softc *sc, int event)
+{
+	int currstate, newstate;
+
+	if(event >= N_EVENTS)
+		panic("i4b_l1fsm.c: event >= N_EVENTS\n");
+
+	currstate = sc->sc_I430state;
+
+	if(currstate >= N_STATES)
+		panic("i4b_l1fsm.c: currstate >= N_STATES\n");	
+
+	newstate = ifpi2_state_tab[event][currstate].newstate;
+
+	if(newstate >= N_STATES)
+		panic("i4b_l1fsm.c: newstate >= N_STATES\n");	
+	
+	NDBGL1(L1_F_MSG, "FSM event [%s]: [%s => %s]", event_text[event],
+                                           state_text[currstate],
+                                           state_text[newstate]);
+
+        (*ifpi2_state_tab[event][currstate].func)(sc);
+
+	if(newstate == ST_ILL)
+	{
+		newstate = ST_F3;
+		NDBGL1(L1_F_ERR, "FSM Illegal State ERROR, oldstate = %s, newstate = %s, event = %s!",
+					state_text[currstate],
+					state_text[newstate],
+					event_text[event]);
+	}
+
+	sc->sc_I430state = newstate;
+}
+
+#if DO_I4B_DEBUG
+/*---------------------------------------------------------------------------*
+ *	return pointer to current state description
+ *---------------------------------------------------------------------------*/	
+char *
+ifpi2_printstate(struct l1_softc *sc)
+{
+	return((char *) state_text[sc->sc_I430state]);
+}
+#endif
+	
+#endif /* NIFPI2 > 0 */
diff --git a/sys/i4b/layer1/ifpi2/i4b_ifpi2_pci.c b/sys/i4b/layer1/ifpi2/i4b_ifpi2_pci.c
new file mode 100644
index 0000000..bbad26f
--- /dev/null
+++ b/sys/i4b/layer1/ifpi2/i4b_ifpi2_pci.c
@@ -0,0 +1,1439 @@
+/*
+ *   Copyright (c) 2001 Gary Jennejohn. All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *   1. Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *   3. Neither the name of the author nor the names of any co-contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *   4. Altered versions must be plainly marked as such, and must not be
+ *      misrepresented as being the original software and/or documentation.
+ *   
+ *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *   SUCH DAMAGE.
+ *
+ *---------------------------------------------------------------------------
+ *
+ *	i4b_ifpi2_pci.c: AVM Fritz!Card PCI hardware driver
+ *	--------------------------------------------------
+ *
+ *	$Id$
+ *
+ * $FreeBSD$
+ *
+ *
+ *---------------------------------------------------------------------------*/
+
+#include "ifpi2.h"
+#include "opt_i4b.h"
+#include "pci.h"
+
+#if (NIFPI2 > 0) && (NPCI > 0)
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/mbuf.h>
+
+#include <machine/bus.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+
+#include <pci/pcireg.h>
+#include <pci/pcivar.h>
+
+#include <sys/socket.h>
+#include <net/if.h>
+
+#include <machine/i4b_debug.h>
+#include <machine/i4b_ioctl.h>
+#include <machine/i4b_trace.h>
+
+#include <i4b/include/i4b_global.h>
+#include <i4b/include/i4b_mbuf.h>
+
+#include <i4b/layer1/i4b_l1.h>
+#include <i4b/layer1/isic/i4b_isic.h>
+/*#include <i4b/layer1/isic/i4b_isac.h>*/
+#include <i4b/layer1/isic/i4b_hscx.h>
+
+#include <i4b/layer1/ifpi2/i4b_ifpi2_ext.h>
+#include <i4b/layer1/ifpi2/i4b_ifpi2_isacsx.h>
+
+#define PCI_AVMA1_VID 0x1244
+#define PCI_AVMA1_V2_DID 0x0e00
+
+/* prototypes */
+static void avma1pp2_disable(device_t);
+
+static void avma1pp2_intr(void *);
+static void hscx_write_reg(int, u_int, struct l1_softc *);
+static u_char hscx_read_reg(int, struct l1_softc *);
+static u_int hscx_read_reg_int(int, struct l1_softc *);
+static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
+static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
+static void avma1pp2_hscx_int_handler(struct l1_softc *);
+static void avma1pp2_hscx_intr(int, u_int, struct l1_softc *);
+static void avma1pp2_init_linktab(struct l1_softc *);
+static void avma1pp2_bchannel_setup(int, int, int, int);
+static void avma1pp2_bchannel_start(int, int);
+static void avma1pp2_hscx_init(struct l1_softc *, int, int);
+static void avma1pp2_bchannel_stat(int, int, bchan_statistics_t *);
+static void avma1pp2_set_linktab(int, int, drvr_link_t *);
+static isdn_link_t * avma1pp2_ret_linktab(int, int);
+static int avma1pp2_pci_probe(device_t);
+static int avma1pp2_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
+int avma1pp2_attach_avma1pp(device_t);
+static void ifpi2_isacsx_intr(struct l1_softc *sc);
+
+static device_method_t avma1pp2_pci_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		avma1pp2_pci_probe),
+	DEVMETHOD(device_attach,	avma1pp2_attach_avma1pp),
+	DEVMETHOD(device_shutdown,	avma1pp2_disable),
+
+	/* bus interface */
+	DEVMETHOD(bus_print_child,	bus_generic_print_child),
+	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
+
+	{ 0, 0 }
+};
+
+static driver_t avma1pp2_pci_driver = {
+	"ifpi2",
+	avma1pp2_pci_methods,
+	sizeof(struct l1_softc)
+};
+
+static devclass_t avma1pp2_pci_devclass;
+
+DRIVER_MODULE(avma1pp2, pci, avma1pp2_pci_driver, avma1pp2_pci_devclass, 0, 0);
+
+/* jump table for multiplex routines */
+
+struct i4b_l1mux_func avma1pp2_l1mux_func = {
+	avma1pp2_ret_linktab,
+	avma1pp2_set_linktab,
+	ifpi2_mph_command_req,
+	ifpi2_ph_data_req,
+	ifpi2_ph_activate_req,
+};
+
+struct l1_softc *ifpi2_scp[IFPI2_MAXUNIT];
+
+/*---------------------------------------------------------------------------*
+ *	AVM PCI Fritz!Card V. 2 special registers
+ *---------------------------------------------------------------------------*/
+
+/*
+ *	AVM PCI Status Latch 0 read only bits
+ */
+#define ASL_IRQ_ISAC            0x01    /* ISAC  interrupt, active high */
+#define ASL_IRQ_HSCX            0x02    /* HSX   interrupt, active high */
+#define ASL_IRQ_TIMER           0x04    /* Timer interrupt, active high */
+#define ASL_IRQ_BCHAN           ASL_IRQ_HSCX
+/* actually active high */
+#define ASL_IRQ_Pending         (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
+
+/*
+ *	AVM PCI Status Latch 0 read only bits
+ */
+#define ASL_TIMERRESET 		0x04
+#define ASL_ENABLE_INT		0x08
+
+/*
+ * "HSCX" status bits
+ */
+#define  HSCX_STAT_RME		0x01
+#define  HSCX_STAT_RDO		0x10
+#define  HSCX_STAT_CRCVFRRAB	0x0E
+#define  HSCX_STAT_CRCVFR	0x06
+#define  HSCX_STAT_RML_MASK	0x3f00
+
+/*
+ * "HSCX" interrupt bits
+ */
+#define  HSCX_INT_XPR		0x80
+#define  HSCX_INT_XDU		0x40
+#define  HSCX_INT_RPR		0x20
+#define  HSCX_INT_MASK		0xE0
+
+/*
+ * "HSCX" command bits
+ */
+#define  HSCX_CMD_XRS		0x80
+#define  HSCX_CMD_XME		0x01
+#define  HSCX_CMD_RRS		0x20
+#define  HSCX_CMD_XML_MASK	0x3f00
+
+/* "HSCX" mode bits */
+#define HSCX_MODE_ITF_FLG 	0x01
+#define HSCX_MODE_TRANS 	0x02
+
+/* offsets to various registers in the ASIC, evidently */
+#define  STAT0_OFFSET   	0x02
+
+#define  HSCX_FIFO1     	0x10
+#define  HSCX_FIFO2     	0x18
+
+#define  HSCX_STAT1     	0x14
+#define  HSCX_STAT2     	0x1c
+
+#define  ISACSX_INDEX   	0x04
+#define  ISACSX_DATA    	0x08
+
+/*
+ * Commands and parameters are sent to the "HSCX" as a long, but the
+ * fields are handled as bytes.
+ *
+ * The long contains:
+ *	(prot << 16)|(txl << 8)|cmd
+ *
+ * where:
+ *	prot = protocol to use
+ *	txl = transmit length
+ *	cmd = the command to be executed
+ *
+ * The fields are defined as u_char in struct l1_softc.
+ *
+ * Macro to coalesce the byte fields into a u_int
+ */
+#define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
+ 					| (sc->avma1pp_prot << 16))
+
+/*
+ * to prevent deactivating the "HSCX" when both channels are active we
+ * define an HSCX_ACTIVE flag which is or'd into the channel's state
+ * flag in avma1pp2_bchannel_setup upon active and cleared upon deactivation.
+ * It is set high to allow room for new flags.
+ */
+#define HSCX_AVMA1PP_ACTIVE	0x1000 
+
+/*---------------------------------------------------------------------------*
+ *	AVM read fifo routines
+ *---------------------------------------------------------------------------*/
+
+static void
+avma1pp2_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
+{
+	bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
+	bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]); 
+	int i;
+
+	switch (what) {
+		case ISIC_WHAT_ISAC:
+			bus_space_write_4(btag, bhandle, ISACSX_INDEX, 0);
+			/* evidently each byte must be read as a long */
+			for (i = 0; i < size; i++)
+				((u_int8_t *)buf)[i] = (u_int8_t)bus_space_read_4(btag, bhandle, ISACSX_DATA);
+			break;
+		case ISIC_WHAT_HSCXA:
+			hscx_read_fifo(0, buf, size, sc);
+			break;
+		case ISIC_WHAT_HSCXB:
+			hscx_read_fifo(1, buf, size, sc);
+			break;
+	}
+}
+
+static void
+hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
+{
+	u_int32_t *ip;
+	size_t cnt;
+	int dataoff;
+	bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
+	bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]); 
+
+	dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
+	
+	ip = (u_int32_t *)buf;
+	cnt = 0;
+	/* what if len isn't a multiple of sizeof(int) and buf is */
+	/* too small ???? */
+	while (cnt < len)
+	{
+		*ip++ = bus_space_read_4(btag, bhandle, dataoff);
+		cnt += 4;
+	}
+}
+
+/*---------------------------------------------------------------------------*
+ *	AVM write fifo routines
+ *---------------------------------------------------------------------------*/
+static void
+avma1pp2_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
+{
+	bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
+	bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]); 
+	int i;
+
+	switch (what) {
+		case ISIC_WHAT_ISAC:
+			bus_space_write_4(btag, bhandle,  ISACSX_INDEX, 0);
+			/* evidently each byte must written as a long */
+			for (i = 0; i < size; i++)
+				bus_space_write_4(btag, bhandle,  ISACSX_DATA, ((unsigned char *)buf)[i]);
+			break;
+		case ISIC_WHAT_HSCXA:
+			hscx_write_fifo(0, buf, size, sc);
+			break;
+		case ISIC_WHAT_HSCXB:
+			hscx_write_fifo(1, buf, size, sc);
+			break;
+	}
+}
+
+static void
+hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
+{
+	u_int32_t *ip;
+	size_t cnt;
+	int dataoff;
+	l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
+	bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
+	bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]); 
+
+	dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
+	
+	sc->avma1pp_cmd &= ~HSCX_CMD_XME;
+	sc->avma1pp_txl = 0;
+	if (Bchan->out_mbuf_cur == NULL)
+	{
+	  if (Bchan->bprot != BPROT_NONE)
+		 sc->avma1pp_cmd |= HSCX_CMD_XME;
+	}
+	if (len != sc->sc_bfifolen)
+		sc->avma1pp_txl = len;
+	
+	cnt = 0; /* borrow cnt */
+	AVMA1PPSETCMDLONG(cnt);
+	hscx_write_reg(chan, cnt, sc);
+
+	ip = (u_int32_t *)buf;
+	cnt = 0;
+	while (cnt < len)
+	{
+		bus_space_write_4(btag, bhandle, dataoff, *ip);
+		ip++;
+		cnt += 4;
+	}
+}
+
+/*---------------------------------------------------------------------------*
+ *	AVM write register routines
+ *---------------------------------------------------------------------------*/
+
+static void
+avma1pp2_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
+{
+	bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
+	bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]); 
+
+	switch (what) {
+		case ISIC_WHAT_ISAC:
+			bus_space_write_4(btag, bhandle, ISACSX_INDEX, offs);
+			bus_space_write_4(btag, bhandle, ISACSX_DATA, data);
+			break;
+		case ISIC_WHAT_HSCXA:
+			hscx_write_reg(0, data, sc);
+			break;
+		case ISIC_WHAT_HSCXB:
+			hscx_write_reg(1, data, sc);
+			break;
+	}
+}
+
+static void
+hscx_write_reg(int chan, u_int val, struct l1_softc *sc)
+{
+	bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
+	bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]); 
+	u_int off;
+
+	off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
+
+	bus_space_write_4(btag, bhandle, off, val);
+}
+
+/*---------------------------------------------------------------------------*
+ *	AVM read register routines
+ *---------------------------------------------------------------------------*/
+static u_int8_t
+avma1pp2_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
+{
+	bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
+	bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]); 
+	u_int8_t val;
+
+	switch (what) {
+		case ISIC_WHAT_ISAC:
+			bus_space_write_4(btag, bhandle, ISACSX_INDEX, offs);
+			val = (u_int8_t)bus_space_read_4(btag, bhandle, ISACSX_DATA);
+			return(val);
+		case ISIC_WHAT_HSCXA:
+			return hscx_read_reg(0, sc);
+		case ISIC_WHAT_HSCXB:
+			return hscx_read_reg(1, sc);
+	}
+	return 0;
+}
+
+static u_char
+hscx_read_reg(int chan, struct l1_softc *sc)
+{
+	return(hscx_read_reg_int(chan, sc) & 0xff);
+}
+
+/*
+ * need to be able to return an int because the RBCH is in the 2nd
+ * byte.
+ */
+static u_int
+hscx_read_reg_int(int chan, struct l1_softc *sc)
+{
+	bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
+	bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]); 
+	u_int off;
+
+	off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
+	return(bus_space_read_4(btag, bhandle, off));
+}
+
+/*---------------------------------------------------------------------------*
+ *	avma1pp2_probe - probe for a card
+ *---------------------------------------------------------------------------*/
+static int
+avma1pp2_pci_probe(dev)
+	device_t		dev;
+{
+	u_int16_t		did, vid;
+
+	vid = pci_get_vendor(dev);
+	did = pci_get_device(dev);
+
+	if ((vid == PCI_AVMA1_VID) && (did == PCI_AVMA1_V2_DID)) {
+		device_set_desc(dev, "AVM Fritz!Card PCI Version 2");
+		return(0);
+	}
+
+	return(ENXIO);
+}
+
+/*---------------------------------------------------------------------------*
+ *	avma1pp2_attach_avma1pp - attach Fritz!Card PCI
+ *---------------------------------------------------------------------------*/
+int
+avma1pp2_attach_avma1pp(device_t dev)
+{
+	struct l1_softc *sc;
+	u_int v;
+	int unit, error = 0;
+	int s;
+	u_int16_t did, vid;
+	void *ih = 0;
+	bus_space_handle_t bhandle;
+	bus_space_tag_t btag; 
+	l1_bchan_state_t *chan;
+
+	s = splimp();
+
+	vid = pci_get_vendor(dev);
+	did = pci_get_device(dev);
+	sc = device_get_softc(dev);
+	unit = device_get_unit(dev);
+	bzero(sc, sizeof(struct l1_softc));
+
+	/* probably not really required */
+	if(unit > IFPI2_MAXUNIT) {
+		printf("avma1pp2-%d: Error, unit > IFPI_MAXUNIT!\n", unit);
+		splx(s);
+		return(ENXIO);
+	}
+
+	if ((vid != PCI_AVMA1_VID) && (did != PCI_AVMA1_V2_DID)) {
+		printf("avma1pp2-%d: unknown device!?\n", unit);
+		goto fail;
+	}
+
+	ifpi2_scp[unit] = sc;
+
+	sc->sc_resources.io_rid[0] = PCIR_MAPS+4;
+	sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
+		&sc->sc_resources.io_rid[0],
+		0, ~0, 1, RF_ACTIVE);
+
+	if (sc->sc_resources.io_base[0] == NULL) {
+		printf("avma1pp2-%d: couldn't map IO port\n", unit);
+		error = ENXIO;
+		goto fail;
+	}
+
+	bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
+	btag = rman_get_bustag(sc->sc_resources.io_base[0]); 
+
+	/* Allocate interrupt */
+	sc->sc_resources.irq_rid = 0;
+	sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
+		&sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
+
+	if (sc->sc_resources.irq == NULL) {
+		bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
+		printf("avma1pp2-%d: couldn't map interrupt\n", unit);
+		error = ENXIO;
+		goto fail;
+	}
+
+	error = bus_setup_intr(dev, sc->sc_resources.irq, INTR_TYPE_NET, avma1pp2_intr, sc, &ih);
+
+	if (error) {
+		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
+		bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
+		printf("avma1pp2-%d: couldn't set up irq\n", unit);
+		goto fail;
+	}
+
+	sc->sc_unit = unit;
+
+	/* end of new-bus stuff */
+
+	ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
+
+	HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
+	HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
+
+	/* setup access routines */
+
+	sc->clearirq = NULL;
+	sc->readreg = avma1pp2_read_reg;
+	sc->writereg = avma1pp2_write_reg;
+
+	sc->readfifo = avma1pp2_read_fifo;
+	sc->writefifo = avma1pp2_write_fifo;
+
+	/* setup card type */
+	
+	sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI_V2;
+
+	/* setup IOM bus type */
+	
+	sc->sc_bustyp = BUS_TYPE_IOM2;
+
+	/* set up some other miscellaneous things */
+	sc->sc_ipac = 0;
+	sc->sc_bfifolen = HSCX_FIFO_LEN;
+
+	/* reset the card */
+	/* the Linux driver does this to clear any pending ISAC interrupts */
+	v = 0;
+	v = ISAC_READ(I_RMODED);
+#ifdef AVMA1PCI_V2_DEBUG
+	printf("avma1pp2_attach: I_MODED %x...", v);
+#endif
+	v = ISAC_READ(I_ISTAD);
+#ifdef AVMA1PCI_V2_DEBUG
+	printf("avma1pp2_attach: I_ISTAD %x...", v);
+#endif
+	v = ISAC_READ(I_ISTA);
+#ifdef AVMA1PCI_V2_DEBUG
+	printf("avma1pp2_attach: I_ISTA %x...", v);
+#endif
+	ISAC_WRITE(I_MASKD, 0xff);
+	ISAC_WRITE(I_MASK, 0xff);
+	/* the Linux driver does this to clear any pending HSCX interrupts */
+	v = hscx_read_reg_int(0, sc);
+#ifdef AVMA1PCI_V2_DEBUG
+	printf("avma1pp2_attach: 0 HSCX_STAT %x...", v);
+#endif
+	v = hscx_read_reg_int(1, sc);
+#ifdef AVMA1PCI_V2_DEBUG
+	printf("avma1pp2_attach: 1 HSCX_STAT %x\n", v);
+#endif
+
+	bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET);
+	DELAY(SEC_DELAY/100); /* 10 ms */
+	bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_ENABLE_INT);
+	DELAY(SEC_DELAY/100); /* 10 ms */
+
+   /* from here to the end would normally be done in isic_pciattach */
+
+	 printf("ifpi2-%d: ISACSX %s\n", unit, "PSB3186");
+
+	/* init the ISAC */
+	ifpi2_isacsx_init(sc);
+
+#if defined (__FreeBSD__) && __FreeBSD__ > 4
+	/* Init the channel mutexes */
+	chan = &sc->sc_chan[HSCX_CH_A];
+	mtx_init(&chan->rx_queue.ifq_mtx, "i4b_avma1pp2_rx", MTX_DEF);
+	mtx_init(&chan->tx_queue.ifq_mtx, "i4b_avma1pp2_tx", MTX_DEF);
+	chan = &sc->sc_chan[HSCX_CH_B];
+	mtx_init(&chan->rx_queue.ifq_mtx, "i4b_avma1pp2_rx", MTX_DEF);
+	mtx_init(&chan->tx_queue.ifq_mtx, "i4b_avma1pp2_tx", MTX_DEF);
+#endif
+
+	/* init the "HSCX" */
+	avma1pp2_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
+	
+	avma1pp2_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
+
+	/* can't use the normal B-Channel stuff */
+	avma1pp2_init_linktab(sc);
+
+	/* set trace level */
+
+	sc->sc_trace = TRACE_OFF;
+
+	sc->sc_state = ISAC_IDLE;
+
+	sc->sc_ibuf = NULL;
+	sc->sc_ib = NULL;
+	sc->sc_ilen = 0;
+
+	sc->sc_obuf = NULL;
+	sc->sc_op = NULL;
+	sc->sc_ol = 0;
+	sc->sc_freeflag = 0;
+
+	sc->sc_obuf2 = NULL;
+	sc->sc_freeflag2 = 0;
+
+#if defined(__FreeBSD__) && __FreeBSD__ >=3
+	callout_handle_init(&sc->sc_T3_callout);
+	callout_handle_init(&sc->sc_T4_callout);	
+#endif
+	
+	/* init higher protocol layers */
+	
+	i4b_l1_mph_status_ind(L0IFPI2UNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avma1pp2_l1mux_func);
+
+  fail:
+	splx(s);
+	return(error);
+}
+
+/*
+ * this is the real interrupt routine
+ */
+static void
+avma1pp2_hscx_intr(int h_chan, u_int stat, struct l1_softc *sc)
+{
+	register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
+	int activity = -1;
+	u_int param = 0;
+	
+	NDBGL1(L1_H_IRQ, "%#x", stat);
+
+	if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
+	{
+		chan->stat_XDU++;			
+		NDBGL1(L1_H_XFRERR, "xmit data underrun");
+		/* abort the transmission */
+		sc->avma1pp_txl = 0;
+		sc->avma1pp_cmd |= HSCX_CMD_XRS;
+		AVMA1PPSETCMDLONG(param);
+		hscx_write_reg(h_chan, param, sc);
+		sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
+		AVMA1PPSETCMDLONG(param);
+		hscx_write_reg(h_chan, param, sc);
+
+		if (chan->out_mbuf_head != NULL)  /* don't continue to transmit this buffer */
+		{
+			i4b_Bfreembuf(chan->out_mbuf_head);
+			chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
+		}
+	}
+
+	/*
+	 * The following is based on examination of the Linux driver.
+	 *
+	 * The logic here is different than with a "real" HSCX; all kinds
+	 * of information (interrupt/status bits) are in stat.
+	 *		HSCX_INT_RPR indicates a receive interrupt
+	 *			HSCX_STAT_RDO indicates an overrun condition, abort -
+	 *			otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
+	 *			HSCX_STAT_RME indicates end-of-frame and apparently any
+	 *			CRC/framing errors are only reported in this state.
+	 *				if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
+	 *					CRC/framing error
+	 */
+	
+	if(stat & HSCX_INT_RPR)
+	{
+		register int fifo_data_len;
+		int error = 0;
+		/* always have to read the FIFO, so use a scratch buffer */
+		u_char scrbuf[HSCX_FIFO_LEN];
+
+		if(stat & HSCX_STAT_RDO)
+		{
+			chan->stat_RDO++;
+			NDBGL1(L1_H_XFRERR, "receive data overflow");
+			error++;				
+		}
+
+		/*
+		 * check whether we're receiving data for an inactive B-channel
+		 * and discard it. This appears to happen for telephony when
+		 * both B-channels are active and one is deactivated. Since
+		 * it is not really possible to deactivate the channel in that
+		 * case (the ASIC seems to deactivate _both_ channels), the
+		 * "deactivated" channel keeps receiving data which can lead
+		 * to exhaustion of mbufs and a kernel panic.
+		 *
+		 * This is a hack, but it's the only solution I can think of
+		 * without having the documentation for the ASIC.
+		 * GJ - 28 Nov 1999
+		 */
+		 if (chan->state == HSCX_IDLE)
+		 {
+			NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
+			error++;
+		 }
+
+		fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
+		
+		if(fifo_data_len == 0)
+			fifo_data_len = sc->sc_bfifolen;
+
+		/* ALWAYS read data from HSCX fifo */
+	
+		HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
+		chan->rxcount += fifo_data_len;
+
+		/* all error conditions checked, now decide and take action */
+		
+		if(error == 0)
+		{
+			if(chan->in_mbuf == NULL)
+			{
+				if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
+					panic("L1 avma1pp2_hscx_intr: RME, cannot allocate mbuf!\n");
+				chan->in_cbptr = chan->in_mbuf->m_data;
+				chan->in_len = 0;
+			}
+
+			if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
+			{
+			   	/* OK to copy the data */
+				bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
+				chan->in_cbptr += fifo_data_len;
+				chan->in_len += fifo_data_len;
+
+				/* setup mbuf data length */
+					
+				chan->in_mbuf->m_len = chan->in_len;
+				chan->in_mbuf->m_pkthdr.len = chan->in_len;
+
+				if(sc->sc_trace & TRACE_B_RX)
+				{
+					i4b_trace_hdr_t hdr;
+					hdr.unit = L0IFPIUNIT(sc->sc_unit);
+					hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
+					hdr.dir = FROM_NT;
+					hdr.count = ++sc->sc_trace_bcount;
+					MICROTIME(hdr.time);
+					i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
+				}
+
+				if (stat & HSCX_STAT_RME)
+				{
+				  if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
+				  {
+					 (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
+					 activity = ACT_RX;
+				
+					 /* mark buffer ptr as unused */
+					
+					 chan->in_mbuf = NULL;
+					 chan->in_cbptr = NULL;
+					 chan->in_len = 0;
+				  }
+				  else
+				  {
+						chan->stat_CRC++;
+						NDBGL1(L1_H_XFRERR, "CRC/RAB");
+					  if (chan->in_mbuf != NULL)
+					  {
+						  i4b_Bfreembuf(chan->in_mbuf);
+						  chan->in_mbuf = NULL;
+						  chan->in_cbptr = NULL;
+						  chan->in_len = 0;
+					  }
+				  }
+				}
+			} /* END enough space in mbuf */
+			else
+			{
+				 if(chan->bprot == BPROT_NONE)
+				 {
+					  /* setup mbuf data length */
+				
+					  chan->in_mbuf->m_len = chan->in_len;
+					  chan->in_mbuf->m_pkthdr.len = chan->in_len;
+
+					  if(sc->sc_trace & TRACE_B_RX)
+					  {
+							i4b_trace_hdr_t hdr;
+							hdr.unit = L0IFPIUNIT(sc->sc_unit);
+							hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
+							hdr.dir = FROM_NT;
+							hdr.count = ++sc->sc_trace_bcount;
+							MICROTIME(hdr.time);
+							i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
+						}
+
+					  if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
+						 activity = ACT_RX;
+				
+					  /* move rx'd data to rx queue */
+
+#if defined (__FreeBSD__) && __FreeBSD__ > 4
+					  (void) IF_HANDOFF(&chan->rx_queue, chan->in_mbuf, NULL);
+#else
+					  if(!(IF_QFULL(&chan->rx_queue)))
+					  {
+						IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
+					  }
+					  else
+					  {
+						i4b_Bfreembuf(chan->in_mbuf);
+					  }
+#endif					
+					  /* signal upper layer that data are available */
+					  (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
+
+					  /* alloc new buffer */
+				
+					  if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
+						 panic("L1 avma1pp2_hscx_intr: RPF, cannot allocate new mbuf!\n");
+	
+					  /* setup new data ptr */
+				
+					  chan->in_cbptr = chan->in_mbuf->m_data;
+	
+					  /* OK to copy the data */
+					  bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
+
+					  chan->in_cbptr += fifo_data_len;
+					  chan->in_len = fifo_data_len;
+
+					  chan->rxcount += fifo_data_len;
+					}
+				 else
+					{
+					  NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
+					  chan->in_cbptr = chan->in_mbuf->m_data;
+					  chan->in_len = 0;
+					}
+			  }
+		} /* if(error == 0) */
+		else
+		{
+		  	/* land here for RDO */
+			if (chan->in_mbuf != NULL)
+			{
+				i4b_Bfreembuf(chan->in_mbuf);
+				chan->in_mbuf = NULL;
+				chan->in_cbptr = NULL;
+				chan->in_len = 0;
+			}
+			sc->avma1pp_txl = 0;
+			sc->avma1pp_cmd |= HSCX_CMD_RRS;
+			AVMA1PPSETCMDLONG(param);
+			hscx_write_reg(h_chan, param, sc);
+			sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
+			AVMA1PPSETCMDLONG(param);
+			hscx_write_reg(h_chan, param, sc);
+		}
+	}
+
+
+	/* transmit fifo empty, new data can be written to fifo */
+	
+	if(stat & HSCX_INT_XPR)
+	{
+		/*
+		 * for a description what is going on here, please have
+		 * a look at isic_bchannel_start() in i4b_bchan.c !
+		 */
+
+		NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
+
+		if(chan->out_mbuf_cur == NULL) 	/* last frame is transmitted */
+		{
+			IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
+
+			if(chan->out_mbuf_head == NULL)
+			{
+				chan->state &= ~HSCX_TX_ACTIVE;
+				(*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
+			}
+			else
+			{
+				chan->state |= HSCX_TX_ACTIVE;
+				chan->out_mbuf_cur = chan->out_mbuf_head;
+				chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
+				chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
+
+				if(sc->sc_trace & TRACE_B_TX)
+				{
+					i4b_trace_hdr_t hdr;
+					hdr.unit = L0IFPIUNIT(sc->sc_unit);
+					hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
+					hdr.dir = FROM_TE;
+					hdr.count = ++sc->sc_trace_bcount;
+					MICROTIME(hdr.time);
+					i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
+				}
+				
+				if(chan->bprot == BPROT_NONE)
+				{
+					if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
+						activity = ACT_TX;
+				}
+				else
+				{
+					activity = ACT_TX;
+				}
+			}
+		}
+			
+		avma1pp2_hscx_fifo(chan, sc);
+	}
+
+	/* call timeout handling routine */
+	
+	if(activity == ACT_RX || activity == ACT_TX)
+		(*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
+}
+
+/*
+ * this is the main routine which checks each channel and then calls
+ * the real interrupt routine as appropriate
+ */
+static void
+avma1pp2_hscx_int_handler(struct l1_softc *sc)
+{
+	u_int stat;
+
+	/* has to be a u_int because the byte count is in the 2nd byte */
+	stat = hscx_read_reg_int(0, sc);
+	if (stat & HSCX_INT_MASK)
+	  avma1pp2_hscx_intr(0, stat, sc);
+	stat = hscx_read_reg_int(1, sc);
+	if (stat & HSCX_INT_MASK)
+	  avma1pp2_hscx_intr(1, stat, sc);
+}
+
+static void
+avma1pp2_disable(device_t dev)
+{
+	struct l1_softc *sc = device_get_softc(dev);
+	bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
+	bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]); 
+
+	/* could be wrong */
+	bus_space_write_1(btag, bhandle, STAT0_OFFSET, 0x07);
+}
+
+static void
+avma1pp2_intr(void *xsc)
+{
+	u_char stat;
+	struct l1_softc *sc;
+	bus_space_handle_t bhandle;
+	bus_space_tag_t btag; 
+
+	sc = xsc;
+	bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
+	btag = rman_get_bustag(sc->sc_resources.io_base[0]); 
+
+	stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
+	NDBGL1(L1_H_IRQ, "stat %x", stat);
+	/* was there an interrupt from this card ? */
+	if ((stat & ASL_IRQ_Pending) == 0)
+		return; /* no */
+	/* interrupts are high active */
+	if (stat & ASL_IRQ_TIMER)
+	  NDBGL1(L1_H_IRQ, "timer interrupt ???");
+	if (stat & ASL_IRQ_HSCX)
+	{
+	  NDBGL1(L1_H_IRQ, "HSCX");
+		avma1pp2_hscx_int_handler(sc);
+	}
+	if (stat & ASL_IRQ_ISAC)
+	{
+	  NDBGL1(L1_H_IRQ, "ISAC");
+		ifpi2_isacsx_intr(sc);
+	}
+}
+
+static void
+avma1pp2_hscx_init(struct l1_softc *sc, int h_chan, int activate)
+{
+	l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
+	u_int param = 0;
+
+	NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
+		sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
+
+	sc->avma1pp_cmd = sc->avma1pp_prot = sc->avma1pp_txl = 0;
+
+	if (activate == 0)
+	{
+		/* only deactivate if both channels are idle */
+		if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
+			sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
+		{
+			return;
+		}
+		sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
+		sc->avma1pp_prot = HSCX_MODE_TRANS;
+		AVMA1PPSETCMDLONG(param);
+		hscx_write_reg(h_chan, param, sc);
+		return;
+	}
+	if(chan->bprot == BPROT_RHDLC)
+	{
+		  NDBGL1(L1_BCHAN, "BPROT_RHDLC");
+
+		/* HDLC Frames, transparent mode 0 */
+		sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
+		sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
+		AVMA1PPSETCMDLONG(param);
+		hscx_write_reg(h_chan, param, sc);
+		sc->avma1pp_cmd = HSCX_CMD_XRS;
+		AVMA1PPSETCMDLONG(param);
+		hscx_write_reg(h_chan, param, sc);
+		sc->avma1pp_cmd = 0;
+	}
+	else
+	{
+		  NDBGL1(L1_BCHAN, "BPROT_NONE??");
+
+		/* Raw Telephony, extended transparent mode 1 */
+		sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
+		sc->avma1pp_prot = HSCX_MODE_TRANS;
+		AVMA1PPSETCMDLONG(param);
+		hscx_write_reg(h_chan, param, sc);
+		sc->avma1pp_cmd = HSCX_CMD_XRS;
+		AVMA1PPSETCMDLONG(param);
+		hscx_write_reg(h_chan, param, sc);
+		sc->avma1pp_cmd = 0;
+	}
+}
+
+static void
+avma1pp2_bchannel_setup(int unit, int h_chan, int bprot, int activate)
+{
+#ifdef __FreeBSD__
+	struct l1_softc *sc = ifpi2_scp[unit];
+#else
+	struct l1_softc *sc = isic_find_sc(unit);
+#endif
+	l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
+
+	int s = SPLI4B();
+	
+	if(activate == 0)
+	{
+		/* deactivation */
+		chan->state = HSCX_IDLE;
+		avma1pp2_hscx_init(sc, h_chan, activate);
+	}
+		
+	NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
+		sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
+
+	/* general part */
+
+	chan->unit = sc->sc_unit;	/* unit number */
+	chan->channel = h_chan;		/* B channel */
+	chan->bprot = bprot;		/* B channel protocol */
+	chan->state = HSCX_IDLE;	/* B channel state */
+
+	/* receiver part */
+
+	chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
+
+	i4b_Bcleanifq(&chan->rx_queue);	/* clean rx queue */
+
+	chan->rxcount = 0;		/* reset rx counter */
+	
+	i4b_Bfreembuf(chan->in_mbuf);	/* clean rx mbuf */
+
+	chan->in_mbuf = NULL;		/* reset mbuf ptr */
+	chan->in_cbptr = NULL;		/* reset mbuf curr ptr */
+	chan->in_len = 0;		/* reset mbuf data len */
+	
+	/* transmitter part */
+
+	chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
+	
+	i4b_Bcleanifq(&chan->tx_queue);	/* clean tx queue */
+
+	chan->txcount = 0;		/* reset tx counter */
+	
+	i4b_Bfreembuf(chan->out_mbuf_head);	/* clean tx mbuf */
+
+	chan->out_mbuf_head = NULL;	/* reset head mbuf ptr */
+	chan->out_mbuf_cur = NULL;	/* reset current mbuf ptr */	
+	chan->out_mbuf_cur_ptr = NULL;	/* reset current mbuf data ptr */
+	chan->out_mbuf_cur_len = 0;	/* reset current mbuf data cnt */
+	
+	if(activate != 0)
+	{
+		/* activation */
+		avma1pp2_hscx_init(sc, h_chan, activate);
+		chan->state |= HSCX_AVMA1PP_ACTIVE;
+	}
+
+	splx(s);
+}
+
+static void
+avma1pp2_bchannel_start(int unit, int h_chan)
+{
+#ifdef __FreeBSD__
+	struct l1_softc *sc = ifpi2_scp[unit];
+#else
+	struct l1_softc *sc = isic_find_sc(unit);
+#endif
+	register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
+	int s;
+	int activity = -1;
+
+	s = SPLI4B();				/* enter critical section */
+	if(chan->state & HSCX_TX_ACTIVE)	/* already running ? */
+	{
+		splx(s);
+		return;				/* yes, leave */
+	}
+
+	/* get next mbuf from queue */
+	
+	IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
+	
+	if(chan->out_mbuf_head == NULL)		/* queue empty ? */
+	{
+		splx(s);			/* leave critical section */
+		return;				/* yes, exit */
+	}
+
+	/* init current mbuf values */
+	
+	chan->out_mbuf_cur = chan->out_mbuf_head;
+	chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
+	chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;	
+	
+	/* activity indicator for timeout handling */
+
+	if(chan->bprot == BPROT_NONE)
+	{
+		if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
+			activity = ACT_TX;
+	}
+	else
+	{
+		activity = ACT_TX;
+	}
+
+	chan->state |= HSCX_TX_ACTIVE;		/* we start transmitting */
+	
+	if(sc->sc_trace & TRACE_B_TX)	/* if trace, send mbuf to trace dev */
+	{
+		i4b_trace_hdr_t hdr;
+		hdr.unit = L0IFPIUNIT(sc->sc_unit);
+		hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
+		hdr.dir = FROM_TE;
+		hdr.count = ++sc->sc_trace_bcount;
+		MICROTIME(hdr.time);
+		i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
+	}			
+
+	avma1pp2_hscx_fifo(chan, sc);
+
+	/* call timeout handling routine */
+	
+	if(activity == ACT_RX || activity == ACT_TX)
+		(*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
+
+	splx(s);	
+}
+
+/*---------------------------------------------------------------------------*
+ *	return the address of isic drivers linktab	
+ *---------------------------------------------------------------------------*/
+static isdn_link_t *
+avma1pp2_ret_linktab(int unit, int channel)
+{
+#ifdef __FreeBSD__
+	struct l1_softc *sc = ifpi2_scp[unit];
+#else
+	struct l1_softc *sc = isic_find_sc(unit);
+#endif
+	l1_bchan_state_t *chan = &sc->sc_chan[channel];
+
+	return(&chan->isic_isdn_linktab);
+}
+ 
+/*---------------------------------------------------------------------------*
+ *	set the driver linktab in the b channel softc
+ *---------------------------------------------------------------------------*/
+static void
+avma1pp2_set_linktab(int unit, int channel, drvr_link_t *dlt)
+{
+#ifdef __FreeBSD__
+	struct l1_softc *sc = ifpi2_scp[unit];
+#else
+	struct l1_softc *sc = isic_find_sc(unit);
+#endif
+	l1_bchan_state_t *chan = &sc->sc_chan[channel];
+
+	chan->isic_drvr_linktab = dlt;
+}
+
+
+/*---------------------------------------------------------------------------*
+ *	initialize our local linktab
+ *---------------------------------------------------------------------------*/
+static void
+avma1pp2_init_linktab(struct l1_softc *sc)
+{
+	l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
+	isdn_link_t *lt = &chan->isic_isdn_linktab;
+
+	/* make sure the hardware driver is known to layer 4 */
+	/* avoid overwriting if already set */
+	if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
+	{
+		ctrl_types[CTRL_PASSIVE].set_linktab = avma1pp2_set_linktab;
+		ctrl_types[CTRL_PASSIVE].get_linktab = avma1pp2_ret_linktab;
+	}
+
+	/* local setup */
+	lt->unit = sc->sc_unit;
+	lt->channel = HSCX_CH_A;
+	lt->bch_config = avma1pp2_bchannel_setup;
+	lt->bch_tx_start = avma1pp2_bchannel_start;
+	lt->bch_stat = avma1pp2_bchannel_stat;
+	lt->tx_queue = &chan->tx_queue;
+
+	/* used by non-HDLC data transfers, i.e. telephony drivers */
+	lt->rx_queue = &chan->rx_queue;
+
+	/* used by HDLC data transfers, i.e. ipr and isp drivers */	
+	lt->rx_mbuf = &chan->in_mbuf;	
+                                                
+	chan = &sc->sc_chan[HSCX_CH_B];
+	lt = &chan->isic_isdn_linktab;
+
+	lt->unit = sc->sc_unit;
+	lt->channel = HSCX_CH_B;
+	lt->bch_config = avma1pp2_bchannel_setup;
+	lt->bch_tx_start = avma1pp2_bchannel_start;
+	lt->bch_stat = avma1pp2_bchannel_stat;
+	lt->tx_queue = &chan->tx_queue;
+
+	/* used by non-HDLC data transfers, i.e. telephony drivers */
+	lt->rx_queue = &chan->rx_queue;
+
+	/* used by HDLC data transfers, i.e. ipr and isp drivers */	
+	lt->rx_mbuf = &chan->in_mbuf;	
+}
+
+/*
+ * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
+ */
+static void
+avma1pp2_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
+{
+#ifdef __FreeBSD__
+	struct l1_softc *sc = ifpi2_scp[unit];
+#else
+	struct l1_softc *sc = isic_find_sc(unit);
+#endif
+	l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
+	int s;
+
+	s = SPLI4B();
+	
+	bsp->outbytes = chan->txcount;
+	bsp->inbytes = chan->rxcount;
+
+	chan->txcount = 0;
+	chan->rxcount = 0;
+
+	splx(s);
+}
+
+/*---------------------------------------------------------------------------*
+ *	fill HSCX fifo with data from the current mbuf
+ *	Put this here until it can go into i4b_hscx.c
+ *---------------------------------------------------------------------------*/
+static int
+avma1pp2_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
+{
+	int len;
+	int nextlen;
+	int i;
+	int cmd = 0;
+	/* using a scratch buffer simplifies writing to the FIFO */
+	u_char scrbuf[HSCX_FIFO_LEN];
+
+	len = 0;
+
+	/*
+	 * fill the HSCX tx fifo with data from the current mbuf. if
+	 * current mbuf holds less data than HSCX fifo length, try to
+	 * get the next mbuf from (a possible) mbuf chain. if there is
+	 * not enough data in a single mbuf or in a chain, then this
+	 * is the last mbuf and we tell the HSCX that it has to send
+	 * CRC and closing flag
+	 */
+	 
+	while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
+	{
+		nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
+
+#ifdef NOTDEF
+		printf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
+			chan->out_mbuf_head,
+			chan->out_mbuf_cur,			
+			chan->out_mbuf_cur_ptr,
+			chan->out_mbuf_cur_len,
+			len,
+			nextlen);
+#endif
+
+		cmd |= HSCX_CMDR_XTF;
+		/* collect the data in the scratch buffer */
+		for (i = 0; i < nextlen; i++)
+			scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
+
+		len += nextlen;
+		chan->txcount += nextlen;
+	
+		chan->out_mbuf_cur_ptr += nextlen;
+		chan->out_mbuf_cur_len -= nextlen;
+			
+		if(chan->out_mbuf_cur_len == 0) 
+		{
+			if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
+			{
+				chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
+				chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
+	
+				if(sc->sc_trace & TRACE_B_TX)
+				{
+					i4b_trace_hdr_t hdr;
+					hdr.unit = L0IFPIUNIT(sc->sc_unit);
+					hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
+					hdr.dir = FROM_TE;
+					hdr.count = ++sc->sc_trace_bcount;
+					MICROTIME(hdr.time);
+					i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
+				}
+			}
+			else
+			{
+				if (chan->bprot != BPROT_NONE)
+					cmd |= HSCX_CMDR_XME;
+				i4b_Bfreembuf(chan->out_mbuf_head);
+				chan->out_mbuf_head = NULL;
+			}
+		}
+	}
+	/* write what we have from the scratch buf to the HSCX fifo */
+	if (len != 0)
+		HSCX_WRFIFO(chan->channel, scrbuf, len);
+	return(cmd);
+}
+
+/*---------------------------------------------------------------------------*
+ *	ifpi2 - ISAC interrupt routine
+ *---------------------------------------------------------------------------*/
+static void
+ifpi2_isacsx_intr(struct l1_softc *sc)
+{
+	register u_char isacsx_irq_stat;
+
+	for(;;)
+	{
+		/* get isac irq status */
+		/* ISTA tells us whether it was a C/I or HDLC int. */
+		isacsx_irq_stat = ISAC_READ(I_ISTA);
+
+		if(isacsx_irq_stat)
+			ifpi2_isacsx_irq(sc, isacsx_irq_stat); /* isac handler */
+		else
+			break;
+	}
+
+	ISAC_WRITE(I_MASKD, 0xff);
+	ISAC_WRITE(I_MASK, 0xff);
+
+	DELAY(100);
+
+	ISAC_WRITE(I_MASKD, isacsx_imaskd);
+	ISAC_WRITE(I_MASK, isacsx_imask);
+}
+
+/*---------------------------------------------------------------------------*
+ *	ifpi2_recover - try to recover from irq lockup
+ *---------------------------------------------------------------------------*/
+void
+ifpi2_recover(struct l1_softc *sc)
+{
+	printf("ifpi2_recover %d\n", sc->sc_unit);
+#if 0 /* fix me later */
+	u_char byte;
+	
+	/* get isac irq status */
+
+	byte = ISAC_READ(I_ISTA);
+
+	NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
+	
+	if(byte & ISACSX_ISTA_EXI)
+		NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
+
+	if(byte & ISACSX_ISTA_CISQ)
+	{
+		byte = ISAC_READ(I_CIRR);
+	
+		NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
+		
+		if(byte & ISACSX_CIRR_SQC)
+			NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
+	}
+
+	NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISACSX_IMASK);
+
+	ISAC_WRITE(I_MASKD, 0xff);	
+	ISAC_WRITE(I_MASK, 0xff);	
+	DELAY(100);
+	ISAC_WRITE(I_MASKD, isacsx_imaskd);
+	ISAC_WRITE(I_MASK, isacsx_imask);
+#endif
+}
+
+
+#endif /* NIFPI2 > 0 */