diff options
| author | kib <kib@FreeBSD.org> | 2017-02-03 12:03:10 +0000 |
|---|---|---|
| committer | kib <kib@FreeBSD.org> | 2017-02-03 12:03:10 +0000 |
| commit | 0b7160d00d1511eafb8598877443090ed738b30e (patch) | |
| tree | bb6917be18c7074073ad0bfda9784c81f16da1b4 /sys/i386 | |
| parent | 5c75d73ea10112eca60a524a52b1a65118c3da39 (diff) | |
| download | FreeBSD-src-0b7160d00d1511eafb8598877443090ed738b30e.zip FreeBSD-src-0b7160d00d1511eafb8598877443090ed738b30e.tar.gz | |
MFC r312555:
Use SFENCE for ordering CLFLUSHOPT.
Diffstat (limited to 'sys/i386')
| -rw-r--r-- | sys/i386/i386/pmap.c | 16 | ||||
| -rw-r--r-- | sys/i386/include/cpufunc.h | 7 |
2 files changed, 17 insertions, 6 deletions
diff --git a/sys/i386/i386/pmap.c b/sys/i386/i386/pmap.c index a4a2169..60cfe47 100644 --- a/sys/i386/i386/pmap.c +++ b/sys/i386/i386/pmap.c @@ -1284,16 +1284,16 @@ pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force) return; #endif /* - * Otherwise, do per-cache line flush. Use the mfence + * Otherwise, do per-cache line flush. Use the sfence * instruction to insure that previous stores are * included in the write-back. The processor * propagates flush to other processors in the cache * coherence domain. */ - mfence(); + sfence(); for (; sva < eva; sva += cpu_clflush_line_size) clflushopt(sva); - mfence(); + sfence(); } else if ((cpu_feature & CPUID_CLFSH) != 0 && eva - sva < PMAP_CLFLUSH_THRESHOLD) { #ifdef DEV_APIC @@ -5348,12 +5348,14 @@ pmap_flush_page(vm_page_t m) eva = sva + PAGE_SIZE; /* - * Use mfence despite the ordering implied by + * Use mfence or sfence despite the ordering implied by * mtx_{un,}lock() because clflush on non-Intel CPUs * and clflushopt are not guaranteed to be ordered by * any other instruction. */ - if (useclflushopt || cpu_vendor_id != CPU_VENDOR_INTEL) + if (useclflushopt) + sfence(); + else if (cpu_vendor_id != CPU_VENDOR_INTEL) mfence(); for (; sva < eva; sva += cpu_clflush_line_size) { if (useclflushopt) @@ -5361,7 +5363,9 @@ pmap_flush_page(vm_page_t m) else clflush(sva); } - if (useclflushopt || cpu_vendor_id != CPU_VENDOR_INTEL) + if (useclflushopt) + sfence(); + else if (cpu_vendor_id != CPU_VENDOR_INTEL) mfence(); *cmap_pte2 = 0; sched_unpin(); diff --git a/sys/i386/include/cpufunc.h b/sys/i386/include/cpufunc.h index f433194..23be5a3 100644 --- a/sys/i386/include/cpufunc.h +++ b/sys/i386/include/cpufunc.h @@ -158,6 +158,13 @@ mfence(void) __asm __volatile("mfence" : : : "memory"); } +static __inline void +sfence(void) +{ + + __asm __volatile("sfence" : : : "memory"); +} + #ifdef _KERNEL #define HAVE_INLINE_FFS |
