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author | kib <kib@FreeBSD.org> | 2015-08-03 12:14:42 +0000 |
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committer | kib <kib@FreeBSD.org> | 2015-08-03 12:14:42 +0000 |
commit | b31c115daa6de83fc575d484bbd4f7114d62b234 (patch) | |
tree | 8808f62dbb04c4b1e243fcfa9bba1dc90c84a48e /sys/i386 | |
parent | 67927a7a7c96545feb52784dea33376dcf127e76 (diff) | |
download | FreeBSD-src-b31c115daa6de83fc575d484bbd4f7114d62b234.zip FreeBSD-src-b31c115daa6de83fc575d484bbd4f7114d62b234.tar.gz |
Clear the IA32_MISC_ENABLE MSR bit, which limits the max CPUID
reported, on APs. We already did this on BSP.
Otherwise, the userspace software which depends on the features
reported by the high CPUID levels is misbehaving. In particular, AVX
detection is non-functional, depending on which CPU thread happens to
execute when doing CPUID. Another victim is the libthr signal
handlers interposer, which needs to save full FPU extended state.
Reported and tested by: Andre Meiser <ortadur@web.de>
Sponsored by: The FreeBSD Foundation
MFC after: 2 weeks
Diffstat (limited to 'sys/i386')
-rw-r--r-- | sys/i386/i386/mp_machdep.c | 2 | ||||
-rw-r--r-- | sys/i386/include/md_var.h | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/sys/i386/i386/mp_machdep.c b/sys/i386/i386/mp_machdep.c index 083aa4a..0942523 100644 --- a/sys/i386/i386/mp_machdep.c +++ b/sys/i386/i386/mp_machdep.c @@ -247,6 +247,8 @@ init_secondary(void) pc->pc_prvspace = pc; pc->pc_curthread = 0; + intel_fix_cpuid(); + gdt_segs[GPRIV_SEL].ssd_base = (int) pc; gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss; diff --git a/sys/i386/include/md_var.h b/sys/i386/include/md_var.h index e610240..13655ee 100644 --- a/sys/i386/include/md_var.h +++ b/sys/i386/include/md_var.h @@ -118,6 +118,7 @@ void fillw(int /*u_short*/ pat, void *base, size_t cnt); void fill_based_sd(struct segment_descriptor *sdp, uint32_t base); void initializecpu(void); void initializecpucache(void); +bool intel_fix_cpuid(void); void i686_pagezero(void *addr); void sse2_pagezero(void *addr); void init_AMD_Elan_sc520(void); |