Move the files from i386/isa/ic/ to dev/ic/.

4 files changed, 0 insertions, 366 deletions

diff --git a/sys/i386/isa/ic/esp.h b/sys/i386/isa/ic/esp.h
deleted file mode 100644
index 06b665b..0000000
--- a/sys/i386/isa/ic/esp.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*-
- * Copyright (c) 1995 Sean Eric Fagan.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the author nor the names of contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#ifndef _IC_ESP_H_
-#define	_IC_ESP_H_
-
-/*
- * Definitions for Hayes ESP serial cards.
- */
-
-/*
- * CMD1 and CMD2 are the command ports, offsets from <esp_iobase>.
- */
-#define	ESP_CMD1	4
-#define	ESP_CMD2	5
-
-/*
- * STAT1 and STAT2 are to get return values and status bytes;
- * they overload CMD1 and CMD2.
- */
-#define	ESP_STATUS1	ESP_CMD1
-#define	ESP_STATUS2	ESP_CMD2
-
-/*
- * Commands.  Commands are given by writing the command value to
- * ESP_CMD1 and then writing or reading some number of bytes from
- * ESP_CMD2 or ESP_STATUS2.
- */
-#define	ESP_GETTEST	0x01	/* self-test command (1 byte + extras) */
-#define	ESP_GETDIPS	0x02	/* get on-board DIP switches (1 byte) */
-#define	ESP_SETFLOWTYPE	0x08	/* set type of flow-control (2 bytes) */
-#define	ESP_SETRXFLOW	0x0a	/* set Rx FIFO flow control levels (4 bytes) */
-#define	ESP_SETMODE	0x10	/* set board mode (1 byte) */
-#ifdef PC98
-#define ESP_SETCLOCK	0x23	/* set UART clock prescaler */
-#endif
-
-/* Mode bits (ESP_SETMODE). */
-#define	ESP_MODE_FIFO	0x02	/* act like a 16550 (compatibility mode) */
-#define	ESP_MODE_RTS	0x04	/* use RTS hardware flow control */
-#define	ESP_MODE_SCALE	0x80	/* scale FIFO trigger levels */
-
-/* Flow control type bits (ESP_SETFLOWTYPE). */
-#define	ESP_FLOW_RTS	0x04	/* cmd1: local Rx sends RTS flow control */
-#define	ESP_FLOW_CTS	0x10	/* cmd2: local transmitter responds to CTS */
-
-/* Used by ESP_SETRXFLOW. */
-#define	HIBYTE(w)	(((w) >> 8) & 0xff)
-#define	LOBYTE(w)	((w) & 0xff)
-
-#endif /* !_IC_ESP_H_ */
diff --git a/sys/i386/isa/ic/i8251.h b/sys/i386/isa/ic/i8251.h
deleted file mode 100644
index 6e07c11..0000000
--- a/sys/i386/isa/ic/i8251.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*-
- * Copyright (c) 1991 The Regents of the University of California.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by the University of
- *	California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- *	@(#)ns16550.h	7.1 (Berkeley) 5/9/91
- * $FreeBSD$
- */
-
-/*
- * modified for PC9801 by M.Ishii 
- *			Kyoto University Microcomputer Club (KMC)
- */
-
-/*
- * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org>
- */
-
-/* define command and status code */
-#define	CMD8251_TxEN	0x01	/* transmit enable */
-#define	CMD8251_DTR	0x02	/* assert DTR */
-#define	CMD8251_RxEN	0x04	/* receive enable */
-#define	CMD8251_SBRK	0x08	/* send break */
-#define	CMD8251_ER	0x10	/* error reset */
-#define	CMD8251_RTS	0x20	/* assert RTS */
-#define	CMD8251_RESET	0x40	/* internal reset */
-#define	CMD8251_EH	0x80	/* enter hunt mode (only synchronous mode)*/
-
-#define	STS8251_TxRDY	0x01	/* transmit READY */
-#define	STS8251_RxRDY	0x02	/* data exists in receive buffer */
-#define	STS8251_TxEMP	0x04	/* transmit buffer EMPTY */
-#define	STS8251_PE	0x08	/* perity error */
-#define	STS8251_OE	0x10	/* overrun error */
-#define	STS8251_FE	0x20	/* framing error */
-#define	STS8251_BD_SD	0x40	/* break detect (async) / sync detect (sync) */
-#define	STS8251_DSR	0x80	/* DSR is asserted */
-
-#define	STS8251F_TxEMP	0x01	/* transmit buffer EMPTY */
-#define	STS8251F_TxRDY	0x02	/* transmit READY */
-#define	STS8251F_RxRDY	0x04	/* data exists in receive buffer */
-#define	STS8251F_OE	0x10	/* overrun error */
-#define	STS8251F_PE	0x20	/* perity error */
-#define	STS8251F_BD_SD	0x80	/* break detect (async) / sync detect (sync) */
-
-#define	INTR8251F_DTCT	0x60	/* FIFO detection mask */
-#define	INTR8251F_INTRV	0x0e	/* interrupt event */
-#define	INTR8251F_TO	0x0c	/* receive timeout */
-#define	INTR8251F_LSTS	0x06	/* line status */
-#define	INTR8251F_RxRDY	0x04	/* receive READY */
-#define	INTR8251F_TxRDY	0x02	/* transmit READY */
-#define	INTR8251F_ISEV	0x01	/* event occured */
-#define	INTR8251F_MSTS	0x00	/* modem status */
-
-#define	CTRL8251F_ENABLE	0x01	/* enable FIFO */
-#define	CTRL8251F_RCV_RST	0x02	/* reset receive FIFO */
-#define	CTRL8251F_XMT_RST	0x04	/* reset transmit FIFO */
-
-#define	MOD8251_5BITS	0x00
-#define	MOD8251_6BITS	0x04
-#define	MOD8251_7BITS	0x08
-#define	MOD8251_8BITS	0x0c
-#define MOD8251_PDISAB	0x00	/* parity disable */
-#define	MOD8251_PODD	0x10	/* parity odd */
-#define	MOD8251_PEVEN	0x30	/* parity even */
-#define	MOD8251_STOP1	0x40	/* stop bit len = 1bit */
-#define	MOD8251_STOP2	0xc0	/* stop bit len = 2bit */
-#define	MOD8251_CLKX16	0x02	/* x16 */
-#define	MOD8251_CLKX1	0x01	/* x1 */
-
-#define	CICSCD_CD	0x20	/* CD */
-#define	CICSCD_CS	0x40	/* CS */
-#define	CICSCD_CI	0x80	/* CI */
-
-#define	CICSCDF_CS	0x10	/* CS */
-#define	CICSCDF_DR	0x20	/* DR */
-#define	CICSCDF_CI	0x40	/* CI */
-#define	CICSCDF_CD	0x80	/* CD */
-
-/* interrupt mask control */
-#define	IEN_Rx		0x01
-#define	IEN_TxEMP	0x02
-#define	IEN_Tx		0x04
diff --git a/sys/i386/isa/ic/ns16550.h b/sys/i386/isa/ic/ns16550.h
deleted file mode 100644
index 2d93e76..0000000
--- a/sys/i386/isa/ic/ns16550.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*-
- * Copyright (c) 1991 The Regents of the University of California.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by the University of
- *	California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- *	from: @(#)ns16550.h	7.1 (Berkeley) 5/9/91
- * $FreeBSD$
- */
-
-/*
- * NS16550 UART registers
- */
-#define	com_data	0	/* data register (R/W) */
-#define	com_dlbl	0	/* divisor latch low (W) */
-#define	com_dlbh	1	/* divisor latch high (W) */
-#define	com_ier		1	/* interrupt enable (W) */
-#define	com_iir		2	/* interrupt identification (R) */
-#define	com_fifo	2	/* FIFO control (W) */
-#define	com_lctl	3	/* line control register (R/W) */
-#define	com_cfcr	3	/* line control register (R/W) */
-#define	com_mcr		4	/* modem control register (R/W) */
-#define	com_lsr		5	/* line status register (R/W) */
-#define	com_msr		6	/* modem status register (R/W) */
diff --git a/sys/i386/isa/ic/rsa.h b/sys/i386/isa/ic/rsa.h
deleted file mode 100644
index 6f9376a..0000000
--- a/sys/i386/isa/ic/rsa.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*-
- * Copyright (c) 1999 FreeBSD Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-/*
- * RSA Mode Driver Data Sheet
- *
- * <<Register Map>>
- * Base + 0x00
- * Mode Select Register(Read/Write)
- * bit4=interrupt type(1: level, 0: edge)
- * bit3=Auto RTS-CTS Flow Control Enable
- * bit2=External FIFO Enable
- * bit1=Reserved(Default 0)Don't Change!!
- * bit0=Swap Upper 8byte and Lower 8byte in 16byte space.
- *
- * Base + 0x01
- * Interrupt Enable Register(Read/Write)
- * bit4=Hardware Timer Interrupt Enable
- * bit3=Character Time-Out Interrupt Enable
- * bit2=Tx FIFO Empty Interrupt Enable
- * bit1=Tx FIFO Half Full Interrupt Enable
- * bit0=Rx FIFO Half Full Interrupt Enable
- *
- * Base + 0x02
- * Status Read Register(Read)
- * bit7=Hardware  Time Out Interrupt Status(1: True, 0: False)
- * bit6=Character Time Out Interrupt Status
- * bit5=Rx FIFO Full Flag(0: True, 1: False)
- * bit4=Rx FIFO Half Full Flag
- * bit3=Rx FIFO Empty Flag
- * bit2=Tx FIFO Full Flag
- * bit1=Tx FIFO Half Full Flag
- * bit0=Tx FIFO Empty Flag
- *
- * Base + 0x02
- * FIFO Reset Register(Write)
- * Reset Extrnal FIFO
- *
- * Base + 0x03
- * Timer Interval Value Set Register(Read/Write)
- * Range of n: 1-255
- * Interval Value: n * 0.2ms
- *
- * Base + 0x04
- * Timer Control Register(Read/Write)
- * bit0=Timer Enable
- *
- * Base + 0x08 - 0x0f
- * Same as UART 16550
- *
- * Special Regisgter in RSA Mode
- * UART Data Register(Base + 0x08)
- * Data transfer between Extrnal FIFO
- *
- * UART MCR(Base + 0x0c)
- * bit3(OUT2[MCR_IENABLE])=1: Diable 16550   to Rx FIFO transfer
- * bit2(OUT1[MCR_DRS])=1:     Diable Tx FIFO to 16550   transfer
- *
- * <<Intrrupt and Intrrupt Reset>>
- * o Reciver Line Status(from UART16550)
- *   Reset: Read LSR
- *
- * o Modem Status(from UART16550)
- *   Reset: Read MSR
- *
- * o Rx FIFO Half Full(from Extrnal FIFO)
- *   Reset: Read Rx FIFO under Hall Full 
- *
- * o Character Time Out(from Extrnal FIFO)
- *   Reset: Read Rx FIFO or SRR
- *
- * o Tx FIFO Empty(from Extrnal FIFO)
- *   Reset: Write Tx FIFO or Read SRR
- *
- * o Tx FIFO Half Full(from Extrnal FIFO)
- *   Reset: Write Tx FIFO until Hall Full or Read SRR
- * 
- * o Hardware Timer(from Extrnal FIFO)
- *   Reset: Disable Timer in TCR
- *   Notes: If you want to use Timer for next intrrupt,
- *          you must enable Timer in TCR
- *
- * <<Used Setting>>
- * Auto RTS-CTS:    Enable or Disable
- * External FIFO:   Enable
- * Swap 8bytes:     Disable
- * Haredware Timer: Disable
- * interrupt type:  edge
- * interrupt source:
- *           Hareware Timer
- *           Character Time Out
- *           Tx FIFO Empty
- *           Rx FIFO Half Full
- *
- */
-
-/* I/O-DATA RSA Serise Exrension Register */
-#define rsa_msr		0	/* Mode Status Register (R/W) */
-#define	rsa_ier		1	/* Interrupt Enable Register (R/W) */
-#define	rsa_srr		2	/* Status Read Register (R) */
-#define	rsa_frr		2	/* FIFO Reset Register (W) */
-#define	rsa_tivsr	3	/* Timer Interval Value Set Register (R/W) */
-#define	rsa_tcr		4	/* Timer Control Register (W) */