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| author | jhb <jhb@FreeBSD.org> | 2015-04-02 01:02:42 +0000 |
|---|---|---|
| committer | jhb <jhb@FreeBSD.org> | 2015-04-02 01:02:42 +0000 |
| commit | b09b758bf25e41249b9253a3a796713405f28b4d (patch) | |
| tree | 7694f537b30d0bb29bc4821549a8b28e4d2fb4b4 /sys/i386 | |
| parent | 5fdf8ec7775f40bbf293206a9670387f9b26b1e2 (diff) | |
| download | FreeBSD-src-b09b758bf25e41249b9253a3a796713405f28b4d.zip FreeBSD-src-b09b758bf25e41249b9253a3a796713405f28b4d.tar.gz | |
MFC 276724:
On some Intel CPUs with a P-state but not C-state invariant TSC the TSC
may also halt in C2 and not just C3 (it seems that in some cases the BIOS
advertises its C3 state as a C2 state in _CST). Just play it safe and
disable both C2 and C3 states if a user forces the use of the TSC as the
timecounter on such CPUs.
PR: 192316
Diffstat (limited to 'sys/i386')
| -rw-r--r-- | sys/i386/i386/machdep.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sys/i386/i386/machdep.c b/sys/i386/i386/machdep.c index bbedfe0..e2e2932 100644 --- a/sys/i386/i386/machdep.c +++ b/sys/i386/i386/machdep.c @@ -1478,7 +1478,7 @@ cpu_idle(int busy) #ifndef XEN /* Apply AMD APIC timer C1E workaround. */ - if (cpu_ident_amdc1e && cpu_disable_deep_sleep) { + if (cpu_ident_amdc1e && cpu_disable_c3_sleep) { msr = rdmsr(MSR_AMDK8_IPM); if (msr & AMDK8_CMPHALT) wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); |
