Major overhaul of the aic7xxx driver:

	- catch the interrupt type (EDGE/LEVEL) before chip reset instead
	  of guessing the right type.

	- Add pause variable to the ahc struct to better handle the different
	  interrupt types and pausing the sequencer.

	- CLRINTSTAT -> CLRSCSIINT: This is a documented bit in the CLRINT
	  register in newer Adaptec documentation, so use their name for it.

	- Report valid residual byte counts.

	- Don't mess with the target scratch areas > id 8 on single, narrow,
	  channel devices.  The BIOS does a checksum of this area and can
	  flip out if we zero it out.

	- Initialize the sequencer FLAGS scratch ram variable in the single
	  channel devices to 0.  This was the cause of the annoying warning
	  where we would get a cmdcmplt the first time we did any type of
	  transfer negotiation with no valid scb.  It also fixes the problem
	  that looked like the INTSTAT register wasn't clearing fast enough.
	  This only showed up on 294x cards, not motherboard aic7870s.

	- Add the AHC_AIC7870 type and use it as the superset of aic7870
	  based controllers.

	- clear the sync offset section of the targ scratch area so that
	  we default to asyncronous transfers.  This was only a problem
	  for wide controllers because there was a scenario where the
	  offset wouldn't get updated before a data(out/in) phase would
	  occur.  This required some change in the sequencer code since we
	  were depending on this field to hold the rate to negotiate.

	- allow sync and wide negotiated commands to be tagged (the sequencer
	  now handles this properly).

1 files changed, 6 insertions, 3 deletions

diff --git a/sys/i386/scsi/aic7xxx.h b/sys/i386/scsi/aic7xxx.h
index 7a9b00f..5183735 100644
--- a/sys/i386/scsi/aic7xxx.h
+++ b/sys/i386/scsi/aic7xxx.h
@@ -20,7 +20,7 @@
  * 4. Modifications may be freely made to this file if the above conditions
  *    are met.
  *
- *	$Id: aic7xxx.h,v 1.3 1995/02/03 17:15:12 gibbs Exp $
+ *	$Id: aic7xxx.h,v 1.4 1995/02/22 01:43:25 gibbs Exp $
  */
 
 #ifndef _AIC7XXX_H_
@@ -46,11 +46,13 @@ struct ahc_dma_seg {
 };
  
 typedef u_char ahc_type;
+#define	AHC_NONE	0x00
 #define	AHC_WIDE	0x02	/* Wide Channel */
 #define AHC_TWIN	0x08	/* Twin Channel */
 #define	AHC_274		0x10	/* EISA Based Controller */
 #define	AHC_284		0x20	/* VL/ISA Based Controller */
-#define	AHC_294		0x40	/* PCI Based Controller */
+#define	AHC_AIC7870	0x40	/* PCI Based Controller */
+#define	AHC_294		0xc0	/* PCI Based Controller */
 
 /*
  * The driver keeps up to MAX_SCB scb structures per card in memory.  Only the
@@ -135,7 +137,8 @@ struct ahc_data {
 	u_short	tagenable;		/* Targets that can handle tagqueing */
 	int	numscbs;
 	u_char	maxscbs;
-	int	unpause;
+	u_char	unpause;
+	u_char	pause;
 };
 
 extern struct ahc_data *ahcdata[NAHC];