- Add support for memory mapped PCI config space access on Intel 915GM

  and 5000P/V/Z chipsets.
- If the base address of the config space BAR is above 4GB for some reason
  and this isn't a PAE kernel, then warn about this (under bootverbose)
  and don't use the BAR.

PR:		kern/126525
Submitted by:	Arthur Hartwig @ Nokia
MFC after:	2 weeks

1 files changed, 23 insertions, 3 deletions

diff --git a/sys/i386/pci/pci_cfgreg.c b/sys/i386/pci/pci_cfgreg.c
index 2fcc8d3..6350990 100644
--- a/sys/i386/pci/pci_cfgreg.c
+++ b/sys/i386/pci/pci_cfgreg.c
@@ -75,7 +75,7 @@ enum {
 };
 
 static TAILQ_HEAD(pcie_cfg_list, pcie_cfg_elem) pcie_list[MAXCPU];
-static uint32_t pciebar;
+static uint64_t pciebar;
 static int cfgmech;
 static int devmax;
 static struct mtx pcicfg_mtx;
@@ -180,10 +180,18 @@ pci_cfgregopen(void)
 			break;
 		case 0x2580:
 		case 0x2584:
-			/* Intel 915 or 925 */
+		case 0x2590:
+			/* Intel 915, 925, or 915GM */
 			pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
 			pciereg_cfgopen();
 			break;
+		case 0x25d0:
+		case 0x25d4:
+		case 0x25d8:
+			/* Intel 5000Z/V/P */
+			pciebar = pci_cfgregread(0, 16, 0, 0x64, 4) << 16;
+			pciereg_cfgopen();
+			break;			
 		}
 	}
 
@@ -507,8 +515,20 @@ pciereg_cfgopen(void)
 	vm_offset_t va;
 	int i;
 
+#ifndef PAE
+	if (pciebar >= 0x100000000) {
+		if (bootverbose)
+			printf(
+	    "PCI: Memory Mapped PCI configuration area base 0x%jx too high\n",
+			    (uintmax_t)pciebar);
+		pciebar = 0;
+		return (0);
+	}
+#endif
+		
 	if (bootverbose)
-		printf("Setting up PCIe mappings for BAR 0x%x\n", pciebar);
+		printf("Setting up PCIe mappings for BAR 0x%jx\n",
+		    (uintmax_t)pciebar);
 
 #ifdef SMP
 	SLIST_FOREACH(pc, &cpuhead, pc_allcpu)