Add the new atpic(4) driver for the 8259A master and slave PICs. By

default we provide 16 interrupt sources for IRQs 0 through 15.  However,
if the I/O APIC driver has already registered sources for any of those IRQs
then we will silently fail to register our own source for that IRQ.

Note that i386/isa/icu.h is now specific to the 8259A and no longer
contains any info relevant to APICs.  Also note that fast interrupts no
longer use a separate entry point.  Instead, both fast and threaded
interrupts share the same entry point which merely looks up the appropriate
source and passes control to intr_execute_handlers().

3 files changed, 498 insertions, 225 deletions

diff --git a/sys/i386/isa/atpic.c b/sys/i386/isa/atpic.c
new file mode 100644
index 0000000..0eef536
--- /dev/null
+++ b/sys/i386/isa/atpic.c
@@ -0,0 +1,415 @@
+/*-
+ * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * PIC driver for the 8259A Master and Slave PICs in PC/AT machines.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include "opt_auto_eoi.h"
+#include "opt_isa.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+
+#include <machine/cpufunc.h>
+#include <machine/frame.h>
+#include <machine/intr_machdep.h>
+#include <machine/md_var.h>
+#include <machine/resource.h>
+#include <machine/segments.h>
+
+#include <i386/isa/icu.h>
+#include <i386/isa/isa.h>
+#include <isa/isavar.h>
+
+#define	MASTER	0
+#define	SLAVE	1
+
+/* XXX: Magic numbers */
+#ifdef PC98
+#ifdef AUTO_EOI_1
+#define	MASTER_MODE	0x1f	/* Master auto EOI, 8086 mode */
+#else
+#define	MASTER_MODE	0x1d	/* Master 8086 mode */
+#endif
+#define	SLAVE_MODE	9	/* 8086 mode */
+#else /* IBM-PC */
+#ifdef AUTO_EOI_1
+#define	MASTER_MODE	(2 | 1)	/* Auto EOI, 8086 mode */
+#else
+#define	MASTER_MODE	1	/* 8086 mode */
+#endif
+#ifdef AUTO_EOI_2
+#define	SLAVE_MODE	(2 | 1)	/* Auto EOI, 8086 mode */
+#else
+#define	SLAVE_MODE	1	/* 8086 mode */
+#endif
+#endif /* PC98 */
+
+static void	atpic_init(void *dummy);
+
+unsigned int imen;	/* XXX */
+
+inthand_t
+	IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2),
+	IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5),
+	IDTVEC(atpic_intr6), IDTVEC(atpic_intr7), IDTVEC(atpic_intr8),
+	IDTVEC(atpic_intr9), IDTVEC(atpic_intr10), IDTVEC(atpic_intr11),
+	IDTVEC(atpic_intr12), IDTVEC(atpic_intr13), IDTVEC(atpic_intr14),
+	IDTVEC(atpic_intr15);
+
+#define	IRQ(ap, ai)	((ap)->at_irqbase + (ai)->at_irq)
+
+#define	ATPIC(io, base, eoi, imenptr)				\
+     	{ { atpic_enable_source, atpic_disable_source, (eoi),		\
+	    atpic_enable_intr, atpic_vector, atpic_source_pending, NULL, \
+	    atpic_resume }, (io), (base), IDT_IO_INTS + (base), (imenptr) }
+
+#define	INTSRC(irq)							\
+	{ { &atpics[(irq) / 8].at_pic }, (irq) % 8,			\
+	    IDTVEC(atpic_intr ## irq ) }
+
+struct atpic {
+	struct pic at_pic;
+	int	at_ioaddr;
+	int	at_irqbase;
+	uint8_t	at_intbase;
+	uint8_t	*at_imen;
+};
+
+struct atpic_intsrc {
+	struct intsrc at_intsrc;
+	int	at_irq;		/* Relative to PIC base. */
+	inthand_t *at_intr;
+};
+
+static void atpic_enable_source(struct intsrc *isrc);
+static void atpic_disable_source(struct intsrc *isrc);
+static void atpic_eoi_master(struct intsrc *isrc);
+static void atpic_eoi_slave(struct intsrc *isrc);
+static void atpic_enable_intr(struct intsrc *isrc);
+static int atpic_vector(struct intsrc *isrc);
+static void atpic_resume(struct intsrc *isrc);
+static int atpic_source_pending(struct intsrc *isrc);
+static void i8259_init(struct atpic *pic, int slave);
+
+static struct atpic atpics[] = {
+	ATPIC(IO_ICU1, 0, atpic_eoi_master, (uint8_t *)&imen),
+	ATPIC(IO_ICU2, 8, atpic_eoi_slave, ((uint8_t *)&imen) + 1)
+};
+
+static struct atpic_intsrc atintrs[] = {
+	INTSRC(0),
+	INTSRC(1),
+	INTSRC(2),
+	INTSRC(3),
+	INTSRC(4),
+	INTSRC(5),
+	INTSRC(6),
+	INTSRC(7),
+	INTSRC(8),
+	INTSRC(9),
+	INTSRC(10),
+	INTSRC(11),
+	INTSRC(12),
+	INTSRC(13),
+	INTSRC(14),
+	INTSRC(15),
+};
+
+static void
+atpic_enable_source(struct intsrc *isrc)
+{
+	struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
+	struct atpic *ap = (struct atpic *)isrc->is_pic;
+
+	mtx_lock_spin(&icu_lock);
+	*ap->at_imen &= ~(1 << ai->at_irq);
+	outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
+	mtx_unlock_spin(&icu_lock);
+}
+
+static void
+atpic_disable_source(struct intsrc *isrc)
+{
+	struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
+	struct atpic *ap = (struct atpic *)isrc->is_pic;
+
+	mtx_lock_spin(&icu_lock);
+	*ap->at_imen |= (1 << ai->at_irq);
+	outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
+	mtx_unlock_spin(&icu_lock);
+}
+
+static void
+atpic_eoi_master(struct intsrc *isrc)
+{
+
+	KASSERT(isrc->is_pic == &atpics[MASTER].at_pic,
+	    ("%s: mismatched pic", __func__));
+#ifndef AUTO_EOI_1
+	mtx_lock_spin(&icu_lock);
+	outb(atpics[MASTER].at_ioaddr, ICU_EOI);
+	mtx_unlock_spin(&icu_lock);
+#endif
+}
+
+static void
+atpic_eoi_slave(struct intsrc *isrc)
+{
+
+	KASSERT(isrc->is_pic == &atpics[SLAVE].at_pic,
+	    ("%s: mismatched pic", __func__));
+#ifndef AUTO_EOI_2
+	mtx_lock_spin(&icu_lock);
+	outb(atpics[SLAVE].at_ioaddr, ICU_EOI);
+#ifndef AUTO_EOI_1
+	outb(atpics[MASTER].at_ioaddr, ICU_EOI);
+#endif
+	mtx_unlock_spin(&icu_lock);
+#endif
+}
+
+static void
+atpic_enable_intr(struct intsrc *isrc)
+{
+	struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
+	struct atpic *ap = (struct atpic *)isrc->is_pic;
+	register_t eflags;
+
+	mtx_lock_spin(&icu_lock);
+	eflags = intr_disable();
+	setidt(ap->at_intbase + ai->at_irq, ai->at_intr, SDT_SYS386IGT,
+	    SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
+	intr_restore(eflags);
+	mtx_unlock_spin(&icu_lock);
+}
+
+static int
+atpic_vector(struct intsrc *isrc)
+{
+	struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
+	struct atpic *ap = (struct atpic *)isrc->is_pic;
+
+	return (IRQ(ap, ai));
+}
+
+static int
+atpic_source_pending(struct intsrc *isrc)
+{
+	struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
+	struct atpic *ap = (struct atpic *)isrc->is_pic;
+
+	return (inb(ap->at_ioaddr) & (1 << ai->at_irq));
+}
+
+static void
+atpic_resume(struct intsrc *isrc)
+{
+	struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
+	struct atpic *ap = (struct atpic *)isrc->is_pic;
+
+	if (ai->at_irq == 0)
+		i8259_init(ap, ap == &atpics[SLAVE]);
+}
+
+static void
+i8259_init(struct atpic *pic, int slave)
+{
+	int imr_addr;
+
+	/* Reset the PIC and program with next four bytes. */
+	mtx_lock_spin(&icu_lock);
+#ifdef DEV_MCA
+	if (MCA_system)
+		outb(pic->at_ioaddr, 0x19);
+	else
+#endif
+		outb(pic->at_ioaddr, 0x11);
+	imr_addr = pic->at_ioaddr + ICU_IMR_OFFSET;
+
+	/* Start vector. */
+	outb(imr_addr, pic->at_intbase);
+
+	/*
+	 * Setup slave links.  For the master pic, indicate what line
+	 * the slave is configured on.  For the slave indicate
+	 * which line on the master we are connected to.
+	 */
+	if (slave)
+		outb(imr_addr, ICU_SLAVEID);	/* my slave id is 7 */
+	else
+		outb(imr_addr, IRQ_SLAVE);	/* slave on line 7 */
+
+	/* Set mode. */
+	if (slave)
+		outb(imr_addr, SLAVE_MODE);
+	else
+		outb(imr_addr, MASTER_MODE);
+
+	/* Set interrupt enable mask. */
+	outb(imr_addr, *pic->at_imen);
+
+	/* Reset is finished, default to IRR on read. */
+	outb(pic->at_ioaddr, 0x0a);
+
+#ifndef PC98
+	/* Set priority order to 3-7, 0-2 (com2 first). */
+	if (!slave)
+		outb(pic->at_ioaddr, 0xc0 | (3 - 1));
+#endif
+	mtx_unlock_spin(&icu_lock);
+}
+
+void
+atpic_startup(void)
+{
+
+	/* Start off with all interrupts disabled. */
+	imen = 0xffff;
+	i8259_init(&atpics[MASTER], 0);
+	i8259_init(&atpics[SLAVE], 1);
+	atpic_enable_source((struct intsrc *)&atintrs[ICU_SLAVEID]);
+}
+
+static void
+atpic_init(void *dummy __unused)
+{
+	struct atpic_intsrc *ai;
+	int i;
+
+	/* Loop through all interrupt sources and add them. */
+	for (i = 0; i < sizeof(atintrs) / sizeof(struct atpic_intsrc); i++) {
+		if (i == ICU_SLAVEID)
+			continue;
+		ai = &atintrs[i];
+		intr_register_source(&ai->at_intsrc);
+	}
+}
+SYSINIT(atpic_init, SI_SUB_INTR, SI_ORDER_SECOND + 1, atpic_init, NULL)
+
+void
+atpic_sched_ithd(struct intrframe iframe)
+{
+	struct intsrc *isrc;
+
+	KASSERT((uint)iframe.if_vec < ICU_LEN,
+	    ("unknown int %d\n", iframe.if_vec));
+	isrc = &atintrs[iframe.if_vec].at_intsrc;
+	intr_execute_handlers(isrc, &iframe);
+}
+
+#ifdef DEV_ISA
+/*
+ * Bus attachment for the ISA PIC.
+ */
+static struct isa_pnp_id atpic_ids[] = {
+	{ 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
+	{ 0 }
+};
+
+static int
+atpic_probe(device_t dev)
+{
+	int result;
+	
+	result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
+	if (result <= 0)
+		device_quiet(dev);
+	return (result);
+}
+
+/*
+ * We might be granted IRQ 2, as this is typically consumed by chaining
+ * between the two PIC components.  If we're using the APIC, however,
+ * this may not be the case, and as such we should free the resource.
+ * (XXX untested)
+ *
+ * The generic ISA attachment code will handle allocating any other resources
+ * that we don't explicitly claim here.
+ */
+static int
+atpic_attach(device_t dev)
+{
+	struct resource *res;
+	int rid;
+
+	/* Try to allocate our IRQ and then free it. */
+	rid = 0;
+	res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 0);
+	if (res != NULL)
+		bus_release_resource(dev, SYS_RES_IRQ, rid, res);
+	return (0);
+}
+
+static device_method_t atpic_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		atpic_probe),
+	DEVMETHOD(device_attach,	atpic_attach),
+	DEVMETHOD(device_detach,	bus_generic_detach),
+	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
+	DEVMETHOD(device_suspend,	bus_generic_suspend),
+	DEVMETHOD(device_resume,	bus_generic_resume),
+	{ 0, 0 }
+};
+
+static driver_t atpic_driver = {
+	"atpic",
+	atpic_methods,
+	1,		/* no softc */
+};
+
+static devclass_t atpic_devclass;
+
+DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
+DRIVER_MODULE(atpic, acpi, atpic_driver, atpic_devclass, 0, 0);
+
+/*
+ * Return a bitmap of the current interrupt requests.  This is 8259-specific
+ * and is only suitable for use at probe time.
+ */
+intrmask_t
+isa_irq_pending(void)
+{
+	u_char irr1;
+	u_char irr2;
+
+	irr1 = inb(IO_ICU1);
+	irr2 = inb(IO_ICU2);
+	return ((irr2 << 8) | irr1);
+}
+#endif /* DEV_ISA */
diff --git a/sys/i386/isa/atpic_vector.s b/sys/i386/isa/atpic_vector.s
index 1023635..2da86e0 100644
--- a/sys/i386/isa/atpic_vector.s
+++ b/sys/i386/isa/atpic_vector.s
@@ -1,10 +1,58 @@
-/*
+/*-
+ * Copyright (c) 1989, 1990 William F. Jolitz.
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
  *	from: vector.s, 386BSD 0.1 unknown origin
  * $FreeBSD$
  */
 
+/*
+ * Interrupt entry points for external interrupts triggered by the 8259A
+ * master and slave interrupt controllers.
+ */
+
+#include "opt_auto_eoi.h"
+
+#include <machine/asmacros.h>
+#include <i386/isa/icu.h>
+#ifdef PC98
+#include <pc98/pc98/pc98.h>
+#else
+#include <i386/isa/isa.h>
+#endif
+
+#include "assym.s"
+
 #define	IRQ_BIT(irq_num)	(1 << ((irq_num) % 8))
-#define	IRQ_LBIT(irq_num)	(1 << (irq_num))
 #define	IRQ_BYTE(irq_num)	((irq_num) >> 3)
 
 #ifdef AUTO_EOI_1
@@ -38,119 +86,8 @@
 
 #endif
 
-#define PUSH_FRAME							\
-	pushl	$0 ;		/* dummy error code */			\
-	pushl	$0 ;		/* dummy trap type */			\
-	pushal ;		/* 8 ints */				\
-	pushl	%ds ;		/* save data and extra segments ... */	\
-	pushl	%es ;							\
-	pushl	%fs
-
-#define PUSH_DUMMY							\
-	pushfl ;		/* eflags */				\
-	pushl	%cs ;		/* cs */				\
-	pushl	12(%esp) ;	/* original caller eip */		\
-	pushl	$0 ;		/* dummy error code */			\
-	pushl	$0 ;		/* dummy trap type */			\
-	subl	$11*4,%esp
-
-#define POP_FRAME							\
-	popl	%fs ;							\
-	popl	%es ;							\
-	popl	%ds ;							\
-	popal ;								\
-	addl	$4+4,%esp
-
-#define POP_DUMMY							\
-	addl	$16*4,%esp
-
-#define MASK_IRQ(icu, irq_num)						\
-	movb	imen + IRQ_BYTE(irq_num),%al ;				\
-	orb	$IRQ_BIT(irq_num),%al ;					\
-	movb	%al,imen + IRQ_BYTE(irq_num) ;				\
-	outb	%al,$icu+ICU_IMR_OFFSET
-
-#define UNMASK_IRQ(icu, irq_num)					\
-	movb	imen + IRQ_BYTE(irq_num),%al ;				\
-	andb	$~IRQ_BIT(irq_num),%al ;				\
-	movb	%al,imen + IRQ_BYTE(irq_num) ;				\
-	outb	%al,$icu+ICU_IMR_OFFSET
 /*
  * Macros for interrupt interrupt entry, call to handler, and exit.
- */
-
-#define	FAST_INTR(irq_num, vec_name, icu, enable_icus)			\
-	.text ;								\
-	SUPERALIGN_TEXT ;						\
-IDTVEC(vec_name) ;							\
-	PUSH_FRAME ;							\
-	mov	$KDSEL,%ax ;						\
-	mov	%ax,%ds ;						\
-	mov	%ax,%es ;						\
-	mov	$KPSEL,%ax ;						\
-	mov	%ax,%fs ;						\
-	FAKE_MCOUNT((12+ACTUALLY_PUSHED)*4(%esp)) ;			\
-	movl	PCPU(CURTHREAD),%ebx ;					\
-	cmpl	$0,TD_CRITNEST(%ebx) ;					\
-	je	1f ;							\
-;									\
-	movl	$1,PCPU(INT_PENDING) ;					\
-	orl	$IRQ_LBIT(irq_num),PCPU(FPENDING) ;			\
-	MASK_IRQ(icu, irq_num) ;					\
-	enable_icus ;							\
-	jmp	10f ;							\
-1: ;									\
-	incl	TD_CRITNEST(%ebx) ;					\
-	incl	TD_INTR_NESTING_LEVEL(%ebx) ;				\
-	pushl	intr_unit + (irq_num) * 4 ;				\
-	call	*intr_handler + (irq_num) * 4 ;				\
-	addl	$4,%esp ;						\
-	enable_icus ;							\
-	incl	cnt+V_INTR ;	/* book-keeping can wait */		\
-	movl	intr_countp + (irq_num) * 4,%eax ;			\
-	incl	(%eax) ;						\
-	decl	TD_CRITNEST(%ebx) ;					\
-	cmpl	$0,PCPU(INT_PENDING) ;					\
-	je	2f ;							\
-;									\
-	call	i386_unpend ;						\
-2: ;									\
-	decl	TD_INTR_NESTING_LEVEL(%ebx) ;				\
-10: ;									\
-	MEXITCOUNT ;							\
-	jmp	doreti
-
-/*
- * Restart a fast interrupt that was held up by a critical section.
- * This routine is called from unpend().  unpend() ensures we are
- * in a critical section and deals with the interrupt nesting level
- * for us.  If we previously masked the irq, we have to unmask it.
- *
- * We have a choice.  We can regenerate the irq using the 'int'
- * instruction or we can create a dummy frame and call the interrupt
- * handler directly.  I've chosen to use the dummy-frame method.
- */
-#define	FAST_UNPEND(irq_num, vec_name, icu)				\
-	.text ;								\
-	SUPERALIGN_TEXT ;						\
-IDTVEC(vec_name) ;							\
-;									\
-	pushl %ebp ;							\
-	movl %esp, %ebp ;						\
-	PUSH_DUMMY ;							\
-	pushl	intr_unit + (irq_num) * 4 ;				\
-	call	*intr_handler + (irq_num) * 4 ;	/* do the work ASAP */	\
-	addl	$4, %esp ;						\
-	incl	cnt+V_INTR ;	/* book-keeping can wait */		\
-	movl	intr_countp + (irq_num) * 4,%eax ;			\
-	incl	(%eax) ;						\
-	UNMASK_IRQ(icu, irq_num) ;					\
-	POP_DUMMY ;							\
-	popl %ebp ;							\
-	ret
-
-/* 
- * Slow, threaded interrupts.
  *
  * XXX Most of the parameters here are obsolete.  Fix this when we're
  * done.
@@ -162,7 +99,12 @@ IDTVEC(vec_name) ;							\
 	.text ;								\
 	SUPERALIGN_TEXT ;						\
 IDTVEC(vec_name) ;							\
-	PUSH_FRAME ;							\
+	pushl	$0 ;		/* dummy error code */			\
+	pushl	$0 ;		/* dummy trap type */			\
+	pushal ;		/* 8 ints */				\
+	pushl	%ds ;		/* save data and extra segments ... */	\
+	pushl	%es ;							\
+	pushl	%fs ;							\
 	mov	$KDSEL,%ax ;	/* load kernel ds, es and fs */		\
 	mov	%ax,%ds ;						\
 	mov	%ax,%es ;						\
@@ -170,84 +112,41 @@ IDTVEC(vec_name) ;							\
 	mov	%ax,%fs ;						\
 ;									\
 	maybe_extra_ipending ;						\
-	MASK_IRQ(icu, irq_num) ;					\
+	movb	imen + IRQ_BYTE(irq_num),%al ;				\
+	orb	$IRQ_BIT(irq_num),%al ;					\
+	movb	%al,imen + IRQ_BYTE(irq_num) ;				\
+	outb	%al,$icu+ICU_IMR_OFFSET ;				\
 	enable_icus ;							\
 ;									\
 	movl	PCPU(CURTHREAD),%ebx ;					\
-        cmpl	$0,TD_CRITNEST(%ebx) ;					\
-	je      1f ;							\
-	movl	$1,PCPU(INT_PENDING);					\
-	orl     $IRQ_LBIT(irq_num),PCPU(IPENDING) ;			\
-	jmp     10f ;							\
-1: ;									\
 	incl	TD_INTR_NESTING_LEVEL(%ebx) ;				\
 ;									\
 	FAKE_MCOUNT(13*4(%esp)) ;	/* XXX late to avoid double count */ \
-	cmpl	$0,PCPU(INT_PENDING) ;					\
-	je      9f ;							\
-	call    i386_unpend ;						\
-9: ;									\
 	pushl	$irq_num; 	/* pass the IRQ */			\
-	call	sched_ithd ;						\
+	call	atpic_sched_ithd ;					\
 	addl	$4, %esp ;	/* discard the parameter */		\
 ;									\
 	decl	TD_INTR_NESTING_LEVEL(%ebx) ;				\
-10: ;									\
 	MEXITCOUNT ;							\
 	jmp	doreti
 
 MCOUNT_LABEL(bintr)
-	FAST_INTR(0,fastintr0, IO_ICU1, ENABLE_ICU1)
-	FAST_INTR(1,fastintr1, IO_ICU1, ENABLE_ICU1)
-	FAST_INTR(2,fastintr2, IO_ICU1, ENABLE_ICU1)
-	FAST_INTR(3,fastintr3, IO_ICU1, ENABLE_ICU1)
-	FAST_INTR(4,fastintr4, IO_ICU1, ENABLE_ICU1)
-	FAST_INTR(5,fastintr5, IO_ICU1, ENABLE_ICU1)
-	FAST_INTR(6,fastintr6, IO_ICU1, ENABLE_ICU1)
-	FAST_INTR(7,fastintr7, IO_ICU1, ENABLE_ICU1)
-	FAST_INTR(8,fastintr8, IO_ICU2, ENABLE_ICU1_AND_2)
-	FAST_INTR(9,fastintr9, IO_ICU2, ENABLE_ICU1_AND_2)
-	FAST_INTR(10,fastintr10, IO_ICU2, ENABLE_ICU1_AND_2)
-	FAST_INTR(11,fastintr11, IO_ICU2, ENABLE_ICU1_AND_2)
-	FAST_INTR(12,fastintr12, IO_ICU2, ENABLE_ICU1_AND_2)
-	FAST_INTR(13,fastintr13, IO_ICU2, ENABLE_ICU1_AND_2)
-	FAST_INTR(14,fastintr14, IO_ICU2, ENABLE_ICU1_AND_2)
-	FAST_INTR(15,fastintr15, IO_ICU2, ENABLE_ICU1_AND_2)
-
 #define	CLKINTR_PENDING	movl $1,CNAME(clkintr_pending)
 /* Threaded interrupts */
-	INTR(0,intr0, IO_ICU1, ENABLE_ICU1, CLKINTR_PENDING)
-	INTR(1,intr1, IO_ICU1, ENABLE_ICU1,)
-	INTR(2,intr2, IO_ICU1, ENABLE_ICU1,)
-	INTR(3,intr3, IO_ICU1, ENABLE_ICU1,)
-	INTR(4,intr4, IO_ICU1, ENABLE_ICU1,)
-	INTR(5,intr5, IO_ICU1, ENABLE_ICU1,)
-	INTR(6,intr6, IO_ICU1, ENABLE_ICU1,)
-	INTR(7,intr7, IO_ICU1, ENABLE_ICU1,)
-	INTR(8,intr8, IO_ICU2, ENABLE_ICU1_AND_2,)
-	INTR(9,intr9, IO_ICU2, ENABLE_ICU1_AND_2,)
-	INTR(10,intr10, IO_ICU2, ENABLE_ICU1_AND_2,)
-	INTR(11,intr11, IO_ICU2, ENABLE_ICU1_AND_2,)
-	INTR(12,intr12, IO_ICU2, ENABLE_ICU1_AND_2,)
-	INTR(13,intr13, IO_ICU2, ENABLE_ICU1_AND_2,)
-	INTR(14,intr14, IO_ICU2, ENABLE_ICU1_AND_2,)
-	INTR(15,intr15, IO_ICU2, ENABLE_ICU1_AND_2,)
-
-	FAST_UNPEND(0,fastunpend0, IO_ICU1)
-	FAST_UNPEND(1,fastunpend1, IO_ICU1)
-	FAST_UNPEND(2,fastunpend2, IO_ICU1)
-	FAST_UNPEND(3,fastunpend3, IO_ICU1)
-	FAST_UNPEND(4,fastunpend4, IO_ICU1)
-	FAST_UNPEND(5,fastunpend5, IO_ICU1)
-	FAST_UNPEND(6,fastunpend6, IO_ICU1)
-	FAST_UNPEND(7,fastunpend7, IO_ICU1)
-	FAST_UNPEND(8,fastunpend8, IO_ICU2)
-	FAST_UNPEND(9,fastunpend9, IO_ICU2)
-	FAST_UNPEND(10,fastunpend10, IO_ICU2)
-	FAST_UNPEND(11,fastunpend11, IO_ICU2)
-	FAST_UNPEND(12,fastunpend12, IO_ICU2)
-	FAST_UNPEND(13,fastunpend13, IO_ICU2)
-	FAST_UNPEND(14,fastunpend14, IO_ICU2)
-	FAST_UNPEND(15,fastunpend15, IO_ICU2)
+	INTR(0,atpic_intr0, IO_ICU1, ENABLE_ICU1, CLKINTR_PENDING)
+	INTR(1,atpic_intr1, IO_ICU1, ENABLE_ICU1,)
+	INTR(2,atpic_intr2, IO_ICU1, ENABLE_ICU1,)
+	INTR(3,atpic_intr3, IO_ICU1, ENABLE_ICU1,)
+	INTR(4,atpic_intr4, IO_ICU1, ENABLE_ICU1,)
+	INTR(5,atpic_intr5, IO_ICU1, ENABLE_ICU1,)
+	INTR(6,atpic_intr6, IO_ICU1, ENABLE_ICU1,)
+	INTR(7,atpic_intr7, IO_ICU1, ENABLE_ICU1,)
+	INTR(8,atpic_intr8, IO_ICU2, ENABLE_ICU1_AND_2,)
+	INTR(9,atpic_intr9, IO_ICU2, ENABLE_ICU1_AND_2,)
+	INTR(10,atpic_intr10, IO_ICU2, ENABLE_ICU1_AND_2,)
+	INTR(11,atpic_intr11, IO_ICU2, ENABLE_ICU1_AND_2,)
+	INTR(12,atpic_intr12, IO_ICU2, ENABLE_ICU1_AND_2,)
+	INTR(13,atpic_intr13, IO_ICU2, ENABLE_ICU1_AND_2,)
+	INTR(14,atpic_intr14, IO_ICU2, ENABLE_ICU1_AND_2,)
+	INTR(15,atpic_intr15, IO_ICU2, ENABLE_ICU1_AND_2,)
 MCOUNT_LABEL(eintr)
-
diff --git a/sys/i386/isa/icu.h b/sys/i386/isa/icu.h
index 82e084f..8958f4a 100644
--- a/sys/i386/isa/icu.h
+++ b/sys/i386/isa/icu.h
@@ -45,38 +45,6 @@
 #ifndef _I386_ISA_ICU_H_
 #define	_I386_ISA_ICU_H_
 
-#ifndef	LOCORE
-
-/*
- * Note:
- *	Most of the SMP equivilants of the icu macros are coded
- *	elsewhere in an MP-safe fashion.
- *	In particular note that the 'imen' variable is opaque.
- *	DO NOT access imen directly, use INTREN()/INTRDIS().
- */
-
-void	INTREN(u_int);
-void	INTRDIS(u_int);
-
-#ifdef APIC_IO
-extern	unsigned apic_imen;	/* APIC interrupt mask enable */
-#else
-extern	unsigned imen;		/* interrupt mask enable */
-#endif
-
-#endif /* LOCORE */
-
-
-#ifdef APIC_IO
-/*
- * Note: The APIC uses different values for IRQxxx.
- *	 Unfortunately many drivers use the 8259 values as indexes
- *	 into tables, etc.  The APIC equivilants are kept as APIC_IRQxxx.
- *	 The 8259 versions have to be used in SMP for legacy operation
- *	 of the drivers.
- */
-#endif /* APIC_IO */
-
 /*
  * Interrupt enable bits - in normal order of priority (which we change)
  */
@@ -122,6 +90,7 @@ extern	unsigned imen;		/* interrupt mask enable */
  * Interrupt Control offset into Interrupt descriptor table (IDT)
  */
 #define	ICU_OFFSET	32		/* 0-31 are processor exceptions */
+#define	ICU_LEN		16		/* 32-47 are ISA interrupts */
 
 #ifdef PC98
 #define	ICU_IMR_OFFSET	2
@@ -130,23 +99,13 @@ extern	unsigned imen;		/* interrupt mask enable */
 #define	ICU_IMR_OFFSET	1
 #define	ICU_SLAVEID	2
 #endif
-#define	ICU_EOI		0x20
 
-#ifdef APIC_IO
-
-/* 32-47: ISA IRQ0-IRQ15, 48-63: IO APIC IRQ16-IRQ31 */
-#define	ICU_LEN		32
-#define	HWI_MASK	0xffffffff	/* bits for h/w interrupts */
-#define	NHWI		32
-
-#else
-
-#define	ICU_LEN		16		/* 32-47 are ISA interrupts */
+#define	ICU_EOI		0x20
 #define	HWI_MASK	0xffff		/* bits for h/w interrupts */
-#define	NHWI		16
 
-#endif /* APIC_IO */
-
-#define	INTRCNT_COUNT	(1 + ICU_LEN + 2 * ICU_LEN)
+#ifndef LOCORE
+void	atpic_sched_ithd(struct intrframe iframe);
+void	atpic_startup(void);
+#endif
 
 #endif /* !_I386_ISA_ICU_H_ */