Maintain a mapping from irq number to (ioapic number, int pin) tuple,

and use this when masking/unmasking interrupts.

Maintain a mapping from (iopaic number, int pin) tuple to irq number,
and use this when configuring devices and programming the ioapics.

Previous code assumed that irq number was equal to int pin number, and
that the ioapic number was 0.

Don't let an AP enter _cpu_switch before all local apics are initialized.

5 files changed, 37 insertions, 30 deletions

diff --git a/sys/i386/isa/apic_ipl.s b/sys/i386/isa/apic_ipl.s
index 5bbdca6..8d9b9d8 100644
--- a/sys/i386/isa/apic_ipl.s
+++ b/sys/i386/isa/apic_ipl.s
@@ -22,7 +22,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: apic_ipl.s,v 1.20 1998/04/22 22:49:29 tegge Exp $
+ *	$Id: apic_ipl.s,v 1.21 1998/08/11 15:08:12 bde Exp $
  */
 
 
@@ -227,7 +227,6 @@ bad_mask:	.asciz	"bad mask"
 #endif
 
 /*
- * MULTIPLE_IOAPICSXXX: cannot assume apic #0 in the following function.
  * (soon to be) MP-safe function to clear ONE INT mask bit.
  * The passed arg is a 32bit u_int MASK.
  * It sets the associated bit in _apic_imen.
@@ -244,10 +243,9 @@ ENTRY(INTREN)
 
 	QUALIFY_MASK
 
-	leal	16(,%ecx,2), %ecx	/* calculate register index */
-
-	movl	$0, %edx		/* XXX FIXME: APIC # */
-	movl	_ioapic(,%edx,4), %edx	/* %edx holds APIC base address */
+	shll	$4, %ecx
+	movl	CNAME(int_to_apicintpin) + 8(%ecx), %edx
+	movl	CNAME(int_to_apicintpin) + 12(%ecx), %ecx
 
 	movl	%ecx, (%edx)		/* write the target register index */
 	movl	16(%edx), %eax		/* read the target register data */
@@ -259,7 +257,6 @@ ENTRY(INTREN)
 	ret
 
 /*
- * MULTIPLE_IOAPICSXXX: cannot assume apic #0 in the following function.
  * (soon to be) MP-safe function to set ONE INT mask bit.
  * The passed arg is a 32bit u_int MASK.
  * It clears the associated bit in _apic_imen.
@@ -276,10 +273,9 @@ ENTRY(INTRDIS)
 
 	QUALIFY_MASK
 
-	leal	16(,%ecx,2), %ecx	/* calculate register index */
-
-	movl	$0, %edx		/* XXX FIXME: APIC # */
-	movl	_ioapic(,%edx,4), %edx	/* %edx holds APIC base address */
+	shll	$4, %ecx
+	movl	CNAME(int_to_apicintpin) + 8(%ecx), %edx
+	movl	CNAME(int_to_apicintpin) + 12(%ecx), %ecx
 
 	movl	%ecx, (%edx)		/* write the target register index */
 	movl	16(%edx), %eax		/* read the target register data */
diff --git a/sys/i386/isa/apic_vector.s b/sys/i386/isa/apic_vector.s
index 4bd4f77..17f8942 100644
--- a/sys/i386/isa/apic_vector.s
+++ b/sys/i386/isa/apic_vector.s
@@ -1,6 +1,6 @@
 /*
  *	from: vector.s, 386BSD 0.1 unknown origin
- *	$Id: apic_vector.s,v 1.32 1998/08/11 17:01:32 bde Exp $
+ *	$Id: apic_vector.s,v 1.33 1998/09/04 23:03:04 luoqi Exp $
  */
 
 
@@ -166,13 +166,17 @@ IDTVEC(vec_name) ;							\
 	popal ;								\
 	addl	$4+4,%esp
 
+#define IOAPICADDR(irq_num) CNAME(int_to_apicintpin) + 16 * (irq_num) + 8
+#define REDIRIDX(irq_num) CNAME(int_to_apicintpin) + 16 * (irq_num) + 12
+	
 #define MASK_IRQ(irq_num)						\
 	IMASK_LOCK ;				/* into critical reg */	\
 	testl	$IRQ_BIT(irq_num), _apic_imen ;				\
 	jne	7f ;			/* masked, don't mask */	\
 	orl	$IRQ_BIT(irq_num), _apic_imen ;	/* set the mask bit */	\
-	movl	_ioapic, %ecx ;			/* ioapic[0] addr */	\
-	movl	$REDTBL_IDX(irq_num), (%ecx) ;	/* write the index */	\
+	movl	IOAPICADDR(irq_num), %ecx ;	/* ioapic addr */	\
+	movl	REDIRIDX(irq_num), %eax ;	/* get the index */	\
+	movl	%eax, (%ecx) ;			/* write the index */	\
 	movl	IOAPIC_WINDOW(%ecx), %eax ;	/* current value */	\
 	orl	$IOART_INTMASK, %eax ;		/* set the mask */	\
 	movl	%eax, IOAPIC_WINDOW(%ecx) ;	/* new value */		\
@@ -218,8 +222,9 @@ IDTVEC(vec_name) ;							\
 	testl	$IRQ_BIT(irq_num), _apic_imen ;				\
 	je	7f ;			/* bit clear, not masked */	\
 	andl	$~IRQ_BIT(irq_num), _apic_imen ;/* clear mask bit */	\
-	movl	_ioapic,%ecx ;			/* ioapic[0]addr */	\
-	movl	$REDTBL_IDX(irq_num),(%ecx) ;	/* write the index */	\
+	movl	IOAPICADDR(irq_num),%ecx ;	/* ioapic addr */	\
+	movl	REDIRIDX(irq_num), %eax ;	/* get the index */	\
+	movl	%eax,(%ecx) ;			/* write the index */	\
 	movl	IOAPIC_WINDOW(%ecx),%eax ;	/* current value */	\
 	andl	$~IOART_INTMASK,%eax ;		/* clear the mask */	\
 	movl	%eax,IOAPIC_WINDOW(%ecx) ;	/* new value */		\
@@ -990,7 +995,7 @@ CNAME(cpustop_restartfunc):
 
 	.globl	_apic_pin_trigger
 _apic_pin_trigger:
-	.space	(NAPIC * 4), 0
+	.long	0
 
 
 /*
diff --git a/sys/i386/isa/clock.c b/sys/i386/isa/clock.c
index 4e14052..3d8f8cd 100644
--- a/sys/i386/isa/clock.c
+++ b/sys/i386/isa/clock.c
@@ -34,7 +34,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)clock.c	7.2 (Berkeley) 5/12/91
- *	$Id: clock.c,v 1.123 1998/06/07 20:36:39 phk Exp $
+ *	$Id: clock.c,v 1.124 1998/06/09 13:10:46 phk Exp $
  */
 
 /*
@@ -953,7 +953,7 @@ cpu_initclocks()
 	/* Finish initializing 8253 timer 0. */
 #ifdef APIC_IO
 
-	apic_8254_intr = isa_apic_pin(0);
+	apic_8254_intr = isa_apic_irq(0);
 	apic_8254_trial = 0;
 	if (apic_8254_intr >= 0 ) {
 		if (apic_int_type(0, 0) == 3)
@@ -993,7 +993,7 @@ cpu_initclocks()
 		printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
 
 #ifdef APIC_IO
-	if (isa_apic_pin(8) != 8)
+	if (isa_apic_irq(8) != 8)
 		panic("APIC RTC != 8");
 #endif /* APIC_IO */
 
diff --git a/sys/i386/isa/intr_machdep.c b/sys/i386/isa/intr_machdep.c
index 49c7f24..3f891f2 100644
--- a/sys/i386/isa/intr_machdep.c
+++ b/sys/i386/isa/intr_machdep.c
@@ -34,7 +34,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)isa.c	7.2 (Berkeley) 5/13/91
- *	$Id: intr_machdep.c,v 1.12 1998/06/18 15:32:06 bde Exp $
+ *	$Id: intr_machdep.c,v 1.13 1998/06/18 16:08:46 bde Exp $
  */
 
 #include "opt_auto_eoi.h"
@@ -429,12 +429,15 @@ icu_setup(int intr, inthand2_t *handler, void *arg, u_int *maskptr, int flags)
 	set_lapic_isrloc(intr, vector);
 #endif
 	/*
-	 * XXX MULTIPLE_IOAPICSXXX
 	 * Reprogram the vector in the IO APIC.
 	 */
-	select = (intr * 2) + IOAPIC_REDTBL0;
-	value = io_apic_read(0, select) & ~IOART_INTVEC;
-	io_apic_write(0, select, value | vector);
+	if (int_to_apicintpin[intr].ioapic >= 0) {
+		select = int_to_apicintpin[intr].redirindex;
+		value = io_apic_read(int_to_apicintpin[intr].ioapic, 
+				     select) & ~IOART_INTVEC;
+		io_apic_write(int_to_apicintpin[intr].ioapic, 
+			      select, value | vector);
+	}
 #else
 	setidt(ICU_OFFSET + intr,
 	       flags & INTR_FAST ? fastintr[intr] : slowintr[intr],
diff --git a/sys/i386/isa/nmi.c b/sys/i386/isa/nmi.c
index 49c7f24..3f891f2 100644
--- a/sys/i386/isa/nmi.c
+++ b/sys/i386/isa/nmi.c
@@ -34,7 +34,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)isa.c	7.2 (Berkeley) 5/13/91
- *	$Id: intr_machdep.c,v 1.12 1998/06/18 15:32:06 bde Exp $
+ *	$Id: intr_machdep.c,v 1.13 1998/06/18 16:08:46 bde Exp $
  */
 
 #include "opt_auto_eoi.h"
@@ -429,12 +429,15 @@ icu_setup(int intr, inthand2_t *handler, void *arg, u_int *maskptr, int flags)
 	set_lapic_isrloc(intr, vector);
 #endif
 	/*
-	 * XXX MULTIPLE_IOAPICSXXX
 	 * Reprogram the vector in the IO APIC.
 	 */
-	select = (intr * 2) + IOAPIC_REDTBL0;
-	value = io_apic_read(0, select) & ~IOART_INTVEC;
-	io_apic_write(0, select, value | vector);
+	if (int_to_apicintpin[intr].ioapic >= 0) {
+		select = int_to_apicintpin[intr].redirindex;
+		value = io_apic_read(int_to_apicintpin[intr].ioapic, 
+				     select) & ~IOART_INTVEC;
+		io_apic_write(int_to_apicintpin[intr].ioapic, 
+			      select, value | vector);
+	}
 #else
 	setidt(ICU_OFFSET + intr,
 	       flags & INTR_FAST ? fastintr[intr] : slowintr[intr],