Remove cx in its old location.

Approved by: re@ <scottl>

4 files changed, 0 insertions, 3199 deletions

diff --git a/sys/i386/isa/cronyx.c b/sys/i386/isa/cronyx.c
deleted file mode 100644
index 836df21..0000000
--- a/sys/i386/isa/cronyx.c
+++ /dev/null
@@ -1,1032 +0,0 @@
-/*
- * Low-level subroutines for Cronyx-Sigma adapter.
- *
- * Copyright (C) 1994-95 Cronyx Ltd.
- * Author: Serge Vakulenko, <vak@cronyx.ru>
- *
- * This software is distributed with NO WARRANTIES, not even the implied
- * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Authors grant any other persons or organisations permission to use
- * or modify this software as long as this message is kept with the software,
- * all derivative works or modified versions.
- *
- * Version 1.6, Wed May 31 16:03:20 MSD 1995
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-#if defined (MSDOS) || defined (__MSDOS__)
-#   include <string.h>
-#   include <dos.h>
-#   define inb(port)    inportb(port)
-#   define inw(port)    inport(port)
-#   define outb(port,b) outportb(port,b)
-#   define outw(port,w)	outport(port,w)
-#   define vtophys(a)	(((unsigned long)(a)>>12 & 0xffff0) +\
-			((unsigned)(a) & 0xffff))
-#   include "cronyx.h"
-#   include "cxreg.h"
-#else
-#   include <sys/param.h>
-#   include <sys/systm.h>
-#   include <sys/socket.h>
-#   include <net/if.h>
-#   include <vm/vm.h>
-#   include <vm/vm_param.h>
-#   include <vm/pmap.h>
-#   ifndef __FreeBSD__
-#      include <machine/inline.h>
-#   endif
-#   include <machine/cronyx.h>
-#   include <i386/isa/cxreg.h>
-#endif
-
-#define DMA_MASK	0xd4	/* DMA mask register */
-#define DMA_MASK_CLEAR	0x04	/* DMA clear mask */
-#define DMA_MODE	0xd6	/* DMA mode register */
-#define DMA_MODE_MASTER	0xc0	/* DMA master mode */
-
-#define BYTE *(unsigned char*)&
-
-static unsigned char irqmask [] = {
-	BCR0_IRQ_DIS,	BCR0_IRQ_DIS,	BCR0_IRQ_DIS,	BCR0_IRQ_3,
-	BCR0_IRQ_DIS,	BCR0_IRQ_5,	BCR0_IRQ_DIS,	BCR0_IRQ_7,
-	BCR0_IRQ_DIS,	BCR0_IRQ_DIS,	BCR0_IRQ_10,	BCR0_IRQ_11,
-	BCR0_IRQ_12,	BCR0_IRQ_DIS,	BCR0_IRQ_DIS,	BCR0_IRQ_15,
-};
-
-static unsigned char dmamask [] = {
-	BCR0_DMA_DIS,	BCR0_DMA_DIS,	BCR0_DMA_DIS,	BCR0_DMA_DIS,
-	BCR0_DMA_DIS,	BCR0_DMA_5,	BCR0_DMA_6,	BCR0_DMA_7,
-};
-
-static long cx_rxbaud = CX_SPEED_DFLT;	/* receiver baud rate */
-static long cx_txbaud = CX_SPEED_DFLT;	/* transmitter baud rate */
-
-static int cx_univ_mode = M_ASYNC;	/* univ. chan. mode: async or sync */
-static int cx_sync_mode = M_HDLC;	/* sync. chan. mode: HDLC, Bisync or X.21 */
-static int cx_iftype = 0;		/* univ. chan. interface: upper/lower */
-
-static cx_chan_opt_t chan_opt_dflt = { /* mode-independent options */
-	{			/* cor4 */
-		7,		/* FIFO threshold, odd is better */
-		0,
-		0,              /* don't detect 1 to 0 on CTS */
-		1,		/* detect 1 to 0 on CD */
-		0,              /* detect 1 to 0 on DSR */
-	},
-	{			/* cor5 */
-		0,		/* receive flow control FIFO threshold */
-		0,
-		0,              /* don't detect 0 to 1 on CTS */
-		1,		/* detect 0 to 1 on CD */
-		0,              /* detect 0 to 1 on DSR */
-	},
-	{			/* rcor */
-		0,		/* dummy clock source */
-		ENCOD_NRZ,      /* NRZ mode */
-		0,              /* disable DPLL */
-		0,
-		0,		/* transmit line value */
-	},
-	{			/* tcor */
-		0,
-		0,		/* local loopback mode */
-		0,
-		1,		/* external 1x clock mode */
-		0,
-		0,		/* dummy transmit clock source */
-	},
-};
-
-static cx_opt_async_t opt_async_dflt = { /* default async options */
-	{			/* cor1 */
-		8-1,		/* 8-bit char length */
-		0,		/* don't ignore parity */
-		PARM_NOPAR,	/* no parity */
-		PAR_EVEN,	/* even parity */
-	},
-	{			/* cor2 */
-		0,              /* disable automatic DSR */
-		1,              /* enable automatic CTS */
-		0,              /* disable automatic RTS */
-		0,		/* no remote loopback */
-		0,
-		0,              /* disable embedded cmds */
-		0,		/* disable XON/XOFF */
-		0,		/* disable XANY */
-	},
-	{			/* cor3 */
-		STOPB_1,	/* 1 stop bit */
-		0,
-		0,		/* disable special char detection */
-		FLOWCC_PASS,	/* pass flow ctl chars to the host */
-		0,		/* range detect disable */
-		0,		/* disable extended spec. char detect */
-	},
-	{			/* cor6 */
-		PERR_INTR,	/* generate exception on parity errors */
-		BRK_INTR,	/* generate exception on break condition */
-		0,		/* don't translate NL to CR on input */
-		0,		/* don't translate CR to NL on input */
-		0,		/* don't discard CR on input */
-	},
-	{			/* cor7 */
-		0,		/* don't translate CR to NL on output */
-		0,		/* don't translate NL to CR on output */
-		0,
-		0,		/* don't process flow ctl err chars */
-		0,		/* disable LNext option */
-		0,		/* don't strip 8 bit on input */
-	},
-	0, 0, 0, 0, 0, 0, 0,	/* clear schr1-4, scrl, scrh, lnxt */
-};
-
-static cx_opt_hdlc_t opt_hdlc_dflt = { /* default hdlc options */
-	{			/* cor1 */
-		2,              /* 2 inter-frame flags */
-		0,		/* no-address mode */
-		CLRDET_DISABLE,	/* disable clear detect */
-		AFLO_1OCT,	/* 1-byte address field length */
-	},
-	{			/* cor2 */
-		0,		/* disable automatic DSR */
-		0,              /* disable automatic CTS */
-		0,              /* disable automatic RTS */
-		0,
-		CRC_INVERT,	/* use CRC V.41 */
-		0,
-		FCS_NOTPASS,	/* don't pass received CRC to the host */
-		0,
-	},
-	{			/* cor3 */
-		0,              /* 0 pad characters sent */
-		IDLE_FLAG,	/* idle in flag */
-		0,		/* enable FCS */
-		FCSP_ONES,	/* FCS preset to all ones (V.41) */
-		SYNC_AA,	/* use AAh as sync char */
-		0,              /* disable pad characters */
-	},
-	0, 0, 0, 0,		/* clear rfar1-4 */
-	POLY_V41,		/* use V.41 CRC polynomial */
-};
-
-static cx_opt_bisync_t opt_bisync_dflt = { /* default bisync options */
-	{			/* cor1 */
-		8-1,            /* 8-bit char length */
-		0,		/* don't ignore parity */
-		PARM_NOPAR,	/* no parity */
-		PAR_EVEN,	/* even parity */
-	},
-	{			/* cor2 */
-		3-2,            /* send three SYN chars */
-		CRC_DONT_INVERT,/* don't invert CRC (CRC-16) */
-		0,		/* use ASCII, not EBCDIC */
-		0,		/* disable bcc append */
-		BCC_CRC16,	/* user CRC16, not LRC */
-	},
-	{			/* cor3 */
-		0,              /* send 0 pad chars */
-		IDLE_FLAG,	/* idle in SYN */
-		0,		/* enable FCS */
-		FCSP_ZEROS,	/* FCS preset to all zeros (CRC-16) */
-		PAD_AA,		/* use AAh as pad char */
-		0,		/* disable pad characters */
-	},
-	{			/* cor6 */
-		10,		/* DLE - disable special termination char */
-	},
-	POLY_16,		/* use CRC-16 polynomial */
-};
-
-static cx_opt_x21_t opt_x21_dflt = {   /* default x21 options */
-	{			/* cor1 */
-		8-1,            /* 8-bit char length */
-		0,		/* don't ignore parity */
-		PARM_NOPAR,	/* no parity */
-		PAR_EVEN,	/* even parity */
-	},
-	{			/* cor2 */
-		0,
-		0,		/* disable embedded transmitter cmds */
-		0,
-	},
-	{			/* cor3 */
-		0,
-		0,		/* disable special character detect */
-		0,		/* don't treat SYN as special condition */
-		0,		/* disable steady state detect */
-		X21SYN_2,	/* 2 SYN chars on receive are required */
-	},
-	{			/* cor6 */
-		16,		/* SYN - standard SYN character */
-	},
-	0, 0, 0,		/* clear schr1-3 */
-};
-
-static int cx_probe_chip (int base);
-static void cx_setup_chip (cx_chip_t *c);
-static void cx_init_board (cx_board_t *b, int num, int port, int irq, int dma,
-	int chain, int rev, int osc, int rev2, int osc2);
-static void cx_reinit_board (cx_board_t *b);
-
-/*
- * Wait for CCR to clear.
- */
-void cx_cmd (int base, int cmd)
-{
-	unsigned short port = CCR(base);
-	unsigned short count;
-
-	/* Wait 10 msec for the previous command to complete. */
-	for (count=0; inb(port) && count<20000; ++count)
-		continue;
-
-	/* Issue the command. */
-	outb (port, cmd);
-
-	/* Wait 10 msec for the command to complete. */
-	for (count=0; inb(port) && count<20000; ++count)
-		continue;
-}
-
-/*
- * Reset the chip.
- */
-static int cx_reset (unsigned short port)
-{
-	int count;
-
-	/* Wait up to 10 msec for revision code to appear after reset. */
-	for (count=0; count<20000; ++count)
-		if (inb(GFRCR(port)) != 0)
-			break;
-
-	cx_cmd (port, CCR_RSTALL);
-
-	/* Firmware revision code should clear imediately. */
-	/* Wait up to 10 msec for revision code to appear again. */
-	for (count=0; count<20000; ++count)
-		if (inb(GFRCR(port)) != 0)
-			return (1);
-
-	/* Reset failed. */
-	return (0);
-}
-
-/*
- * Check if the CD2400 board is present at the given base port.
- */
-static int cx_probe_chained_board (int port, int *c0, int *c1)
-{
-	int rev, i;
-
-	/* Read and check the board revision code. */
-	rev = inb (BSR(port));
-	*c0 = *c1 = 0;
-	switch (rev & BSR_VAR_MASK) {
-	case CRONYX_100:	*c0 = 1;	break;
-	case CRONYX_400:	*c1 = 1;	break;
-	case CRONYX_500:	*c0 = *c1 = 1;	break;
-	case CRONYX_410:	*c0 = 1;	break;
-	case CRONYX_810:	*c0 = *c1 = 1;	break;
-	case CRONYX_410s:	*c0 = 1;	break;
-	case CRONYX_810s:	*c0 = *c1 = 1;	break;
-	case CRONYX_440:	*c0 = 1;	break;
-	case CRONYX_840:	*c0 = *c1 = 1;	break;
-	case CRONYX_401:	*c0 = 1;	break;
-	case CRONYX_801:	*c0 = *c1 = 1;	break;
-	case CRONYX_401s:	*c0 = 1;	break;
-	case CRONYX_801s:	*c0 = *c1 = 1;	break;
-	case CRONYX_404:	*c0 = 1;	break;
-	case CRONYX_703:	*c0 = *c1 = 1;	break;
-	default:		return (0);	/* invalid variant code */
-	}
-
-	switch (rev & BSR_OSC_MASK) {
-	case BSR_OSC_20:	/* 20 MHz */
-	case BSR_OSC_18432:	/* 18.432 MHz */
-		break;
-	default:
-		return (0);	/* oscillator frequency does not match */
-	}
-
-	for (i=2; i<0x10; i+=2)
-		if ((inb (BSR(port)+i) & BSR_REV_MASK) != (rev & BSR_REV_MASK))
-			return (0);	/* status changed? */
-	return (1);
-}
-
-/*
- * Check if the CD2400 board is present at the given base port.
- */
-int
-cx_probe_board (int port)
-{
-	int c0, c1, c2=0, c3=0, result;
-
-	if (! cx_probe_chained_board (port, &c0, &c1))
-		return (0);     /* no board detected */
-
-	if (! (inb (BSR(port)) & BSR_NOCHAIN)) { /* chained board attached */
-		if (! cx_probe_chained_board (port + 0x10, &c2, &c3))
-			return (0);     /* invalid chained board? */
-
-		if (! (inb (BSR(port+0x10)) & BSR_NOCHAIN))
-			return (0);     /* invalid chained board flag? */
-	}
-
-	/* Turn off the reset bit. */
-	outb (BCR0(port), BCR0_NORESET);
-	if (c2 || c3)
-		outb (BCR0(port + 0x10), BCR0_NORESET);
-
-	result = 1;
-	if (c0 && ! cx_probe_chip (CS0(port)))
-		result = 0;	/* no CD2400 chip here */
-	else if (c1 && ! cx_probe_chip (CS1(port)))
-		result = 0;	/* no second CD2400 chip */
-	else if (c2 && ! cx_probe_chip (CS0(port + 0x10)))
-		result = 0;	/* no CD2400 chip on the slave board */
-	else if (c3 && ! cx_probe_chip (CS1(port + 0x10)))
-		result = 0;	/* no second CD2400 chip on the slave board */
-
-	/* Reset the controller. */
-	outb (BCR0(port), 0);
-	if (c2 || c3)
-		outb (BCR0(port + 0x10), 0);
-
-	/* Yes, we really have valid CD2400 board. */
-	return (result);
-}
-
-/*
- * Check if the CD2400 chip is present at the given base port.
- */
-static int cx_probe_chip (int base)
-{
-	int rev, newrev, count;
-
-	/* Wait up to 10 msec for revision code to appear after reset. */
-	for (count=0; inb(GFRCR(base))==0; ++count)
-		if (count >= 20000)
-			return (0); /* reset failed */
-
-	/* Read and check the global firmware revision code. */
-	rev = inb (GFRCR(base));
-	if (rev<REVCL_MIN || rev>REVCL_MAX)
-		return (0);	/* CD2400 revision does not match */
-
-	/* Reset the chip. */
-	if (! cx_reset (base))
-		return (0);
-
-	/* Read and check the new global firmware revision code. */
-	newrev = inb (GFRCR(base));
-	if (newrev != rev)
-		return (0);	/* revision changed */
-
-	/* Yes, we really have CD2400 chip here. */
-	return (1);
-}
-
-/*
- * Probe and initialize the board structure.
- */
-void cx_init (cx_board_t *b, int num, int port, int irq, int dma)
-{
-	int rev, chain, rev2;
-
-	rev = inb (BSR(port));
-	chain = !(rev & BSR_NOCHAIN);
-	rev2 = chain ? inb (BSR(port+0x10)) : 0;
-	cx_init_board (b, num, port, irq, dma, chain,
-		(rev & BSR_VAR_MASK), (rev & BSR_OSC_MASK),
-		(rev2 & BSR_VAR_MASK), (rev2 & BSR_OSC_MASK));
-}
-
-/*
- * Initialize the board structure, given the type of the board.
- */
-static void
-cx_init_board (cx_board_t *b, int num, int port, int irq, int dma,
-	int chain, int rev, int osc, int rev2, int osc2)
-{
-	cx_chan_t *c;
-	int i, c0, c1;
-
-	/* Initialize board structure. */
-	b->port = port;
-	b->num = num;
-	b->irq = irq;
-	b->dma = dma;
-	b->if0type = b->if8type = cx_iftype;
-
-	/* Set channels 0 and 8 mode, set DMA and IRQ. */
-	b->bcr0 = b->bcr0b = BCR0_NORESET | dmamask[b->dma] | irqmask[b->irq];
-
-	/* Clear DTR[0..3] and DTR[8..12]. */
-	b->bcr1 = b->bcr1b = 0;
-
-	/* Initialize chip structures. */
-	for (i=0; i<NCHIP; ++i) {
-		b->chip[i].num = i;
-		b->chip[i].board = b;
-	}
-	b->chip[0].port = CS0(port);
-	b->chip[1].port = CS1(port);
-	b->chip[2].port = CS0(port+0x10);
-	b->chip[3].port = CS1(port+0x10);
-
-	/*------------------ Master board -------------------*/
-
-	/* Read and check the board revision code. */
-	c0 = c1 = 0;
-	b->name[0] = 0;
-	switch (rev) {
-	case CRONYX_100:  strcpy (b->name, "100");  c0 = 1;      break;
-	case CRONYX_400:  strcpy (b->name, "400");  c1 = 1;      break;
-	case CRONYX_500:  strcpy (b->name, "500");  c0 = c1 = 1; break;
-	case CRONYX_410:  strcpy (b->name, "410");  c0 = 1;      break;
-	case CRONYX_810:  strcpy (b->name, "810");  c0 = c1 = 1; break;
-	case CRONYX_410s: strcpy (b->name, "410s"); c0 = 1;      break;
-	case CRONYX_810s: strcpy (b->name, "810s"); c0 = c1 = 1; break;
-	case CRONYX_440:  strcpy (b->name, "440");  c0 = 1;      break;
-	case CRONYX_840:  strcpy (b->name, "840");  c0 = c1 = 1; break;
-	case CRONYX_401:  strcpy (b->name, "401");  c0 = 1;      break;
-	case CRONYX_801:  strcpy (b->name, "801");  c0 = c1 = 1; break;
-	case CRONYX_401s: strcpy (b->name, "401s"); c0 = 1;      break;
-	case CRONYX_801s: strcpy (b->name, "801s"); c0 = c1 = 1; break;
-	case CRONYX_404:  strcpy (b->name, "404");  c0 = 1;      break;
-	case CRONYX_703:  strcpy (b->name, "703");  c0 = c1 = 1; break;
-	}
-
-	switch (osc) {
-	default:
-	case BSR_OSC_20: /* 20 MHz */
-		b->chip[0].oscfreq = b->chip[1].oscfreq = 20000000L;
-		strcat (b->name, "a");
-		break;
-	case BSR_OSC_18432: /* 18.432 MHz */
-		b->chip[0].oscfreq = b->chip[1].oscfreq = 18432000L;
-		strcat (b->name, "b");
-		break;
-	}
-
-	if (! c0)
-		b->chip[0].port = 0;
-	if (! c1)
-		b->chip[1].port = 0;
-
-	/*------------------ Slave board -------------------*/
-
-	if (! chain) {
-		b->chip[2].oscfreq = b->chip[3].oscfreq = 0L;
-		b->chip[2].port = b->chip[3].port = 0;
-	} else {
-		/* Read and check the board revision code. */
-		c0 = c1 = 0;
-		strcat (b->name, "/");
-		switch (rev2) {
-		case CRONYX_100:  strcat(b->name,"100");  c0=1;    break;
-		case CRONYX_400:  strcat(b->name,"400");  c1=1;    break;
-		case CRONYX_500:  strcat(b->name,"500");  c0=c1=1; break;
-		case CRONYX_410:  strcat(b->name,"410");  c0=1;    break;
-		case CRONYX_810:  strcat(b->name,"810");  c0=c1=1; break;
-		case CRONYX_410s: strcat(b->name,"410s"); c0=1;    break;
-		case CRONYX_810s: strcat(b->name,"810s"); c0=c1=1; break;
-		case CRONYX_440:  strcat(b->name,"440");  c0=1;    break;
-		case CRONYX_840:  strcat(b->name,"840");  c0=c1=1; break;
-		case CRONYX_401:  strcat(b->name,"401");  c0=1;    break;
-		case CRONYX_801:  strcat(b->name,"801");  c0=c1=1; break;
-		case CRONYX_401s: strcat(b->name,"401s"); c0=1;    break;
-		case CRONYX_801s: strcat(b->name,"801s"); c0=c1=1; break;
-		case CRONYX_404:  strcat(b->name,"404");  c0=1;    break;
-		case CRONYX_703:  strcat(b->name,"703");  c0=c1=1; break;
-		}
-
-		switch (osc2) {
-		default:
-		case BSR_OSC_20: /* 20 MHz */
-			b->chip[2].oscfreq = b->chip[3].oscfreq = 20000000L;
-			strcat (b->name, "a");
-			break;
-		case BSR_OSC_18432: /* 18.432 MHz */
-			b->chip[2].oscfreq = b->chip[3].oscfreq = 18432000L;
-			strcat (b->name, "b");
-			break;
-		}
-
-		if (! c0)
-			b->chip[2].port = 0;
-		if (! c1)
-			b->chip[3].port = 0;
-	}
-
-	/* Initialize channel structures. */
-	for (i=0; i<NCHAN; ++i) {
-		cx_chan_t *c = b->chan + i;
-
-		c->num = i;
-		c->board = b;
-		c->chip = b->chip + i*NCHIP/NCHAN;
-		c->stat = b->stat + i;
-		c->type = T_NONE;
-	}
-
-	/*------------------ Master board -------------------*/
-
-	switch (rev) {
-	case CRONYX_400:
-		break;
-	case CRONYX_100:
-	case CRONYX_500:
-		b->chan[0].type = T_UNIV_RS232;
-		break;
-	case CRONYX_410:
-	case CRONYX_810:
-		b->chan[0].type = T_UNIV_V35;
-		for (i=1; i<4; ++i)
-			b->chan[i].type = T_UNIV_RS232;
-		break;
-	case CRONYX_410s:
-	case CRONYX_810s:
-		b->chan[0].type = T_UNIV_V35;
-		for (i=1; i<4; ++i)
-			b->chan[i].type = T_SYNC_RS232;
-		break;
-	case CRONYX_440:
-	case CRONYX_840:
-		b->chan[0].type = T_UNIV_V35;
-		for (i=1; i<4; ++i)
-			b->chan[i].type = T_SYNC_V35;
-		break;
-	case CRONYX_401:
-	case CRONYX_801:
-		b->chan[0].type = T_UNIV_RS449;
-		for (i=1; i<4; ++i)
-			b->chan[i].type = T_UNIV_RS232;
-		break;
-	case CRONYX_401s:
-	case CRONYX_801s:
-		b->chan[0].type = T_UNIV_RS449;
-		for (i=1; i<4; ++i)
-			b->chan[i].type = T_SYNC_RS232;
-		break;
-	case CRONYX_404:
-		b->chan[0].type = T_UNIV_RS449;
-		for (i=1; i<4; ++i)
-			b->chan[i].type = T_SYNC_RS449;
-		break;
-	case CRONYX_703:
-		b->chan[0].type = T_UNIV_RS449;
-		for (i=1; i<3; ++i)
-			b->chan[i].type = T_SYNC_RS449;
-		break;
-	}
-
-	/* If the second controller is present,
-	 * then we have 4..7 channels in async. mode */
-	if (b->chip[1].port)
-		for (i=4; i<8; ++i)
-			b->chan[i].type = T_UNIV_RS232;
-
-	/*------------------ Slave board -------------------*/
-
-	if (chain) {
-		switch (rev2) {
-		case CRONYX_400:
-			break;
-		case CRONYX_100:
-		case CRONYX_500:
-			b->chan[8].type = T_UNIV_RS232;
-			break;
-		case CRONYX_410:
-		case CRONYX_810:
-			b->chan[8].type = T_UNIV_V35;
-			for (i=9; i<12; ++i)
-				b->chan[i].type = T_UNIV_RS232;
-			break;
-		case CRONYX_410s:
-		case CRONYX_810s:
-			b->chan[8].type = T_UNIV_V35;
-			for (i=9; i<12; ++i)
-				b->chan[i].type = T_SYNC_RS232;
-			break;
-		case CRONYX_440:
-		case CRONYX_840:
-			b->chan[8].type = T_UNIV_V35;
-			for (i=9; i<12; ++i)
-				b->chan[i].type = T_SYNC_V35;
-			break;
-		case CRONYX_401:
-		case CRONYX_801:
-			b->chan[8].type = T_UNIV_RS449;
-			for (i=9; i<12; ++i)
-				b->chan[i].type = T_UNIV_RS232;
-			break;
-		case CRONYX_401s:
-		case CRONYX_801s:
-			b->chan[8].type = T_UNIV_RS449;
-			for (i=9; i<12; ++i)
-				b->chan[i].type = T_UNIV_RS232;
-			break;
-		case CRONYX_404:
-			b->chan[8].type = T_UNIV_RS449;
-			for (i=9; i<12; ++i)
-				b->chan[i].type = T_SYNC_RS449;
-			break;
-		case CRONYX_703:
-			b->chan[8].type = T_UNIV_RS449;
-			for (i=9; i<11; ++i)
-				b->chan[i].type = T_SYNC_RS449;
-			break;
-		}
-
-		/* If the second controller is present,
-		 * then we have 4..7 channels in async. mode */
-		if (b->chip[3].port)
-			for (i=12; i<16; ++i)
-				b->chan[i].type = T_UNIV_RS232;
-	}
-
-	b->nuniv = b->nsync = b->nasync = 0;
-	for (c=b->chan; c<b->chan+NCHAN; ++c)
-		switch (c->type) {
-		case T_ASYNC:      ++b->nasync; break;
-		case T_UNIV_RS232:
-		case T_UNIV_RS449:
-		case T_UNIV_V35:   ++b->nuniv;  break;
-		case T_SYNC_RS232:
-		case T_SYNC_V35:
-		case T_SYNC_RS449: ++b->nsync;  break;
-		}
-
-	cx_reinit_board (b);
-}
-
-/*
- * Reinitialize all channels, using new options and baud rate.
- */
-static void
-cx_reinit_board (cx_board_t *b)
-{
-	cx_chan_t *c;
-
-	b->if0type = b->if8type = cx_iftype;
-	for (c=b->chan; c<b->chan+NCHAN; ++c) {
-		switch (c->type) {
-		default:
-		case T_NONE:
-			continue;
-		case T_UNIV_RS232:
-		case T_UNIV_RS449:
-		case T_UNIV_V35:
-			c->mode = (cx_univ_mode == M_ASYNC) ?
-				M_ASYNC : cx_sync_mode;
-			break;
-		case T_SYNC_RS232:
-		case T_SYNC_V35:
-		case T_SYNC_RS449:
-			c->mode = cx_sync_mode;
-			break;
-		case T_ASYNC:
-			c->mode = M_ASYNC;
-			break;
-		}
-		c->rxbaud = cx_rxbaud;
-		c->txbaud = cx_txbaud;
-		c->opt = chan_opt_dflt;
-		c->aopt = opt_async_dflt;
-		c->hopt = opt_hdlc_dflt;
-		c->bopt = opt_bisync_dflt;
-		c->xopt = opt_x21_dflt;
-	}
-}
-
-/*
- * Set up the board.
- */
-void cx_setup_board (cx_board_t *b)
-{
-	int i;
-
-	/* Disable DMA channel. */
-	outb (DMA_MASK, (b->dma & 3) | DMA_MASK_CLEAR);
-
-	/* Reset the controller. */
-	outb (BCR0(b->port), 0);
-	if (b->chip[2].port || b->chip[3].port)
-		outb (BCR0(b->port+0x10), 0);
-
-	/*
-	 * Set channels 0 and 8 to RS232 async. mode.
-	 * Enable DMA and IRQ.
-	 */
-	outb (BCR0(b->port), b->bcr0);
-	if (b->chip[2].port || b->chip[3].port)
-		outb (BCR0(b->port+0x10), b->bcr0b);
-
-	/* Clear DTR[0..3] and DTR[8..12]. */
-	outw (BCR1(b->port), b->bcr1);
-	if (b->chip[2].port || b->chip[3].port)
-		outw (BCR1(b->port+0x10), b->bcr1b);
-
-	/* Initialize all controllers. */
-	for (i=0; i<NCHIP; ++i)
-		if (b->chip[i].port)
-			cx_setup_chip (b->chip + i);
-
-	/* Set up DMA channel to master mode. */
-	outb (DMA_MODE, (b->dma & 3) | DMA_MODE_MASTER);
-
-	/* Enable DMA channel. */
-	outb (DMA_MASK, b->dma & 3);
-
-	/* Initialize all channels. */
-	for (i=0; i<NCHAN; ++i)
-		if (b->chan[i].type != T_NONE)
-			cx_setup_chan (b->chan + i);
-}
-
-/*
- * Initialize the board.
- */
-static void cx_setup_chip (cx_chip_t *c)
-{
-	/* Reset the chip. */
-	cx_reset (c->port);
-
-	/*
-	 * Set all interrupt level registers to the same value.
-	 * This enables the internal CD2400 priority scheme.
-	 */
-	outb (RPILR(c->port), BRD_INTR_LEVEL);
-	outb (TPILR(c->port), BRD_INTR_LEVEL);
-	outb (MPILR(c->port), BRD_INTR_LEVEL);
-
-	/* Set bus error count to zero. */
-	outb (BERCNT(c->port), 0);
-
-	/* Set 16-bit DMA mode. */
-	outb (DMR(c->port), 0);
-
-	/* Set timer period register to 1 msec (approximately). */
-	outb (TPR(c->port), 10);
-}
-
-/*
- * Initialize the CD2400 channel.
- */
-void cx_setup_chan (cx_chan_t *c)
-{
-	unsigned short port = c->chip->port;
-	int clock, period;
-
-	if (c->num == 0) {
-		c->board->bcr0 &= ~BCR0_UMASK;
-		if (c->mode != M_ASYNC)
-			c->board->bcr0 |= BCR0_UM_SYNC;
-		if (c->board->if0type &&
-		    (c->type==T_UNIV_RS449 || c->type==T_UNIV_V35))
-			c->board->bcr0 |= BCR0_UI_RS449;
-		outb (BCR0(c->board->port), c->board->bcr0);
-	} else if (c->num == 8) {
-		c->board->bcr0b &= ~BCR0_UMASK;
-		if (c->mode != M_ASYNC)
-			c->board->bcr0b |= BCR0_UM_SYNC;
-		if (c->board->if8type &&
-		    (c->type==T_UNIV_RS449 || c->type==T_UNIV_V35))
-			c->board->bcr0b |= BCR0_UI_RS449;
-		outb (BCR0(c->board->port+0x10), c->board->bcr0b);
-	}
-
-	/* set current channel number */
-	outb (CAR(port), c->num & 3);
-
-	/* reset the channel */
-	cx_cmd (port, CCR_CLRCH);
-
-	/* set LIVR to contain the board and channel numbers */
-	outb (LIVR(port), c->board->num << 6 | c->num << 2);
-
-	/* clear DTR, RTS, set TXCout/DTR pin */
-	outb (MSVR_RTS(port), 0);
-	outb (MSVR_DTR(port), c->mode==M_ASYNC ? 0 : MSV_TXCOUT);
-
-	switch (c->mode) {	/* initialize the channel mode */
-	case M_ASYNC:
-		/* set receiver timeout register */
-		outw (RTPR(port), 10);          /* 10 msec, see TPR */
-
-		outb (CMR(port), CMR_RXDMA | CMR_TXDMA | CMR_ASYNC);
-		outb (COR1(port), BYTE c->aopt.cor1);
-		outb (COR2(port), BYTE c->aopt.cor2);
-		outb (COR3(port), BYTE c->aopt.cor3);
-		outb (COR6(port), BYTE c->aopt.cor6);
-		outb (COR7(port), BYTE c->aopt.cor7);
-		outb (SCHR1(port), c->aopt.schr1);
-		outb (SCHR2(port), c->aopt.schr2);
-		outb (SCHR3(port), c->aopt.schr3);
-		outb (SCHR4(port), c->aopt.schr4);
-		outb (SCRL(port), c->aopt.scrl);
-		outb (SCRH(port), c->aopt.scrh);
-		outb (LNXT(port), c->aopt.lnxt);
-		break;
-	case M_HDLC:
-		outb (CMR(port), CMR_RXDMA | CMR_TXDMA | CMR_HDLC);
-		outb (COR1(port), BYTE c->hopt.cor1);
-		outb (COR2(port), BYTE c->hopt.cor2);
-		outb (COR3(port), BYTE c->hopt.cor3);
-		outb (RFAR1(port), c->hopt.rfar1);
-		outb (RFAR2(port), c->hopt.rfar2);
-		outb (RFAR3(port), c->hopt.rfar3);
-		outb (RFAR4(port), c->hopt.rfar4);
-		outb (CPSR(port), c->hopt.cpsr);
-		break;
-	case M_BISYNC:
-		outb (CMR(port), CMR_RXDMA | CMR_TXDMA | CMR_BISYNC);
-		outb (COR1(port), BYTE c->bopt.cor1);
-		outb (COR2(port), BYTE c->bopt.cor2);
-		outb (COR3(port), BYTE c->bopt.cor3);
-		outb (COR6(port), BYTE c->bopt.cor6);
-		outb (CPSR(port), c->bopt.cpsr);
-		break;
-	case M_X21:
-		outb (CMR(port), CMR_RXDMA | CMR_TXDMA | CMR_X21);
-		outb (COR1(port), BYTE c->xopt.cor1);
-		outb (COR2(port), BYTE c->xopt.cor2);
-		outb (COR3(port), BYTE c->xopt.cor3);
-		outb (COR6(port), BYTE c->xopt.cor6);
-		outb (SCHR1(port), c->xopt.schr1);
-		outb (SCHR2(port), c->xopt.schr2);
-		outb (SCHR3(port), c->xopt.schr3);
-		break;
-	}
-
-	/* set mode-independent options */
-	outb (COR4(port), BYTE c->opt.cor4);
-	outb (COR5(port), BYTE c->opt.cor5);
-
-	/* set up receiver clock values */
-	if (c->mode == M_ASYNC || c->opt.rcor.dpll) {
-		cx_clock (c->chip->oscfreq, c->rxbaud, &clock, &period);
-		c->opt.rcor.clk = clock;
-	} else {
-		c->opt.rcor.clk = CLK_EXT;
-		period = 1;
-	}
-	outb (RCOR(port), BYTE c->opt.rcor);
-	outb (RBPR(port), period);
-
-	/* set up transmitter clock values */
-	if (c->mode == M_ASYNC || !c->opt.tcor.ext1x) {
-		unsigned ext1x = c->opt.tcor.ext1x;
-		c->opt.tcor.ext1x = 0;
-		cx_clock (c->chip->oscfreq, c->txbaud, &clock, &period);
-		c->opt.tcor.clk = clock;
-		c->opt.tcor.ext1x = ext1x;
-	} else {
-		c->opt.tcor.clk = CLK_EXT;
-		period = 1;
-	}
-	outb (TCOR(port), BYTE c->opt.tcor);
-	outb (TBPR(port), period);
-
-	/* set receiver A buffer physical address */
-	c->arphys = vtophys (c->arbuf);
-	outw (ARBADRU(port), (unsigned short) (c->arphys>>16));
-	outw (ARBADRL(port), (unsigned short) c->arphys);
-
-	/* set receiver B buffer physical address */
-	c->brphys = vtophys (c->brbuf);
-	outw (BRBADRU(port), (unsigned short) (c->brphys>>16));
-	outw (BRBADRL(port), (unsigned short) c->brphys);
-
-	/* set transmitter A buffer physical address */
-	c->atphys = vtophys (c->atbuf);
-	outw (ATBADRU(port), (unsigned short) (c->atphys>>16));
-	outw (ATBADRL(port), (unsigned short) c->atphys);
-
-	/* set transmitter B buffer physical address */
-	c->btphys = vtophys (c->btbuf);
-	outw (BTBADRU(port), (unsigned short) (c->btphys>>16));
-	outw (BTBADRL(port), (unsigned short) c->btphys);
-
-	c->dtr = 0;
-	c->rts = 0;
-}
-
-/*
- * Control DTR signal for the channel.
- * Turn it on/off.
- */
-void cx_chan_dtr (cx_chan_t *c, int on)
-{
-	c->dtr = on ? 1 : 0;
-
-	if (c->mode == M_ASYNC) {
-		outb (CAR(c->chip->port), c->num & 3);
-		outb (MSVR_DTR(c->chip->port), on ? MSV_DTR : 0);
-		return;
-	}
-
-	switch (c->num) {
-	default:
-		/* Channels 4..7 and 12..15 in syncronous mode
-		 * have no DTR signal. */
-		break;
-
-	case 1: case 2:  case 3:
-		if (c->type == T_UNIV_RS232)
-			break;
-	case 0:
-		if (on)
-			c->board->bcr1 |= 0x100 << c->num;
-		else
-			c->board->bcr1 &= ~(0x100 << c->num);
-		outw (BCR1(c->board->port), c->board->bcr1);
-		break;
-
-	case 9: case 10: case 11:
-		if (c->type == T_UNIV_RS232)
-			break;
-	case 8:
-		if (on)
-			c->board->bcr1b |= 0x100 << (c->num & 3);
-		else
-			c->board->bcr1b &= ~(0x100 << (c->num & 3));
-		outw (BCR1(c->board->port+0x10), c->board->bcr1b);
-		break;
-	}
-}
-
-/*
- * Control RTS signal for the channel.
- * Turn it on/off.
- */
-void
-cx_chan_rts (cx_chan_t *c, int on)
-{
-	c->rts = on ? 1 : 0;
-	outb (CAR(c->chip->port), c->num & 3);
-	outb (MSVR_RTS(c->chip->port), on ? MSV_RTS : 0);
-}
-
-
-/*
- * Get the state of CARRIER signal of the channel.
- */
-int
-cx_chan_cd (cx_chan_t *c)
-{
-	unsigned char sigval;
-
-	if (c->mode == M_ASYNC) {
-		outb (CAR(c->chip->port), c->num & 3);
-		return (inb (MSVR(c->chip->port)) & MSV_CD ? 1 : 0);
-	}
-
-	/*
-	 * Channels 4..7 and 12..15 don't have CD signal available.
-	 */
-	switch (c->num) {
-	default:
-		return (1);
-
-	case 1: case 2:  case 3:
-		if (c->type == T_UNIV_RS232)
-			return (1);
-	case 0:
-		sigval = inw (BSR(c->board->port)) >> 8;
-		break;
-
-	case 9: case 10: case 11:
-		if (c->type == T_UNIV_RS232)
-			return (1);
-	case 8:
-		sigval = inw (BSR(c->board->port+0x10)) >> 8;
-		break;
-	}
-	return (~sigval >> 4 >> (c->num & 3) & 1);
-}
-
-/*
- * Compute CD2400 clock values.
- */
-void cx_clock (long hz, long ba, int *clk, int *div)
-{
-	static short clocktab[] = { 8, 32, 128, 512, 2048, 0 };
-
-	for (*clk=0; clocktab[*clk]; ++*clk) {
-		long c = ba * clocktab[*clk];
-		if (hz <= c*256) {
-			*div = (2 * hz + c) / (2 * c) - 1;
-			return;
-		}
-	}
-	/* Incorrect baud rate.  Return some meaningful values. */
-	*clk = 0;
-	*div = 255;
-}
diff --git a/sys/i386/isa/cx.c b/sys/i386/isa/cx.c
deleted file mode 100644
index a2a4693..0000000
--- a/sys/i386/isa/cx.c
+++ /dev/null
@@ -1,883 +0,0 @@
-/*
- * Cronyx-Sigma adapter driver for FreeBSD.
- * Supports PPP/HDLC protocol in synchronous mode,
- * and asyncronous channels with full modem control.
- *
- * Copyright (C) 1994 Cronyx Ltd.
- * Author: Serge Vakulenko, <vak@zebub.msk.su>
- *
- * This software is distributed with NO WARRANTIES, not even the implied
- * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Authors grant any other persons or organisations permission to use
- * or modify this software as long as this message is kept with the software,
- * all derivative works or modified versions.
- *
- * Version 1.9, Wed Oct  4 18:58:15 MSK 1995
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#undef DEBUG
-
-#include "cx.h"
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/fcntl.h>
-#include <sys/conf.h>
-#include <sys/tty.h>
-#include <sys/socket.h>
-#include <net/if.h>
-
-#      define t_out t_outq
-#      define RB_LEN(q) ((q).c_cc)
-#      define RB_GETC(q) getc(&q)
-#ifndef TSA_CARR_ON /* FreeBSD 2.x before not long after 2.0.5 */
-#      define TSA_CARR_ON(tp) tp
-#      define TSA_OLOWAT(q) ((caddr_t)&(q)->t_out)
-#endif
-
-#include <machine/cronyx.h>
-#include <i386/isa/cxreg.h>
-
-/* XXX imported from if_cx.c. */
-void cxswitch (cx_chan_t *c, cx_soft_opt_t new);
-
-/* XXX exported. */
-void cxmint (cx_chan_t *c);
-int cxrinta (cx_chan_t *c);
-void cxtinta (cx_chan_t *c);
-timeout_t cxtimeout;
-
-#ifdef DEBUG
-#   define print(s)     printf s
-#else
-#   define print(s)     {/*void*/}
-#endif
-
-#define DMABUFSZ        (6*256)         /* buffer size */
-#define BYTE            *(unsigned char*)&
-#define UNIT(u)         (minor(u) & 077)
-#define UNIT_CTL        077
-
-extern cx_board_t cxboard [NCX];        /* adapter state structures */
-extern cx_chan_t *cxchan [NCX*NCHAN];   /* unit to channel struct pointer */
-static struct tty cx_tty [NCX*NCHAN];          /* tty data */
-
-static	d_open_t	cxopen;
-static	d_close_t	cxclose;
-static	d_ioctl_t	cxioctl;
-
-#define	CDEV_MAJOR	42
-/* Don't make this static, since if_cx.c uses it. */
-struct cdevsw cx_cdevsw = {
-	.d_open =	cxopen,
-	.d_close =	cxclose,
-	.d_read =	ttyread,
-	.d_write =	ttywrite,
-	.d_ioctl =	cxioctl,
-	.d_poll =	ttypoll,
-	.d_name =	"cx",
-	.d_maj =	CDEV_MAJOR,
-	.d_flags =	D_TTY,
-	.d_kqfilter =	ttykqfilter,
-};
-
-static void cxoproc (struct tty *tp);
-static void cxstop (struct tty *tp, int flag);
-static int cxparam (struct tty *tp, struct termios *t);
-
-static int
-cxopen (dev_t dev, int flag, int mode, struct thread *td)
-{
-	int unit = UNIT (dev);
-	cx_chan_t *c = cxchan[unit];
-	unsigned short port;
-	struct tty *tp;
-	int error = 0;
-
-	if (unit == UNIT_CTL) {
-		print (("cx: cxopen /dev/cronyx\n"));
-		return (0);
-	}
-	if (unit >= NCX*NCHAN || !c || c->type==T_NONE)
-		return (ENXIO);
-	port = c->chip->port;
-	print (("cx%d.%d: cxopen unit=%d\n", c->board->num, c->num, unit));
-	if (c->mode != M_ASYNC)
-		return (EBUSY);
-	if (! c->ttyp) {
-		c->ttyp = &cx_tty[unit];
-		c->ttyp->t_oproc = cxoproc;
-		c->ttyp->t_stop = cxstop;
-		c->ttyp->t_param = cxparam;
-	}
-	dev->si_tty = c->ttyp;
-	tp = c->ttyp;
-	tp->t_dev = dev;
-	if ((tp->t_state & TS_ISOPEN) && (tp->t_state & TS_XCLUDE) &&
-	    suser(td))
-		return (EBUSY);
-	if (! (tp->t_state & TS_ISOPEN)) {
-		ttychars (tp);
-		if (tp->t_ispeed == 0) {
-			tp->t_iflag = 0;
-			tp->t_oflag = 0;
-			tp->t_lflag = 0;
-			tp->t_cflag = CREAD | CS8 | HUPCL;
-			tp->t_ispeed = c->rxbaud;
-			tp->t_ospeed = c->txbaud;
-		}
-		cxparam (tp, &tp->t_termios);
-		ttsetwater (tp);
-	}
-
-	spltty ();
-	if (! (tp->t_state & TS_ISOPEN)) {
-		/*
-		 * Compute optimal receiver buffer length.
-		 * The best choice is rxbaud/400.
-		 * Make it even, to avoid byte-wide DMA transfers.
-		 * --------------------------
-		 * Baud rate    Buffer length
-		 * --------------------------
-		 *      300     4
-		 *     1200     4
-		 *     9600     24
-		 *    19200     48
-		 *    38400     96
-		 *    57600     192
-		 *   115200     288
-		 * --------------------------
-		 */
-		int rbsz = (c->rxbaud + 800 - 1) / 800 * 2;
-		if (rbsz < 4)
-			rbsz = 4;
-		else if (rbsz > DMABUFSZ)
-			rbsz = DMABUFSZ;
-
-		/* Initialize channel, enable receiver. */
-		cx_cmd (port, CCR_INITCH | CCR_ENRX);
-		cx_cmd (port, CCR_INITCH | CCR_ENRX);
-
-		/* Start receiver. */
-		outw (ARBCNT(port), rbsz);
-		outw (BRBCNT(port), rbsz);
-		outw (ARBSTS(port), BSTS_OWN24);
-		outw (BRBSTS(port), BSTS_OWN24);
-
-		/* Enable interrupts. */
-		outb (IER(port), IER_RXD | IER_RET | IER_TXD | IER_MDM);
-
-		cx_chan_dtr (c, 1);
-		cx_chan_rts (c, 1);
-	}
-	if (cx_chan_cd (c))
-		(*linesw[tp->t_line].l_modem)(tp, 1);
-	if (! (flag & O_NONBLOCK)) {
-		/* Lock the channel against cxconfig while we are
-		 * waiting for carrier. */
-		c->sopt.lock = 1;
-		while (!(tp->t_cflag & CLOCAL) && !(tp->t_state & TS_CARR_ON))
-			if ((error = tsleep (TSA_CARR_ON(tp), TTIPRI | PCATCH,
-			    "cxdcd", 0)))
-				break;
-		c->sopt.lock = 0;       /* Unlock the channel. */
-	}
-	print (("cx%d.%d: cxopen done csr=%b\n", c->board->num, c->num,
-		inb(CSR(c->chip->port)), CSRA_BITS));
-	spl0 ();
-	if (error)
-		return (error);
-	error = (*linesw[tp->t_line].l_open) (dev, tp);
-	return (error);
-}
-
-static int
-cxclose (dev_t dev, int flag, int mode, struct thread *td)
-{
-	int unit = UNIT (dev);
-	cx_chan_t *c = cxchan[unit];
-	struct tty *tp;
-	int s;
-
-	if (unit == UNIT_CTL)
-		return (0);
-	tp = c->ttyp;
-	(*linesw[tp->t_line].l_close) (tp, flag);
-
-	/* Disable receiver.
-	 * Transmitter continues sending the queued data. */
-	s = spltty ();
-	outb (CAR(c->chip->port), c->num & 3);
-	outb (IER(c->chip->port), IER_TXD | IER_MDM);
-	cx_cmd (c->chip->port, CCR_DISRX);
-
-	/* Clear DTR and RTS. */
-	if ((tp->t_cflag & HUPCL) || ! (tp->t_state & TS_ISOPEN)) {
-		cx_chan_dtr (c, 0);
-		cx_chan_rts (c, 0);
-	}
-
-	/* Stop sending break. */
-	if (c->brk == BRK_SEND) {
-		c->brk = BRK_STOP;
-		if (! (tp->t_state & TS_BUSY))
-			cxoproc (tp);
-	}
-	splx (s);
-	ttyclose (tp);
-	return (0);
-}
-
-static int
-cxioctl (dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td)
-{
-	int unit = UNIT (dev);
-	cx_chan_t *c, *m;
-	cx_stat_t *st;
-	struct tty *tp;
-	int error, s;
-	unsigned char msv;
-	struct ifnet *master;
-
-	if (unit == UNIT_CTL) {
-		/* Process an ioctl request on /dev/cronyx */
-		cx_options_t *o = (cx_options_t*) data;
-
-		if (o->board >= NCX || o->channel >= NCHAN)
-			return (EINVAL);
-		c = &cxboard[o->board].chan[o->channel];
-		if (c->type == T_NONE)
-			return (ENXIO);
-		switch (cmd) {
-		default:
-			return (EINVAL);
-
-		case CXIOCSETMODE:
-			print (("cx%d.%d: CXIOCSETMODE\n", o->board, o->channel));
-			if (c->type == T_NONE)
-				return (EINVAL);
-			if (c->type == T_ASYNC && o->mode != M_ASYNC)
-				return (EINVAL);
-			if (o->mode == M_ASYNC)
-				switch (c->type) {
-				case T_SYNC_RS232:
-				case T_SYNC_V35:
-				case T_SYNC_RS449:
-					return (EINVAL);
-				}
-			/* Somebody is waiting for carrier? */
-			if (c->sopt.lock)
-				return (EBUSY);
-			/* /dev/ttyXX is already opened by someone? */
-			if (c->mode == M_ASYNC && c->ttyp &&
-			    (c->ttyp->t_state & TS_ISOPEN))
-				return (EBUSY);
-			/* Network interface is up? */
-			if (c->mode != M_ASYNC && (c->ifp->if_flags & IFF_UP))
-				return (EBUSY);
-
-			/* Find the master interface. */
-			master = *o->master ? ifunit (o->master) : c->ifp;
-			if (! master)
-				return (EINVAL);
-			m = cxchan[master->if_dunit];
-
-			/* Leave the previous master queue. */
-			if (c->master != c->ifp) {
-				cx_chan_t *p = cxchan[c->master->if_dunit];
-
-				for (; p; p=p->slaveq)
-					if (p->slaveq == c)
-						p->slaveq = c->slaveq;
-			}
-
-			/* Set up new master. */
-			c->master = master;
-			c->slaveq = 0;
-
-			/* Join the new master queue. */
-			if (c->master != c->ifp) {
-				c->slaveq = m->slaveq;
-				m->slaveq = c;
-			}
-
-			c->mode   = o->mode;
-			c->rxbaud = o->rxbaud;
-			c->txbaud = o->txbaud;
-			c->opt    = o->opt;
-			c->aopt   = o->aopt;
-			c->hopt   = o->hopt;
-			c->bopt   = o->bopt;
-			c->xopt   = o->xopt;
-			switch (c->num) {
-			case 0: c->board->if0type = o->iftype; break;
-			case 8: c->board->if8type = o->iftype; break;
-			}
-			s = spltty ();
-			cxswitch (c, o->sopt);
-			cx_setup_chan (c);
-			outb (IER(c->chip->port), 0);
-			splx (s);
-			break;
-
-		case CXIOCGETSTAT:
-			st = (cx_stat_t*) data;
-			st->rintr  = c->stat->rintr;
-			st->tintr  = c->stat->tintr;
-			st->mintr  = c->stat->mintr;
-			st->ibytes = c->stat->ibytes;
-			st->ipkts  = c->stat->ipkts;
-			st->ierrs  = c->stat->ierrs;
-			st->obytes = c->stat->obytes;
-			st->opkts  = c->stat->opkts;
-			st->oerrs  = c->stat->oerrs;
-			break;
-
-		case CXIOCGETMODE:
-			print (("cx%d.%d: CXIOCGETMODE\n", o->board, o->channel));
-			o->type   = c->type;
-			o->mode   = c->mode;
-			o->rxbaud = c->rxbaud;
-			o->txbaud = c->txbaud;
-			o->opt    = c->opt;
-			o->aopt   = c->aopt;
-			o->hopt   = c->hopt;
-			o->bopt   = c->bopt;
-			o->xopt   = c->xopt;
-			o->sopt   = c->sopt;
-			switch (c->num) {
-			case 0: o->iftype = c->board->if0type; break;
-			case 8: o->iftype = c->board->if8type; break;
-			}
-			if (c->master != c->ifp)
-				strlcpy(o->master, c->master->if_xname,
-				    sizeof(o->master));
-			else
-				*o->master = 0;
-			break;
-		}
-		return (0);
-	}
-
-	c = cxchan[unit];
-	tp = c->ttyp;
-	if (! tp)
-		return (EINVAL);
-	error = (*linesw[tp->t_line].l_ioctl) (tp, cmd, data, flag, td);
-	if (error != ENOIOCTL)
-		return (error);
-	error = ttioctl (tp, cmd, data, flag);
-	if (error != ENOIOCTL)
-		return (error);
-
-	s = spltty ();
-	switch (cmd) {
-	default:
-		splx (s);
-		return (ENOTTY);
-	case TIOCSBRK:          /* Start sending line break */
-		c->brk = BRK_SEND;
-		if (! (tp->t_state & TS_BUSY))
-			cxoproc (tp);
-		break;
-	case TIOCCBRK:          /* Stop sending line break */
-		c->brk = BRK_STOP;
-		if (! (tp->t_state & TS_BUSY))
-			cxoproc (tp);
-		break;
-	case TIOCSDTR:          /* Set DTR */
-		cx_chan_dtr (c, 1);
-		break;
-	case TIOCCDTR:          /* Clear DTR */
-		cx_chan_dtr (c, 0);
-		break;
-	case TIOCMSET:          /* Set DTR/RTS */
-		cx_chan_dtr (c, (*(int*)data & TIOCM_DTR) ? 1 : 0);
-		cx_chan_rts (c, (*(int*)data & TIOCM_RTS) ? 1 : 0);
-		break;
-	case TIOCMBIS:          /* Add DTR/RTS */
-		if (*(int*)data & TIOCM_DTR) cx_chan_dtr (c, 1);
-		if (*(int*)data & TIOCM_RTS) cx_chan_rts (c, 1);
-		break;
-	case TIOCMBIC:          /* Clear DTR/RTS */
-		if (*(int*)data & TIOCM_DTR) cx_chan_dtr (c, 0);
-		if (*(int*)data & TIOCM_RTS) cx_chan_rts (c, 0);
-		break;
-	case TIOCMGET:          /* Get modem status */
-		msv = inb (MSVR(c->chip->port));
-		*(int*)data = TIOCM_LE; /* always enabled while open */
-		if (msv & MSV_DSR) *(int*)data |= TIOCM_DSR;
-		if (msv & MSV_CTS) *(int*)data |= TIOCM_CTS;
-		if (msv & MSV_CD)  *(int*)data |= TIOCM_CD;
-		if (c->dtr)        *(int*)data |= TIOCM_DTR;
-		if (c->rts)        *(int*)data |= TIOCM_RTS;
-		break;
-	}
-	splx (s);
-	return (0);
-}
-
-/*
- * Fill transmitter buffer with data.
- */
-static void
-cxout (cx_chan_t *c, char b)
-{
-	unsigned char *buf, *p, sym;
-	unsigned short port = c->chip->port, len = 0, cnt_port, sts_port;
-	struct tty *tp = c->ttyp;
-
-	if (! tp)
-		return;
-
-	/* Choose the buffer. */
-	if (b == 'A') {
-		buf      = c->atbuf;
-		cnt_port = ATBCNT(port);
-		sts_port = ATBSTS(port);
-	} else {
-		buf      = c->btbuf;
-		cnt_port = BTBCNT(port);
-		sts_port = BTBSTS(port);
-	}
-
-	/* Is it busy? */
-	if (inb (sts_port) & BSTS_OWN24) {
-		tp->t_state |= TS_BUSY;
-		return;
-	}
-
-	switch (c->brk) {
-	case BRK_SEND:
-		*buf++ = 0;     /* extended transmit command */
-		*buf++ = 0x81;  /* send break */
-		*buf++ = 0;     /* extended transmit command */
-		*buf++ = 0x82;  /* insert delay */
-		*buf++ = 250;   /* 1/4 of second */
-		*buf++ = 0;     /* extended transmit command */
-		*buf++ = 0x82;  /* insert delay */
-		*buf++ = 250;   /* + 1/4 of second */
-		len = 8;
-		c->brk = BRK_IDLE;
-		break;
-	case BRK_STOP:
-		*buf++ = 0;     /* extended transmit command */
-		*buf++ = 0x83;  /* stop break */
-		len = 2;
-		c->brk = BRK_IDLE;
-		break;
-	case BRK_IDLE:
-		p = buf;
-		if (tp->t_iflag & IXOFF)
-			while (RB_LEN (tp->t_out) && p<buf+DMABUFSZ-1) {
-				sym = RB_GETC (tp->t_out);
-				/* Send XON/XOFF out of band. */
-				if (sym == tp->t_cc[VSTOP]) {
-					outb (STCR(port), STC_SNDSPC|STC_SSPC_2);
-					continue;
-				}
-				if (sym == tp->t_cc[VSTART]) {
-					outb (STCR(port), STC_SNDSPC|STC_SSPC_1);
-					continue;
-				}
-				/* Duplicate NULLs in ETC mode. */
-				if (! sym)
-					*p++ = 0;
-				*p++ = sym;
-			}
-		else
-			while (RB_LEN (tp->t_out) && p<buf+DMABUFSZ-1) {
-				sym = RB_GETC (tp->t_out);
-				/* Duplicate NULLs in ETC mode. */
-				if (! sym)
-					*p++ = 0;
-				*p++ = sym;
-			}
-		len = p - buf;
-		break;
-	}
-
-	/* Start transmitter. */
-	if (len) {
-		outw (cnt_port, len);
-		outb (sts_port, BSTS_INTR | BSTS_OWN24);
-		c->stat->obytes += len;
-		tp->t_state |= TS_BUSY;
-		print (("cx%d.%d: out %d bytes to %c\n",
-			c->board->num, c->num, len, b));
-	}
-}
-
-static void
-cxoproc (struct tty *tp)
-{
-	int unit = UNIT (tp->t_dev);
-	cx_chan_t *c = cxchan[unit];
-	unsigned short port = c->chip->port;
-	int s = spltty ();
-
-	/* Set current channel number */
-	outb (CAR(port), c->num & 3);
-
-	if (! (tp->t_state & (TS_TIMEOUT | TS_TTSTOP))) {
-		/* Start transmitter. */
-		if (! (inb (CSR(port)) & CSRA_TXEN))
-			cx_cmd (port, CCR_ENTX);
-
-		/* Determine the buffer order. */
-		if (inb (DMABSTS(port)) & DMABSTS_NTBUF) {
-			cxout (c, 'B');
-			cxout (c, 'A');
-		} else {
-			cxout (c, 'A');
-			cxout (c, 'B');
-		}
-	}
-#ifndef TS_ASLEEP /* FreeBSD some time after 2.0.5 */
-	ttwwakeup(tp);
-#else
-	if (RB_LEN (tp->t_out) <= tp->t_lowat) {
-		if (tp->t_state & TS_ASLEEP) {
-			tp->t_state &= ~TS_ASLEEP;
-			wakeup(TSA_OLOWAT(tp));
-		}
-		selwakeuppri(&tp->t_wsel, TTOPRI);
-	}
-#endif
-	splx (s);
-}
-
-static int
-cxparam (struct tty *tp, struct termios *t)
-{
-	int unit = UNIT (tp->t_dev);
-	cx_chan_t *c = cxchan[unit];
-	unsigned short port = c->chip->port;
-	int clock, period, s;
-	cx_cor1_async_t cor1;
-
-	if (t->c_ospeed == 0) {
-		/* Clear DTR and RTS. */
-		s = spltty ();
-		cx_chan_dtr (c, 0);
-		cx_chan_rts (c, 0);
-		splx (s);
-		print (("cx%d.%d: cxparam (hangup)\n", c->board->num, c->num));
-		return (0);
-	}
-	print (("cx%d.%d: cxparam\n", c->board->num, c->num));
-
-	/* Check requested parameters. */
-	if (t->c_ospeed < 300 || t->c_ospeed > 256*1024)
-                return(EINVAL);
-	if (t->c_ispeed && (t->c_ispeed < 300 || t->c_ispeed > 256*1024))
-                return(EINVAL);
-
-	/* And copy them to tty and channel structures. */
-	c->rxbaud = tp->t_ispeed = t->c_ispeed;
-	c->txbaud = tp->t_ospeed = t->c_ospeed;
-	tp->t_cflag = t->c_cflag;
-
-	/* Set character length and parity mode. */
-	BYTE cor1 = 0;
-	switch (t->c_cflag & CSIZE) {
-	default:
-	case CS8: cor1.charlen = 7; break;
-	case CS7: cor1.charlen = 6; break;
-	case CS6: cor1.charlen = 5; break;
-	case CS5: cor1.charlen = 4; break;
-	}
-	if (t->c_cflag & PARENB) {
-		cor1.parmode = PARM_NORMAL;
-		cor1.ignpar = 0;
-		cor1.parity = (t->c_cflag & PARODD) ? PAR_ODD : PAR_EVEN;
-	} else {
-		cor1.parmode = PARM_NOPAR;
-		cor1.ignpar = 1;
-	}
-
-	/* Enable/disable hardware CTS. */
-	c->aopt.cor2.ctsae = (t->c_cflag & CRTSCTS) ? 1 : 0;
-	/* Handle DSR as CTS. */
-	c->aopt.cor2.dsrae = (t->c_cflag & CRTSCTS) ? 1 : 0;
-	/* Enable extended transmit command mode.
-	 * Unfortunately, there is no other method for sending break. */
-	c->aopt.cor2.etc = 1;
-	/* Enable/disable hardware XON/XOFF. */
-	c->aopt.cor2.ixon = (t->c_iflag & IXON) ? 1 : 0;
-	c->aopt.cor2.ixany = (t->c_iflag & IXANY) ? 1 : 0;
-
-	/* Set the number of stop bits. */
-	if (t->c_cflag & CSTOPB)
-		c->aopt.cor3.stopb = STOPB_2;
-	else
-		c->aopt.cor3.stopb = STOPB_1;
-	/* Disable/enable passing XON/XOFF chars to the host. */
-	c->aopt.cor3.scde = (t->c_iflag & IXON) ? 1 : 0;
-	c->aopt.cor3.flowct = (t->c_iflag & IXON) ? FLOWCC_NOTPASS : FLOWCC_PASS;
-
-	c->aopt.schr1 = t->c_cc[VSTART];        /* XON */
-	c->aopt.schr2 = t->c_cc[VSTOP];         /* XOFF */
-
-	/* Set current channel number. */
-	s = spltty ();
-	outb (CAR(port), c->num & 3);
-
-	/* Set up receiver clock values. */
-	cx_clock (c->chip->oscfreq, c->rxbaud, &clock, &period);
-	c->opt.rcor.clk = clock;
-	outb (RCOR(port), BYTE c->opt.rcor);
-	outb (RBPR(port), period);
-
-	/* Set up transmitter clock values. */
-	cx_clock (c->chip->oscfreq, c->txbaud, &clock, &period);
-	c->opt.tcor.clk = clock;
-	c->opt.tcor.ext1x = 0;
-	outb (TCOR(port), BYTE c->opt.tcor);
-	outb (TBPR(port), period);
-
-	outb (COR2(port), BYTE c->aopt.cor2);
-	outb (COR3(port), BYTE c->aopt.cor3);
-	outb (SCHR1(port), c->aopt.schr1);
-	outb (SCHR2(port), c->aopt.schr2);
-
-	if (BYTE c->aopt.cor1 != BYTE cor1) {
-		BYTE c->aopt.cor1 = BYTE cor1;
-		outb (COR1(port), BYTE c->aopt.cor1);
-		/* Any change to COR1 require reinitialization. */
-		/* Unfortunately, it may cause transmitter glitches... */
-		cx_cmd (port, CCR_INITCH);
-	}
-	splx (s);
-	return (0);
-}
-
-/*
- * Stop output on a line
- */
-static void
-cxstop (struct tty *tp, int flag)
-{
-	cx_chan_t *c = cxchan[UNIT(tp->t_dev)];
-	unsigned short port = c->chip->port;
-	int s = spltty ();
-
-	if (tp->t_state & TS_BUSY) {
-		print (("cx%d.%d: cxstop\n", c->board->num, c->num));
-
-		/* Set current channel number */
-		outb (CAR(port), c->num & 3);
-
-		/* Stop transmitter */
-		cx_cmd (port, CCR_DISTX);
-	}
-	splx (s);
-}
-
-/*
- * Handle receive interrupts, including receive errors and
- * receive timeout interrupt.
- */
-int cxrinta (cx_chan_t *c)
-{
-	unsigned short port = c->chip->port;
-	unsigned short len = 0, risr = inw (RISR(port)), reoir = 0;
-	struct tty *tp = c->ttyp;
-
-	/* Compute optimal receiver buffer length. */
-	int rbsz = (c->rxbaud + 800 - 1) / 800 * 2;
-	if (rbsz < 4)
-		rbsz = 4;
-	else if (rbsz > DMABUFSZ)
-		rbsz = DMABUFSZ;
-
-	if (risr & RISA_TIMEOUT) {
-		unsigned long rcbadr = (unsigned short) inw (RCBADRL(port)) |
-			(long) inw (RCBADRU(port)) << 16;
-		unsigned char *buf = 0;
-		unsigned short cnt_port = 0, sts_port = 0;
-		if (rcbadr >= c->brphys && rcbadr < c->brphys+DMABUFSZ) {
-			buf = c->brbuf;
-			len = rcbadr - c->brphys;
-			cnt_port = BRBCNT(port);
-			sts_port = BRBSTS(port);
-		} else if (rcbadr >= c->arphys && rcbadr < c->arphys+DMABUFSZ) {
-			buf = c->arbuf;
-			len = rcbadr - c->arphys;
-			cnt_port = ARBCNT(port);
-			sts_port = ARBSTS(port);
-		} else
-			printf ("cx%d.%d: timeout: invalid buffer address\n",
-				c->board->num, c->num);
-
-		if (len) {
-			print (("cx%d.%d: async receive timeout (%d bytes), risr=%b, arbsts=%b, brbsts=%b\n",
-				c->board->num, c->num, len, risr, RISA_BITS,
-				inb (ARBSTS(port)), BSTS_BITS, inb (BRBSTS(port)), BSTS_BITS));
-			c->stat->ibytes += len;
-			if (tp && (tp->t_state & TS_ISOPEN)) {
-				int i;
-				int (*rint)(int, struct tty *) =
-					linesw[tp->t_line].l_rint;
-
-				for (i=0; i<len; ++i)
-					(*rint) (buf[i], tp);
-			}
-
-			/* Restart receiver. */
-			outw (cnt_port, rbsz);
-			outb (sts_port, BSTS_OWN24);
-		}
-		return (REOI_TERMBUFF);
-	}
-
-	print (("cx%d.%d: async receive interrupt, risr=%b, arbsts=%b, brbsts=%b\n",
-		c->board->num, c->num, risr, RISA_BITS,
-		inb (ARBSTS(port)), BSTS_BITS, inb (BRBSTS(port)), BSTS_BITS));
-
-	if (risr & RIS_BUSERR) {
-		printf ("cx%d.%d: receive bus error\n", c->board->num, c->num);
-		++c->stat->ierrs;
-	}
-	if (risr & (RIS_OVERRUN | RISA_PARERR | RISA_FRERR | RISA_BREAK)) {
-		int err = 0;
-
-		if (risr & RISA_PARERR)
-			err |= TTY_PE;
-		if (risr & RISA_FRERR)
-			err |= TTY_FE;
-#ifdef TTY_OE
-		if (risr & RIS_OVERRUN)
-			err |= TTY_OE;
-#endif
-#ifdef TTY_BI
-		if (risr & RISA_BREAK)
-			err |= TTY_BI;
-#endif
-		print (("cx%d.%d: receive error %x\n", c->board->num, c->num, err));
-		if (tp && (tp->t_state & TS_ISOPEN))
-			(*linesw[tp->t_line].l_rint) (err, tp);
-		++c->stat->ierrs;
-	}
-
-	/* Discard exception characters. */
-	if ((risr & RISA_SCMASK) && tp && (tp->t_iflag & IXON))
-		reoir |= REOI_DISCEXC;
-
-	/* Handle received data. */
-	if ((risr & RIS_EOBUF) && tp && (tp->t_state & TS_ISOPEN)) {
-		int (*rint)(int, struct tty *) = linesw[tp->t_line].l_rint;
-		unsigned char *buf;
-		int i;
-
-		len = (risr & RIS_BB) ? inw(BRBCNT(port)) : inw(ARBCNT(port));
-
-		print (("cx%d.%d: async: %d bytes received\n",
-			c->board->num, c->num, len));
-		c->stat->ibytes += len;
-
-		buf = (risr & RIS_BB) ? c->brbuf : c->arbuf;
-		for (i=0; i<len; ++i)
-			(*rint) (buf[i], tp);
-	}
-
-	/* Restart receiver. */
-	if (! (inb (ARBSTS(port)) & BSTS_OWN24)) {
-		outw (ARBCNT(port), rbsz);
-		outb (ARBSTS(port), BSTS_OWN24);
-	}
-	if (! (inb (BRBSTS(port)) & BSTS_OWN24)) {
-		outw (BRBCNT(port), rbsz);
-		outb (BRBSTS(port), BSTS_OWN24);
-	}
-	return (reoir);
-}
-
-/*
- * Handle transmit interrupt.
- */
-void cxtinta (cx_chan_t *c)
-{
-	struct tty *tp = c->ttyp;
-	unsigned short port = c->chip->port;
-	unsigned char tisr = inb (TISR(port));
-
-	print (("cx%d.%d: async transmit interrupt, tisr=%b, atbsts=%b, btbsts=%b\n",
-		c->board->num, c->num, tisr, TIS_BITS,
-		inb (ATBSTS(port)), BSTS_BITS, inb (BTBSTS(port)), BSTS_BITS));
-
-	if (tisr & TIS_BUSERR) {
-		printf ("cx%d.%d: transmit bus error\n",
-			c->board->num, c->num);
-		++c->stat->oerrs;
-	} else if (tisr & TIS_UNDERRUN) {
-		printf ("cx%d.%d: transmit underrun error\n",
-			c->board->num, c->num);
-		++c->stat->oerrs;
-	}
-	if (tp) {
-		tp->t_state &= ~(TS_BUSY | TS_FLUSH);
-		if (tp->t_line)
-			(*linesw[tp->t_line].l_start) (tp);
-		else
-			cxoproc (tp);
-	}
-}
-
-/*
- * Handle modem interrupt.
- */
-void cxmint (cx_chan_t *c)
-{
-	unsigned short port = c->chip->port;
-	unsigned char misr = inb (MISR(port));
-	unsigned char msvr = inb (MSVR(port));
-	struct tty *tp = c->ttyp;
-
-	if (c->mode != M_ASYNC) {
-		printf ("cx%d.%d: unexpected modem interrupt, misr=%b, msvr=%b\n",
-			c->board->num, c->num, misr, MIS_BITS, msvr, MSV_BITS);
-		return;
-	}
-	print (("cx%d.%d: modem interrupt, misr=%b, msvr=%b\n",
-		c->board->num, c->num, misr, MIS_BITS, msvr, MSV_BITS));
-
-	/* Ignore DSR events. */
-	/* Ignore RTC/CTS events, handled by hardware. */
-	/* Handle carrier detect/loss. */
-	if (tp && (misr & MIS_CCD))
-		(*linesw[tp->t_line].l_modem) (tp, (msvr & MSV_CD) != 0);
-}
-
-/*
- * Recover after lost transmit interrupts.
- */
-void cxtimeout (void *a)
-{
-	cx_board_t *b;
-	cx_chan_t *c;
-	struct tty *tp;
-	int s;
-
-	for (b=cxboard; b<cxboard+NCX; ++b)
-		for (c=b->chan; c<b->chan+NCHAN; ++c) {
-			tp = c->ttyp;
-			if (c->type==T_NONE || c->mode!=M_ASYNC || !tp)
-				continue;
-			s = spltty ();
-			if (tp->t_state & TS_BUSY) {
-				tp->t_state &= ~TS_BUSY;
-				if (tp->t_line)
-					(*linesw[tp->t_line].l_start) (tp);
-				else
-					cxoproc (tp);
-			}
-			splx (s);
-		}
-	timeout (cxtimeout, 0, hz*5);
-}
diff --git a/sys/i386/isa/cxreg.h b/sys/i386/isa/cxreg.h
deleted file mode 100644
index 4102f2f..0000000
--- a/sys/i386/isa/cxreg.h
+++ /dev/null
@@ -1,453 +0,0 @@
-/*
- * Defines for Cronyx-Sigma adapter, based on Cirrus Logic multiprotocol
- * controller RISC processor CL-CD2400/2401.
- *
- * Copyright (C) 1994 Cronyx Ltd.
- * Author: Serge Vakulenko, <vak@zebub.msk.su>
- *
- * This software is distributed with NO WARRANTIES, not even the implied
- * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Authors grant any other persons or organizations permission to use
- * or modify this software as long as this message is kept with the software,
- * all derivative works or modified versions.
- *
- * Version 1.0, Fri Oct  7 19:34:06 MSD 1994
- * $FreeBSD$
- */
-#define NBRD      3		/* the maximum number of installed boards */
-#define NPORT     16		/* the number of i/o ports per board */
-
-#define REVCL_MIN 7		/* CD2400 min. revision number G */
-#define REVCL_MAX 11		/* CD2400 max. revision number K */
-
-#define BRD_INTR_LEVEL 0x5a	/* interrupt level (arbitrary PILR value) */
-
-#define CS0(p)	((p) | 0x8000)	/* chip select 0 */
-#define CS1(p)	((p) | 0xc000)	/* chip select 1 */
-#define BSR(p)	(p)		/* board status register, read only */
-#define BCR0(p)	(p)		/* board command register 0, write only */
-#define BCR1(p)	((p) | 0x2000)	/* board command register 1, write only */
-
-/*
- * Chip register address, B is chip base port, R is chip register number.
- */
-#define R(b,r) ((b) | (((r)<<6 & 0x3c00) | ((r) & 0xf)))
-
-/*
- * Interrupt acknowledge register, P is board port, L is interrupt level,
- * as programmed in PILR.
- */
-#define IACK(p,l)   (R(p,l) | 0x4000)
-
-/*
- * Global registers.
- */
-#define GFRCR(b)    R(b,0x82)	/* global firmware revision code register */
-#define CAR(b)      R(b,0xec)	/* channel access register */
-
-/*
- * Option registers.
- */
-#define CMR(b)      R(b,0x18)	/* channel mode register */
-#define COR1(b)     R(b,0x13)	/* channel option register 1 */
-#define COR2(b)     R(b,0x14)	/* channel option register 2 */
-#define COR3(b)     R(b,0x15)	/* channel option register 3 */
-#define COR4(b)     R(b,0x16)	/* channel option register 4 */
-#define COR5(b)     R(b,0x17)	/* channel option register 5 */
-#define COR6(b)     R(b,0x1b)	/* channel option register 6 */
-#define COR7(b)     R(b,0x04)	/* channel option register 7 */
-#define SCHR1(b)    R(b,0x1c)	/* special character register 1 */
-#define SCHR2(b)    R(b,0x1d)	/* special character register 2 */
-#define SCHR3(b)    R(b,0x1e)	/* special character register 3 */
-#define SCHR4(b)    R(b,0x1f)	/* special character register 4 */
-#define SCRL(b)     R(b,0x20)	/* special character range low */
-#define SCRH(b)     R(b,0x21)	/* special character range high */
-#define LNXT(b)     R(b,0x2d)	/* LNext character */
-#define RFAR1(b)    R(b,0x1c)	/* receive frame address register 1 */
-#define RFAR2(b)    R(b,0x1d)	/* receive frame address register 2 */
-#define RFAR3(b)    R(b,0x1e)	/* receive frame address register 3 */
-#define RFAR4(b)    R(b,0x1f)	/* receive frame address register 4 */
-#define CPSR(b)     R(b,0xd4)	/* CRC polynomial select register */
-
-/*
- * Bit rate and clock option registers.
- */
-#define RBPR(b)     R(b,0xc9)	/* receive baud rate period register */
-#define RCOR(b)     R(b,0xca)	/* receive clock option register */
-#define TBPR(b)     R(b,0xc1)	/* transmit baud rate period register */
-#define TCOR(b)     R(b,0xc2)	/* receive clock option register */
-
-/*
- * Channel command and status registers.
- */
-#define CCR(b)      R(b,0x10)	/* channel command register */
-#define STCR(b)     R(b,0x11)	/* special transmit command register */
-#define CSR(b)      R(b,0x19)	/* channel status register */
-#define MSVR(b)     R(b,0xdc)	/* modem signal value register */
-#define MSVR_RTS(b) R(b,0xdc)	/* modem RTS setup register */
-#define MSVR_DTR(b) R(b,0xdd)	/* modem DTR setup register */
-
-/*
- * Interrupt registers.
- */
-#define LIVR(b)     R(b,0x0a)	/* local interrupt vector register */
-#define IER(b)      R(b,0x12)	/* interrupt enable register */
-#define LICR(b)     R(b,0x25)	/* local interrupting channel register */
-#define STK(b)      R(b,0xe0)	/* stack register */
-
-/*
- * Receive interrupt registers.
- */
-#define RPILR(b)    R(b,0xe3)	/* receive priority interrupt level register */
-#define RIR(b)      R(b,0xef)	/* receive interrupt register */
-#define RISR(b)     R(b,0x8a)	/* receive interrupt status register */
-#define RISRL(b)    R(b,0x8a)	/* receive interrupt status register low */
-#define RISRH(b)    R(b,0x8b)	/* receive interrupt status register high */
-#define RFOC(b)     R(b,0x33)	/* receive FIFO output count */
-#define RDR(b)      R(b,0xf8)	/* receive data register */
-#define REOIR(b)    R(b,0x87)	/* receive end of interrupt register */
-
-/*
- * Transmit interrupt registers.
- */
-#define TPILR(b)    R(b,0xe2)	/* transmit priority interrupt level reg */
-#define TIR(b)      R(b,0xee)	/* transmit interrupt register */
-#define TISR(b)     R(b,0x89)	/* transmit interrupt status register */
-#define TFTC(b)     R(b,0x83)	/* transmit FIFO transfer count */
-#define TDR(b)      R(b,0xf8)	/* transmit data register */
-#define TEOIR(b)    R(b,0x86)	/* transmit end of interrupt register */
-
-/*
- * Modem interrupt registers.
- */
-#define MPILR(b)    R(b,0xe1)	/* modem priority interrupt level register */
-#define MIR(b)      R(b,0xed)	/* modem interrupt register */
-#define MISR(b)     R(b,0x88)	/* modem/timer interrupt status register */
-#define MEOIR(b)    R(b,0x85)	/* modem end of interrupt register */
-
-/*
- * DMA registers.
- */
-#define DMR(b)      R(b,0xf4)	/* DMA mode register */
-#define BERCNT(b)   R(b,0x8d)	/* bus error retry count */
-#define DMABSTS(b)  R(b,0x1a)	/* DMA buffer status */
-
-/*
- * DMA receive registers.
- */
-#define ARBADRL(b)  R(b,0x40)	/* A receive buffer address lower */
-#define ARBADRU(b)  R(b,0x42)	/* A receive buffer address upper */
-#define BRBADRL(b)  R(b,0x44)	/* B receive buffer address lower */
-#define BRBADRU(b)  R(b,0x46)	/* B receive buffer address upper */
-#define ARBCNT(b)   R(b,0x48)	/* A receive buffer byte count */
-#define BRBCNT(b)   R(b,0x4a)	/* B receive buffer byte count */
-#define ARBSTS(b)   R(b,0x4c)	/* A receive buffer status */
-#define BRBSTS(b)   R(b,0x4d)	/* B receive buffer status */
-#define RCBADRL(b)  R(b,0x3c)	/* receive current buffer address lower */
-#define RCBADRU(b)  R(b,0x3e)	/* receive current buffer address upper */
-
-/*
- * DMA transmit registers.
- */
-#define ATBADRL(b)  R(b,0x50)	/* A transmit buffer address lower */
-#define ATBADRU(b)  R(b,0x52)	/* A transmit buffer address upper */
-#define BTBADRL(b)  R(b,0x54)	/* B transmit buffer address lower */
-#define BTBADRU(b)  R(b,0x56)	/* B transmit buffer address upper */
-#define ATBCNT(b)   R(b,0x58)	/* A transmit buffer byte count */
-#define BTBCNT(b)   R(b,0x5a)	/* B transmit buffer byte count */
-#define ATBSTS(b)   R(b,0x5c)	/* A transmit buffer status */
-#define BTBSTS(b)   R(b,0x5d)	/* B transmit buffer status */
-#define TCBADRL(b)  R(b,0x38)	/* transmit current buffer address lower */
-#define TCBADRU(b)  R(b,0x3a)	/* transmit current buffer address upper */
-
-/*
- * Timer registers.
- */
-#define TPR(b)      R(b,0xd8)	/* timer period register */
-#define RTPR(b)     R(b,0x26)	/* receive timeout period register */
-#define RTPRL(b)    R(b,0x26)	/* receive timeout period register low */
-#define RTPTH(b)    R(b,0x27)	/* receive timeout period register high */
-#define GT1(b)      R(b,0x28)	/* general timer 1 */
-#define GT1L(b)     R(b,0x28)	/* general timer 1 low */
-#define GT1H(b)     R(b,0x29)	/* general timer 1 high */
-#define GT2(b)      R(b,0x2a)	/* general timer 2 */
-#define TTR(b)      R(b,0x2a)	/* transmit timer register */
-
-/*
- * Board status register bits.
- */
-#define BSR_NOINTR     0x01	/* no interrupt pending flag */
-
-#define BSR_VAR_MASK   0x66	/* adapter variant mask */
-
-#define BSR_OSC_MASK   0x18	/* oscillator frequency mask */
-#define BSR_OSC_20     0x18	/* 20 MHz */
-#define BSR_OSC_18432  0x10	/* 18.432 MHz */
-
-#define BSR_NOCHAIN    0x80	/* no daisy chained board */
-
-#define BSR_NODSR(n)   (0x100 << (n))	/* DSR from channels 0-3, inverted */
-#define BSR_NOCD(n)    (0x1000 << (n))	/* CD from channels 0-3, inverted */
-
-/*
- * Board revision mask.
- */
-#define BSR_REV_MASK   (BSR_OSC_MASK|BSR_VAR_MASK|BSR_NOCHAIN)
-
-/*
- * Board control register 0 bits.
- */
-#define BCR0_IRQ_DIS  0x00	/* no interrupt generated */
-#define BCR0_IRQ_3    0x01	/* select IRQ number 3 */
-#define BCR0_IRQ_5    0x02	/* select IRQ number 5 */
-#define BCR0_IRQ_7    0x03	/* select IRQ number 7 */
-#define BCR0_IRQ_10   0x04	/* select IRQ number 10 */
-#define BCR0_IRQ_11   0x05	/* select IRQ number 11 */
-#define BCR0_IRQ_12   0x06	/* select IRQ number 12 */
-#define BCR0_IRQ_15   0x07	/* select IRQ number 15 */
-
-#define BCR0_NORESET  0x08	/* CD2400 reset flag (inverted) */
-
-#define BCR0_DMA_DIS  0x00	/* no interrupt generated */
-#define BCR0_DMA_5    0x10	/* select DMA channel 5 */
-#define BCR0_DMA_6    0x20	/* select DMA channel 6 */
-#define BCR0_DMA_7    0x30	/* select DMA channel 7 */
-
-#define BCR0_UM_ASYNC 0x00	/* channel 0 mode - async */
-#define BCR0_UM_SYNC  0x80	/* channel 0 mode - sync */
-#define BCR0_UI_RS232 0x00	/* channel 0 interface - RS-232 */
-#define BCR0_UI_RS449 0x40	/* channel 0 interface - RS-449/V.35 */
-#define BCR0_UMASK    0xc0	/* channel 0 interface mask */
-
-/*
- * Board control register 1 bits.
- */
-#define BCR1_DTR(n)  (0x100 << (n))	/* DTR for channels 0-3 sync */
-
-/*
- * Cronyx board variants.
- */
-#define CRONYX_100	0x64
-#define CRONYX_400	0x62
-#define CRONYX_500	0x60
-#define CRONYX_410	0x24
-#define CRONYX_810	0x20
-#define CRONYX_410s	0x04
-#define CRONYX_810s	0x00
-#define CRONYX_440	0x44
-#define CRONYX_840	0x40
-#define CRONYX_401	0x26
-#define CRONYX_801	0x22
-#define CRONYX_401s	0x06
-#define CRONYX_801s	0x02
-#define CRONYX_404	0x46
-#define CRONYX_703	0x42
-
-/*
- * Channel commands (CCR).
- */
-#define CCR_CLRCH  0x40		/* clear channel */
-#define CCR_INITCH 0x20		/* initialize channel */
-#define CCR_RSTALL 0x10		/* reset all channels */
-#define CCR_ENTX   0x08		/* enable transmitter */
-#define CCR_DISTX  0x04		/* disable transmitter */
-#define CCR_ENRX   0x02		/* enable receiver */
-#define CCR_DISRX  0x01		/* disable receiver */
-#define CCR_CLRT1  0xc0		/* clear timer 1 */
-#define CCR_CLRT2  0xa0		/* clear timer 2 */
-#define CCR_CLRRCV 0x90		/* clear receiver */
-
-/*
- * Interrupt enable register (IER) bits.
- */
-#define IER_MDM    0x80		/* modem status changed */
-#define IER_RET    0x20		/* receive exception timeout */
-#define IER_RXD    0x08		/* data received */
-#define IER_TIMER  0x04		/* timer expired */
-#define IER_TXMPTY 0x02		/* transmitter empty */
-#define IER_TXD    0x01		/* data transmitted */
-
-/*
- * Modem signal values register bits (MSVR).
- */
-#define MSV_DSR    0x80		/* state of Data Set Ready input */
-#define MSV_CD     0x40		/* state of Carrier Detect input */
-#define MSV_CTS    0x20		/* state of Clear to Send input */
-#define MSV_TXCOUT 0x10		/* TXCout/DTR pin output flag */
-#define MSV_PORTID 0x04		/* device is CL-CD2401 (not 2400) */
-#define MSV_DTR    0x02		/* state of Data Terminal Ready output */
-#define MSV_RTS    0x01		/* state of Request to Send output */
-#define MSV_BITS "\20\1rts\2dtr\3cd2400\5txcout\6cts\7cd\10dsr"
-
-/*
- * DMA buffer status register bits (DMABSTS).
- */
-#define DMABSTS_TDALIGN 0x80	/* internal data alignment in transmit FIFO */
-#define DMABSTS_RSTAPD  0x40	/* reset append mode */
-#define DMABSTS_CRTTBUF 0x20	/* internal current transmit buffer in use */
-#define DMABSTS_APPEND  0x10	/* append buffer is in use */
-#define DMABSTS_NTBUF   0x08	/* next transmit buffer is B (not A) */
-#define DMABSTS_TBUSY   0x04	/* current transmit buffer is in use */
-#define DMABSTS_NRBUF   0x02	/* next receive buffer is B (not A) */
-#define DMABSTS_RBUSY   0x01	/* current receive buffer is in use */
-
-/*
- * Buffer status register bits ([AB][RT]BSTS).
- */
-#define BSTS_BUSERR 0x80	/* bus error */
-#define BSTS_EOFR   0x40	/* end of frame */
-#define BSTS_EOBUF  0x20	/* end of buffer */
-#define BSTS_APPEND 0x08	/* append mode */
-#define BSTS_INTR   0x02	/* interrupt required */
-#define BSTS_OWN24  0x01	/* buffer is (free to be) used by CD2400 */
-#define BSTS_BITS "\20\1own24\2intr\4append\6eobuf\7eofr\10buserr"
-
-/*
- * Receive interrupt status register (RISR) bits.
- */
-#define RIS_OVERRUN   0x0008	/* overrun error */
-#define RIS_BB        0x0800	/* buffer B status (not A) */
-#define RIS_EOBUF     0x2000	/* end of buffer reached */
-#define RIS_EOFR      0x4000	/* frame reception complete */
-#define RIS_BUSERR    0x8000	/* bus error */
-
-#define RISH_CLRDCT   0x0001	/* X.21 clear detect */
-#define RISH_RESIND   0x0004	/* residual indication */
-#define RISH_CRCERR   0x0010	/* CRC error */
-#define RISH_RXABORT  0x0020	/* abort sequence received */
-#define RISH_EOFR     0x0040	/* complete frame received */
-#define RISH_BITS "\20\1clrdct\3resind\4overrun\5crcerr\6rxabort\7eofr\14bb\16eobuf\17eofr\20buserr"
-
-#define RISA_BREAK    0x0001	/* break signal detected */
-#define RISA_FRERR    0x0002	/* frame error (bad stop bits) */
-#define RISA_PARERR   0x0004	/* parity error */
-#define RISA_SCMASK   0x0070	/* special character detect mask */
-#define RISA_SCHR1    0x0010	/* special character 1 detected */
-#define RISA_SCHR2    0x0020	/* special character 2 detected */
-#define RISA_SCHR3    0x0030	/* special character 3 detected */
-#define RISA_SCHR4    0x0040	/* special character 4 detected */
-#define RISA_SCRANGE  0x0070	/* special character in range detected */
-#define RISA_TIMEOUT  0x0080	/* receive timeout, no data */
-#define RISA_BITS "\20\1break\2frerr\3parerr\4overrun\5schr1\6schr2\7schr4\10timeout\14bb\16eobuf\17eofr\20buserr"
-
-#define RISB_CRCERR   0x0010	/* CRC error */
-#define RISB_RXABORT  0x0020	/* abort sequence received */
-#define RISB_EOFR     0x0040	/* complete frame received */
-
-#define RISX_LEADCHG  0x0001	/* CTS lead change */
-#define RISX_PARERR   0x0004	/* parity error */
-#define RISX_SCMASK   0x0070	/* special character detect mask */
-#define RISX_SCHR1    0x0010	/* special character 1 detected */
-#define RISX_SCHR2    0x0020	/* special character 2 detected */
-#define RISX_SCHR3    0x0030	/* special character 3 detected */
-#define RISX_ALLZERO  0x0040	/* all 0 condition detected */
-#define RISX_ALLONE   0x0050	/* all 1 condition detected */
-#define RISX_ALTOZ    0x0060	/* alternating 1 0 condition detected */
-#define RISX_SYN      0x0070	/* SYN detected */
-#define RISX_LEAD     0x0080	/* leading value */
-
-/*
- * Channel mode register (CMR) bits.
- */
-#define CMR_RXDMA     0x80	/* DMA receive transfer mode */
-#define CMR_TXDMA     0x40	/* DMA transmit transfer mode */
-#define CMR_HDLC      0x00	/* HDLC protocol mode */
-#define CMR_BISYNC    0x01	/* BISYNC protocol mode */
-#define CMR_ASYNC     0x02	/* ASYNC protocol mode */
-#define CMR_X21       0x03	/* X.21 protocol mode */
-
-/*
- * Modem interrupt status register (MISR) bits.
- */
-#define MIS_CDSR      0x80	/* DSR changed */
-#define MIS_CCD       0x40	/* CD changed */
-#define MIS_CCTS      0x20	/* CTS changed */
-#define MIS_CGT2      0x02	/* GT2 timer expired */
-#define MIS_CGT1      0x01	/* GT1 timer expired */
-#define MIS_BITS "\20\1gt1\2gt2\6ccts\7ccd\10cdsr"
-
-/*
- * Transmit interrupt status register (TISR) bits.
- */
-#define TIS_BUSERR    0x80	/* Bus error */
-#define TIS_EOFR      0x40	/* End of frame */
-#define TIS_EOBUF     0x20	/* end of transmit buffer reached */
-#define TIS_UNDERRUN  0x10	/* transmit underrun */
-#define TIS_BB        0x08	/* buffer B status (not A) */
-#define TIS_TXEMPTY   0x02	/* transmitter empty */
-#define TIS_TXDATA    0x01	/* transmit data below threshold */
-#define TIS_BITS "\20\1txdata\2txempty\4bb\5underrun\6eobuf\7eofr\10buserr"
-
-/*
- * Local interrupt vector register (LIVR) bits.
- */
-#define LIV_EXCEP     0
-#define LIV_MODEM     1
-#define LIV_TXDATA    2
-#define LIV_RXDATA    3
-
-/*
- * Transmit end of interrupt registers (TEOIR) bits.
- */
-#define TEOI_TERMBUFF  0x80	/* force current buffer to be discarded */
-#define TEOI_EOFR      0x40	/* end of frame in interrupt mode */
-#define TEOI_SETTM2    0x20	/* set general timer 2 in sync mode */
-#define TEOI_SETTM1    0x10	/* set general timer 1 in sync mode */
-#define TEOI_NOTRANSF  0x08	/* no transfer of data on this interrupt */
-
-/*
- * Receive end of interrupt registers (REOIR) bits.
- */
-#define REOI_TERMBUFF  0x80	/* force current buffer to be terminated */
-#define REOI_DISCEXC   0x40	/* discard exception character */
-#define REOI_SETTM2    0x20	/* set general timer 2 */
-#define REOI_SETTM1    0x10	/* set general timer 1 */
-#define REOI_NOTRANSF  0x08	/* no transfer of data */
-#define REOI_GAP_MASK  0x07	/* optional gap size to leave in buffer */
-
-/*
- * Special transmit command register (STCR) bits.
- */
-#define STC_ABORTTX   0x40	/* abort transmission (HDLC mode) */
-#define STC_APPDCMP   0x20	/* append complete (async DMA mode) */
-#define STC_SNDSPC    0x08	/* send special characters (async mode) */
-#define STC_SSPC_MASK 0x07	/* special character select */
-#define STC_SSPC_1    0x01	/* send special character #1 */
-#define STC_SSPC_2    0x02	/* send special character #2 */
-#define STC_SSPC_3    0x03	/* send special character #3 */
-#define STC_SSPC_4    0x04	/* send special character #4 */
-
-/*
- * Channel status register (CSR) bits, asynchronous mode.
- */
-#define CSRA_RXEN    0x80       /* receiver enable */
-#define CSRA_RXFLOFF 0x40       /* receiver flow off */
-#define CSRA_RXFLON  0x20       /* receiver flow on */
-#define CSRA_TXEN    0x08       /* transmitter enable */
-#define CSRA_TXFLOFF 0x04       /* transmitter flow off */
-#define CSRA_TXFLON  0x02       /* transmitter flow on */
-#define CSRA_BITS "\20\2txflon\3txfloff\4txen\6rxflon\7rxfloff\10rxen"
-
-/*
- * Hacks to avoid inb() and outb()'s checks that the port type is not
- * pessimal.
- */
-
-static __inline u_char
-xinb(u_int port)
-{
-	return (inb(port));
-}
-
-#undef inb
-#define	inb(port)		xinb(port)
-
-static __inline void
-xoutb(u_int port, u_char data)
-{
-	outb(port, data);
-}
-
-#undef outb
-#define	outb(port, data)	xoutb((port), (data))
diff --git a/sys/i386/isa/if_cx.c b/sys/i386/isa/if_cx.c
deleted file mode 100644
index 1fe8b2f..0000000
--- a/sys/i386/isa/if_cx.c
+++ /dev/null
@@ -1,831 +0,0 @@
-/*
- * Cronyx-Sigma adapter driver for FreeBSD.
- * Supports PPP/HDLC and Cisco/HDLC protocol in synchronous mode,
- * and asyncronous channels with full modem control.
- * Keepalive protocol implemented in both Cisco and PPP modes.
- *
- * Copyright (C) 1994 Cronyx Ltd.
- * Author: Serge Vakulenko, <vak@zebub.msk.su>
- *
- * This software is distributed with NO WARRANTIES, not even the implied
- * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Authors grant any other persons or organisations permission to use
- * or modify this software as long as this message is kept with the software,
- * all derivative works or modified versions.
- *
- * Version 1.9, Wed Oct  4 18:58:15 MSK 1995
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#undef DEBUG
-
-#include "cx.h"
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/malloc.h>
-#include <sys/mbuf.h>
-#include <sys/sockio.h>
-#include <sys/socket.h>
-#include <sys/conf.h>
-#include <sys/bus.h>
-
-#include <net/if.h>
-
-#include <net/bpf.h>
-
-#include <i386/isa/isa_device.h>
-
-#ifndef COMPAT_OLDISA
-#error "The cx device requires the old isa compatibility shims"
-#endif
-
-#define watchdog_func_t void(*)(struct ifnet *)
-#define start_func_t    void(*)(struct ifnet*)
-
-#include <net/if_sppp.h>
-#include <machine/cronyx.h>
-#include <i386/isa/cxreg.h>
-
-/* XXX exported. */
-void cxswitch (cx_chan_t *c, cx_soft_opt_t new);
-
-static int cxprobe(struct isa_device *id);
-static int cxattach(struct isa_device *id);
-static void cxput(cx_chan_t *c, char b);
-static void cxsend(cx_chan_t *c);
-static void cxrinth(cx_chan_t *c);
-static ointhand2_t cxintr;
-static int cxtinth(cx_chan_t *c);
-
-#ifdef DEBUG
-#   define print(s)     printf s
-#else
-#   define print(s)     {/*void*/}
-#endif
-
-#define TXTIMEOUT       10              /* transmit timeout in seconds */
-#define DMABUFSZ        (6*256)         /* buffer size */
-#define PPP_HEADER_LEN  4               /* size of PPP header */
-
-/*
- * Under BSDI it's possible to use general p2p protocol scheme,
- * as well as our own one.  Switching is done via IFF_ALTPHYS flag.
- * Our ifnet pointer holds the buffer large enough to contain
- * any of sppp and p2p structures.
- */
-#define IFSTRUCTSZ   (sizeof (struct sppp))
-#define IFNETSZ         (sizeof (struct ifnet))
-
-static int cxsioctl (struct ifnet *ifp, u_long cmd, caddr_t data);
-static void cxstart (struct ifnet *ifp);
-static void cxwatchdog (struct ifnet *ifp);
-static void cxinput (cx_chan_t *c, void *buf, unsigned len);
-extern int cxrinta (cx_chan_t *c);
-extern void cxtinta (cx_chan_t *c);
-extern void cxmint (cx_chan_t *c);
-extern timeout_t cxtimeout;
-static void cxdown (cx_chan_t *c);
-static void cxup (cx_chan_t *c);
-
-cx_board_t cxboard [NCX];           /* adapter state structures */
-cx_chan_t *cxchan [NCX*NCHAN];      /* unit to channel struct pointer */
-
-extern struct cdevsw cx_cdevsw;
-
-static unsigned short irq_valid_values [] = { 3, 5, 7, 10, 11, 12, 15, 0 };
-static unsigned short drq_valid_values [] = { 5, 6, 7, 0 };
-static unsigned short port_valid_values [] = {
-	0x240, 0x260, 0x280, 0x300, 0x320, 0x380, 0x3a0, 0,
-};
-
-/*
- * Check that the value is contained in the list of correct values.
- */
-static int valid (unsigned short value, unsigned short *list)
-{
-	while (*list)
-		if (value == *list++)
-			return (1);
-	return (0);
-}
-
-/*
- * Print the mbuf chain, for debug purposes only.
- */
-static void printmbuf (struct mbuf *m)
-{
-	printf ("mbuf:");
-	for (; m; m=m->m_next) {
-		if (m->m_flags & M_PKTHDR)
-			printf (" HDR %d:", m->m_pkthdr.len);
-		if (m->m_flags & M_EXT)
-			printf (" EXT:");
-		printf (" %d", m->m_len);
-	}
-	printf ("\n");
-}
-
-/*
- * Make an mbuf from data.
- */
-static struct mbuf *makembuf (void *buf, unsigned len)
-{
-	struct mbuf *m, *o, *p;
-
-	MGETHDR (m, M_DONTWAIT, MT_DATA);
-	if (! m)
-		return (0);
-	if (len >= MINCLSIZE)
-		MCLGET (m, M_DONTWAIT);
-	m->m_pkthdr.len = len;
-	m->m_len = 0;
-
-	p = m;
-	while (len) {
-		unsigned n = M_TRAILINGSPACE (p);
-		if (n > len)
-			n = len;
-
-		if (! n) {
-			/* Allocate new mbuf. */
-			o = p;
-			MGET (p, M_DONTWAIT, MT_DATA);
-			if (! p) {
-				m_freem (m);
-				return (0);
-			}
-			if (len >= MINCLSIZE)
-				MCLGET (p, M_DONTWAIT);
-			p->m_len = 0;
-			o->m_next = p;
-
-			n = M_TRAILINGSPACE (p);
-			if (n > len)
-				n = len;
-		}
-
-		bcopy (buf, mtod (p, caddr_t) + p->m_len, n);
-
-		p->m_len += n;
-		buf = (char *)buf + n;
-		len -= n;
-	}
-	return (m);
-}
-
-/*
- * Test the presence of the adapter on the given i/o port.
- */
-static int
-cxprobe (struct isa_device *id)
-{
-	int unit = id->id_unit;
-	int iobase = id->id_iobase;
-	int irq = id->id_irq;
-	int drq = id->id_drq;
-	int irqnum;
-	irqnum = ffs (irq) - 1;
-
-	print (("cx%d: probe iobase=0x%x irq=%d drq=%d\n",
-		unit, iobase, irqnum, drq));
-	if (! valid (irqnum, irq_valid_values)) {
-		printf ("cx%d: Incorrect IRQ: %d\n", unit, irqnum);
-		return (0);
-	}
-	if (! valid (iobase, port_valid_values)) {
-		printf ("cx%d: Incorrect port address: 0x%x\n", unit, iobase);
-		return (0);
-	}
-	if (! valid (drq, drq_valid_values)) {
-		printf ("cx%d: Incorrect DMA channel: %d\n", unit, drq);
-		return (0);
-	}
-	if (! cx_probe_board (iobase))
-		return (0);
-
-	return (1);
-}
-
-/*
- * The adapter is present, initialize the driver structures.
- */
-
-static int
-cxattach (struct isa_device *id)
-{
-	int unit = id->id_unit;
-	int iobase = id->id_iobase;
-	int irq = id->id_irq;
-	int drq = id->id_drq;
-	cx_board_t *b = cxboard + unit;
-	int i;
-	struct sppp *sp;
-
-	id->id_ointr = cxintr;
-
-	/* Initialize the board structure. */
-	cx_init (b, unit, iobase, ffs(irq)-1, drq);
-
-	for (i=0; i<NCHAN; ++i) {
-		cx_chan_t *c = b->chan + i;
-		int u = b->num*NCHAN + i;
-		cxchan[u] = c;
-
-		if (c->type == T_NONE)
-			continue;
-
-		/* Allocate the buffer memory. */
-		c->arbuf = malloc (DMABUFSZ, M_DEVBUF, M_NOWAIT);
-		c->brbuf = malloc (DMABUFSZ, M_DEVBUF, M_NOWAIT);
-		c->atbuf = malloc (DMABUFSZ, M_DEVBUF, M_NOWAIT);
-		c->btbuf = malloc (DMABUFSZ, M_DEVBUF, M_NOWAIT);
-
-		/* All buffers should be located in lower 16M of memory! */
-		if (!c->arbuf || !c->brbuf || !c->atbuf || !c->btbuf) {
-			printf ("cx%d.%d: No memory for channel buffers\n",
-				c->board->num, c->num);
-			c->type = T_NONE;
-		}
-
-		switch (c->type) {
-		case T_SYNC_RS232:
-		case T_SYNC_V35:
-		case T_SYNC_RS449:
-		case T_UNIV_RS232:
-		case T_UNIV_RS449:
-		case T_UNIV_V35:
-			c->ifp = malloc (IFSTRUCTSZ, M_DEVBUF, M_NOWAIT);
-			if (! c->ifp) {
-				printf ("cx%d.%d: No memory for ifnet buffer\n",
-					c->board->num, c->num);
-				c->type = T_NONE;
-				continue;
-			}
-			bzero (c->ifp, IFSTRUCTSZ);
-			c->master = c->ifp;
-			c->ifp->if_softc = c;
-			if_initname(c->ifp, "cx", u);
-			c->ifp->if_mtu = PP_MTU;
-			c->ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST;
-			c->ifp->if_ioctl = cxsioctl;
-			c->ifp->if_start = (start_func_t) cxstart;
-			c->ifp->if_watchdog = (watchdog_func_t) cxwatchdog;
-			/* Init routine is never called by upper level? */
-			sppp_attach (c->ifp);
-			if_attach (c->ifp);
-			sp = (struct sppp*) c->ifp;
-			/* If BPF is in the kernel, call the attach for it. */
-			bpfattach (c->ifp, DLT_PPP, PPP_HEADER_LEN);
-		}
-	}
-
-	/* Reset the adapter. */
-	cx_setup_board (b);
-
-	/* Activate the timeout routine. */
-	if (unit == 0)
-		timeout (cxtimeout, 0, hz*5);
-
-	printf ("cx%d: <Cronyx-%s>\n", unit, b->name);
-	make_dev(&cx_cdevsw, unit, UID_ROOT, GID_WHEEL, 0600, "cx%d", unit);
-	return (1);
-}
-
-struct isa_driver cxdriver = {
-	INTR_TYPE_NET,
-	cxprobe,
-	cxattach,
-	"cx"
-};
-COMPAT_ISA_DRIVER(cx, cxdriver);
-
-/*
- * Process an ioctl request.
- */
-static int
-cxsioctl (struct ifnet *ifp, u_long cmd, caddr_t data)
-{
-	cx_chan_t *q, *c = ifp->if_softc;
-	int error, s, was_up, should_be_up;
-
-	/*
-	 * No socket ioctls while the channel is in async mode.
-	 */
-	if (c->type==T_NONE || c->mode==M_ASYNC)
-		return (EINVAL);
-
-	/*
-	 * Socket ioctls on slave subchannels are not allowed.
-	 */
-	if (c->master != c->ifp)
-		return (EBUSY);
-
-	was_up = (ifp->if_flags & IFF_RUNNING) != 0;
-	error = sppp_ioctl (ifp, cmd, data);
-	if (error)
-		return (error);
-
-	print (("cxioctl (%d.%d, ", c->board->num, c->num));
-	switch (cmd) {
-	default:
-		print (("0x%x)\n", cmd));
-		return (0);
-	case SIOCADDMULTI:
-		print (("SIOCADDMULTI)\n"));
-		return (0);
-	case SIOCDELMULTI:
-		print (("SIOCDELMULTI)\n"));
-		return (0);
-	case SIOCSIFFLAGS:
-		print (("SIOCSIFFLAGS)\n"));
-		break;
-	case SIOCSIFADDR:
-		print (("SIOCSIFADDR)\n"));
-		break;
-	}
-
-	/* We get here only in case of SIFFLAGS or SIFADDR. */
-	s = splimp ();
-	should_be_up = (ifp->if_flags & IFF_RUNNING) != 0;
-	if (!was_up && should_be_up) {
-		/* Interface goes up -- start it. */
-		cxup (c);
-
-		/* Start all slave subchannels. */
-		for (q=c->slaveq; q; q=q->slaveq)
-			cxup (q);
-
-		cxstart (c->ifp);
-	} else if (was_up && !should_be_up) {
-		/* Interface is going down -- stop it. */
-		cxdown (c);
-
-		/* Stop all slave subchannels. */
-		for (q=c->slaveq; q; q=q->slaveq)
-			cxdown (q);
-
-		/* Flush the interface output queue */
-		if (! c->sopt.ext)
-			sppp_flush (c->ifp);
-	}
-	splx (s);
-	return (0);
-}
-
-/*
- * Stop the interface.  Called on splimp().
- */
-static void
-cxdown (cx_chan_t *c)
-{
-	unsigned short port = c->chip->port;
-
-	print (("cx%d.%d: cxdown\n", c->board->num, c->num));
-
-	/* The interface is down, stop it */
-	c->ifp->if_flags &= ~IFF_OACTIVE;
-
-	/* Reset the channel (for sync modes only) */
-		outb (CAR(port), c->num & 3);
-		outb (STCR(port), STC_ABORTTX | STC_SNDSPC);
-
-	cx_setup_chan (c);
-}
-
-/*
- * Start the interface.  Called on splimp().
- */
-static void
-cxup (cx_chan_t *c)
-{
-	unsigned short port = c->chip->port;
-
-		/* The interface is up, start it */
-	        print (("cx%d.%d: cxup\n", c->board->num, c->num));
-
-		/* Initialize channel, enable receiver and transmitter */
-		cx_cmd (port, CCR_INITCH | CCR_ENRX | CCR_ENTX);
-		/* Repeat the command, to avoid the rev.H bug */
-		cx_cmd (port, CCR_INITCH | CCR_ENRX | CCR_ENTX);
-
-		/* Start receiver */
-		outw (ARBCNT(port), DMABUFSZ);
-		outb (ARBSTS(port), BSTS_OWN24);
-		outw (BRBCNT(port), DMABUFSZ);
-		outb (BRBSTS(port), BSTS_OWN24);
-
-		/* Raise DTR and RTS */
-		cx_chan_dtr (c, 1);
-		cx_chan_rts (c, 1);
-
-		/* Enable interrupts */
-		outb (IER(port), IER_RXD | IER_TXD);
-}
-
-/*
- * Fill transmitter buffer with data.
- */
-static void 
-cxput (cx_chan_t *c, char b)
-{
-	struct mbuf *m;
-	unsigned char *buf;
-	unsigned short port = c->chip->port, len, cnt_port, sts_port;
-
-	/* Choose the buffer. */
-	if (b == 'A') {
-		buf      = c->atbuf;
-		cnt_port = ATBCNT(port);
-		sts_port = ATBSTS(port);
-	} else {
-		buf      = c->btbuf;
-		cnt_port = BTBCNT(port);
-		sts_port = BTBSTS(port);
-	}
-
-	/* Is it busy? */
-	if (inb (sts_port) & BSTS_OWN24) {
-		if (c->ifp->if_flags & IFF_DEBUG)
-			print (("cx%d.%d: tbuf %c already busy, bsts=%b\n",
-				c->board->num, c->num, b,
-				inb (sts_port), BSTS_BITS));
-		goto ret;
-	}
-
-	/* Get the packet to send. */
-	m = sppp_dequeue (c->master);
-	if (! m)
-		return;
-	len = m->m_pkthdr.len;
-
-	/* Count the transmitted bytes to the subchannel, not the master. */
-	c->master->if_obytes -= len + 3;
-	c->ifp->if_obytes += len + 3;
-	c->stat->obytes += len + 3;
-
-	if (len >= DMABUFSZ) {
-		printf ("cx%d.%d: too long packet: %d bytes: ",
-			c->board->num, c->num, len);
-		printmbuf (m);
-		m_freem (m);
-		return;
-	}
-	m_copydata (m, 0, len, buf);
-	BPF_MTAP (c->ifp, m);
-	m_freem (m);
-
-	/* Start transmitter. */
-	outw (cnt_port, len);
-	outb (sts_port, BSTS_EOFR | BSTS_INTR | BSTS_OWN24);
-
-	if (c->ifp->if_flags & IFF_DEBUG)
-		print (("cx%d.%d: enqueue %d bytes to %c\n",
-			c->board->num, c->num, len, buf==c->atbuf ? 'A' : 'B'));
-ret:
-	c->ifp->if_flags |= IFF_OACTIVE;
-}
-
-/*
- * Start output on the (slave) interface.  Get another datagram to send
- * off of the interface queue, and copy it to the interface
- * before starting the output.
- */
-static void
-cxsend (cx_chan_t *c)
-{
-	unsigned short port = c->chip->port;
-
-	if (c->ifp->if_flags & IFF_DEBUG)
-		print (("cx%d.%d: cxsend\n", c->board->num, c->num));
-
-	/* No output if the interface is down. */
-	if (! (c->ifp->if_flags & IFF_RUNNING))
-		return;
-
-	/* Set the current channel number. */
-	outb (CAR(port), c->num & 3);
-
-	/* Determine the buffer order. */
-	if (inb (DMABSTS(port)) & DMABSTS_NTBUF) {
-		cxput (c, 'B');
-		cxput (c, 'A');
-	} else {
-		cxput (c, 'A');
-		cxput (c, 'B');
-	}
-
-	/* Set up transmit timeout. */
-	if (c->master->if_flags & IFF_OACTIVE)
-		c->master->if_timer = TXTIMEOUT;
-
-	/*
-	 * Enable TXMPTY interrupt,
-	 * to catch the case when the second buffer is empty.
-	 */
-	if ((inb (ATBSTS(port)) & BSTS_OWN24) &&
-	    (inb (BTBSTS(port)) & BSTS_OWN24)) {
-		outb (IER(port), IER_RXD | IER_TXD | IER_TXMPTY);
-	} else
-		outb (IER(port), IER_RXD | IER_TXD);
-}
-
-/*
- * Start output on the (master) interface and all slave interfaces.
- * Always called on splimp().
- */
-static void
-cxstart (struct ifnet *ifp)
-{
-	cx_chan_t *q, *c = ifp->if_softc;
-
-	if (c->ifp->if_flags & IFF_DEBUG)
-		print (("cx%d.%d: cxstart\n", c->board->num, c->num));
-
-	/* Start the master subchannel. */
-	cxsend (c);
-
-	/* Start all slave subchannels. */
-	if (c->slaveq && ! sppp_isempty (c->master))
-		for (q=c->slaveq; q; q=q->slaveq)
-			if ((q->ifp->if_flags & IFF_RUNNING) &&
-			    ! (q->ifp->if_flags & IFF_OACTIVE))
-				cxsend (q);
-}
-
-/*
- * Handle transmit timeouts.
- * Recover after lost transmit interrupts.
- * Always called on splimp().
- */
-static void
-cxwatchdog (struct ifnet *ifp)
-{
-	cx_chan_t *q, *c = ifp->if_softc;
-
-	if (! (ifp->if_flags & IFF_RUNNING))
-		return;
-	if (ifp->if_flags & IFF_DEBUG)
-		printf ("cx%d.%d: device timeout\n", c->board->num, c->num);
-
-	cxdown (c);
-	for (q=c->slaveq; q; q=q->slaveq)
-		cxdown (q);
-
-	cxup (c);
-	for (q=c->slaveq; q; q=q->slaveq)
-		cxup (q);
-
-	cxstart (ifp);
-}
-
-/*
- * Handle receive interrupts, including receive errors and
- * receive timeout interrupt.
- */
-static void 
-cxrinth (cx_chan_t *c)
-{
-	unsigned short port = c->chip->port;
-	unsigned short len, risr = inw (RISR(port));
-
-	/* Receive errors. */
-	if (risr & (RIS_BUSERR | RIS_OVERRUN | RISH_CRCERR | RISH_RXABORT)) {
-		if (c->ifp->if_flags & IFF_DEBUG)
-			printf ("cx%d.%d: receive error, risr=%b\n",
-				c->board->num, c->num, risr, RISH_BITS);
-		++c->ifp->if_ierrors;
-		++c->stat->ierrs;
-		if (risr & RIS_OVERRUN)
-			++c->ifp->if_collisions;
-	} else if (risr & RIS_EOBUF) {
-		if (c->ifp->if_flags & IFF_DEBUG)
-			print (("cx%d.%d: hdlc receive interrupt, risr=%b, arbsts=%b, brbsts=%b\n",
-				c->board->num, c->num, risr, RISH_BITS,
-				inb (ARBSTS(port)), BSTS_BITS,
-				inb (BRBSTS(port)), BSTS_BITS));
-		++c->stat->ipkts;
-
-		/* Handle received data. */
-		len = (risr & RIS_BB) ? inw(BRBCNT(port)) : inw(ARBCNT(port));
-		c->stat->ibytes += len;
-		if (len > DMABUFSZ) {
-			/* Fatal error: actual DMA transfer size
-			 * exceeds our buffer size.  It could be caused
-			 * by incorrectly programmed DMA register or
-			 * hardware fault.  Possibly, should panic here. */
-			printf ("cx%d.%d: panic! DMA buffer overflow: %d bytes\n",
-			       c->board->num, c->num, len);
-			++c->ifp->if_ierrors;
-		} else if (! (risr & RIS_EOFR)) {
-			/* The received frame does not fit in the DMA buffer.
-			 * It could be caused by serial lie noise,
-			 * or if the peer has too big MTU. */
-			if (c->ifp->if_flags & IFF_DEBUG)
-				printf ("cx%d.%d: received frame length exceeds MTU, risr=%b\n",
-					c->board->num, c->num, risr, RISH_BITS);
-			++c->ifp->if_ierrors;
-		} else {
-			/* Valid frame received. */
-			if (c->ifp->if_flags & IFF_DEBUG)
-				print (("cx%d.%d: hdlc received %d bytes\n",
-				c->board->num, c->num, len));
-			cxinput (c, (risr & RIS_BB) ? c->brbuf : c->arbuf, len);
-			++c->ifp->if_ipackets;
-		}
-	} else if (c->ifp->if_flags & IFF_DEBUG) {
-		print (("cx%d.%d: unknown hdlc receive interrupt, risr=%b\n",
-			c->board->num, c->num, risr, RISH_BITS));
-		++c->stat->ierrs;
-	}
-
-	/* Restart receiver. */
-	if (! (inb (ARBSTS(port)) & BSTS_OWN24)) {
-		outw (ARBCNT(port), DMABUFSZ);
-		outb (ARBSTS(port), BSTS_OWN24);
-	}
-	if (! (inb (BRBSTS(port)) & BSTS_OWN24)) {
-		outw (BRBCNT(port), DMABUFSZ);
-		outb (BRBSTS(port), BSTS_OWN24);
-	}
-}
-
-/*
- * Handle transmit interrupt.
- */
-static int
-cxtinth (cx_chan_t *c)
-{
-	unsigned short port = c->chip->port;
-	unsigned char tisr = inb (TISR(port));
-	unsigned char teoir = 0;
-
-	c->ifp->if_flags &= ~IFF_OACTIVE;
-	if (c->ifp == c->master)
-		c->ifp->if_timer = 0;
-
-	if (tisr & (TIS_BUSERR | TIS_UNDERRUN)) {
-		/* if (c->ifp->if_flags & IFF_DEBUG) */
-			print (("cx%d.%d: transmit error, tisr=%b, atbsts=%b, btbsts=%b\n",
-				c->board->num, c->num, tisr, TIS_BITS,
-				inb (ATBSTS(port)), BSTS_BITS,
-				inb (BTBSTS(port)), BSTS_BITS));
-		++c->ifp->if_oerrors;
-		++c->stat->oerrs;
-
-		/* Terminate the failed buffer. */
-		/* teoir = TEOI_TERMBUFF; */
-	} else if (c->ifp->if_flags & IFF_DEBUG)
-		print (("cx%d.%d: hdlc transmit interrupt, tisr=%b, atbsts=%b, btbsts=%b\n",
-			c->board->num, c->num, tisr, TIS_BITS,
-			inb (ATBSTS(port)), BSTS_BITS,
-			inb (BTBSTS(port)), BSTS_BITS));
-
-	if (tisr & TIS_EOFR) {
-		++c->ifp->if_opackets;
-		++c->stat->opkts;
-	}
-
-	/* Start output on the (sub-) channel. */
-	cxsend (c);
-
-	return (teoir);
-}
-
-static void
-cxintr (int bnum)
-{
-	cx_board_t *b = cxboard + bnum;
-	while (! (inw (BSR(b->port)) & BSR_NOINTR)) {
-		/* Acknowledge the interrupt to enter the interrupt context. */
-		/* Read the local interrupt vector register. */
-		unsigned char livr = inb (IACK(b->port, BRD_INTR_LEVEL));
-		cx_chan_t *c = b->chan + (livr>>2 & 0xf);
-		unsigned short port = c->chip->port;
-		unsigned short eoiport = REOIR(port);
-		unsigned char eoi = 0;
-
-		if (c->type == T_NONE) {
-			printf ("cx%d.%d: unexpected interrupt, livr=0x%x\n",
-				c->board->num, c->num, livr);
-			continue;       /* incorrect channel number? */
-		}
-		/* print (("cx%d.%d: interrupt, livr=0x%x\n",
-			c->board->num, c->num, livr)); */
-
-		/* Clear RTS to stop receiver data flow while we are busy
-		 * processing the interrupt, thus avoiding underruns. */
-		if (! c->sopt.norts) {
-			outb (MSVR_RTS(port), 0);
-			c->rts = 0;
-		}
-
-		switch (livr & 3) {
-		case LIV_EXCEP:         /* receive exception */
-		case LIV_RXDATA:        /* receive interrupt */
-			++c->stat->rintr;
-			switch (c->mode) {
-			case M_ASYNC: eoi = cxrinta (c); break;
-			case M_HDLC:  cxrinth (c);       break;
-			default:;       /* No bisync and X.21 yet */
-			}
-			break;
-		case LIV_TXDATA:        /* transmit interrupt */
-			++c->stat->tintr;
-			eoiport = TEOIR(port);
-			switch (c->mode) {
-			case M_ASYNC: cxtinta (c);       break;
-			case M_HDLC:  eoi = cxtinth (c); break;
-			default:;       /* No bisync and X.21 yet */
-			}
-			break;
-		case LIV_MODEM:         /* modem/timer interrupt */
-			++c->stat->mintr;
-			eoiport = MEOIR(port);
-			cxmint (c);
-			break;
-		}
-
-		/* Raise RTS for this channel if and only if
-		 * both receive buffers are empty. */
-		if (! c->sopt.norts && (inb (CSR(port)) & CSRA_RXEN) &&
-		    (inb (ARBSTS(port)) & BSTS_OWN24) &&
-		    (inb (BRBSTS(port)) & BSTS_OWN24)) {
-			outb (MSVR_RTS(port), MSV_RTS);
-			c->rts = 1;
-		}
-
-		/* Exit from interrupt context. */
-		outb (eoiport, eoi);
-
-		/* Master channel - start output on all idle subchannels. */
-		if (c->master == c->ifp && c->slaveq &&
-		    (livr & 3) == LIV_TXDATA && c->mode == M_HDLC &&
-		    ! sppp_isempty (c->ifp)) {
-			cx_chan_t *q;
-
-			for (q=c->slaveq; q; q=q->slaveq)
-				if ((q->ifp->if_flags & IFF_RUNNING) &&
-				    ! (q->ifp->if_flags & IFF_OACTIVE))
-					cxsend (q);
-		}
-	}
-}
-
-/*
- * Process the received packet.
- */
-static void 
-cxinput (cx_chan_t *c, void *buf, unsigned len)
-{
-	/* Make an mbuf. */
-	struct mbuf *m = makembuf (buf, len);
-	if (! m) {
-		if (c->ifp->if_flags & IFF_DEBUG)
-			printf ("cx%d.%d: no memory for packet\n",
-				c->board->num, c->num);
-		++c->ifp->if_iqdrops;
-		return;
-	}
-	m->m_pkthdr.rcvif = c->master;
-#ifdef DEBUG
-	if (c->ifp->if_flags & IFF_DEBUG)
-	printmbuf (m);
-#endif
-
-	/*
-	 * Check if there's a BPF listener on this interface.
-	 * If so, hand off the raw packet to bpf.
-	 */
-	BPF_TAP (c->ifp, buf, len);
-
-	/* Count the received bytes to the subchannel, not the master. */
-	c->master->if_ibytes -= len + 3;
-	c->ifp->if_ibytes += len + 3;
-
-	sppp_input (c->master, m);
-}
-
-void cxswitch (cx_chan_t *c, cx_soft_opt_t new)
-{
-	new.ext = 0;
-	if (! new.ext) {
-		struct sppp *sp = (struct sppp*) c->ifp;
-
-#if 0 /* Doesn't work this way any more 990402 /phk */
-		if (new.cisco)
-			sp->pp_flags |= PP_CISCO;
-		else
-			sp->pp_flags &= ~PP_CISCO;
-#endif
-		if (new.keepalive)
-			sp->pp_flags |= PP_KEEPALIVE;
-		else
-			sp->pp_flags &= ~PP_KEEPALIVE;
-	}
-	c->sopt = new;
-}