Preliminary support for per-cpu data pages.

This eliminates a lot of #ifdef SMP type code.  Things like _curproc reside
in a data page that is unique on each cpu, eliminating the expensive macros
like:    #define curproc (SMPcurproc[cpunumber()])

There are some unresolved bootstrap and address space sharing issues at
present, but Steve is waiting on this for other work.  There is still some
strictly temporary code present that isn't exactly pretty.

This is part of a larger change that has run into some bumps, this part is
standalone so it should be safe.  The temporary code goes away when the
full idle cpu support is finished.

Reviewed by: fsmp, dyson

4 files changed, 22 insertions, 24 deletions

diff --git a/sys/i386/isa/apic_vector.s b/sys/i386/isa/apic_vector.s
index 0817521..fa7edb0 100644
--- a/sys/i386/isa/apic_vector.s
+++ b/sys/i386/isa/apic_vector.s
@@ -1,6 +1,6 @@
 /*
  *	from: vector.s, 386BSD 0.1 unknown origin
- *	$Id: apic_vector.s,v 1.1 1997/05/26 17:58:26 fsmp Exp $
+ *	$Id: apic_vector.s,v 1.2 1997/05/31 08:59:51 peter Exp $
  */
 
 
@@ -11,19 +11,19 @@
 #define REDTBL_IDX(irq_num)	(0x10 + ((irq_num) * 2))
 
 /*
- * 'lazy masking' code submitted by: Bruce Evans <bde@zeta.org.au>
+ * 'lazy masking' code suggested by Bruce Evans <bde@zeta.org.au>
  */
 #define MAYBE_MASK_IRQ(irq_num)						\
 	testl	$IRQ_BIT(irq_num),iactive ;	/* lazy masking */	\
 	je	1f ;			/* NOT currently active */	\
 	orl	$IRQ_BIT(irq_num),_imen ;	/* set the mask bit */	\
-	movl	_io_apic_base,%ecx ;		/* io apic addr */	\
+	movl	_ioapic,%ecx ;			/* ioapic[0]addr */	\
 	movl	$REDTBL_IDX(irq_num),(%ecx) ;	/* write the index */	\
 	movl	IOAPIC_WINDOW(%ecx),%eax ;	/* current value */	\
 	orl	$IOART_INTMASK,%eax ;		/* set the mask */	\
 	movl	%eax,IOAPIC_WINDOW(%ecx) ;	/* new value */		\
-	movl	_apic_base, %eax ;					\
-	movl	$0, APIC_EOI(%eax) ;					\
+	movl	$lapic_eoi, %eax ;					\
+	movl	$0, (%eax) ;						\
 	orl	$IRQ_BIT(irq_num), _ipending ;				\
 	REL_MPLOCK ;			/* SMP release global lock */	\
 	popl	%es ;							\
@@ -43,7 +43,7 @@
 	testl	$IRQ_BIT(irq_num),_imen ;				\
 	je	2f ;							\
 	andl	$~IRQ_BIT(irq_num),_imen ;	/* clear mask bit */	\
-	movl	_io_apic_base,%ecx ;		/* io apic addr */	\
+	movl	_ioapic,%ecx ;			/* ioapic[0]addr */	\
 	movl	$REDTBL_IDX(irq_num),(%ecx) ;	/* write the index */	\
 	movl	IOAPIC_WINDOW(%ecx),%eax ;	/* current value */	\
 	andl	$~IOART_INTMASK,%eax ;		/* clear the mask */	\
@@ -72,8 +72,8 @@ IDTVEC(vec_name) ;							\
 	GET_MPLOCK ;		/* SMP Spin lock */			\
 	pushl	_intr_unit + (irq_num) * 4 ;				\
 	call	*_intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \
-	movl	_apic_base, %eax ;					\
-	movl	$0, APIC_EOI(%eax) ;					\
+	movl	$lapic_eoi, %eax ;					\
+	movl	$0, (%eax) ;						\
 	addl	$4,%esp ;						\
 	incl	_cnt+V_INTR ;	/* book-keeping can wait */		\
 	movl	_intr_countp + (irq_num) * 4,%eax ;			\
@@ -132,8 +132,8 @@ IDTVEC(vec_name) ;							\
 	movl	%ax,%es ;						\
 	GET_MPLOCK ;		/* SMP Spin lock */			\
 	MAYBE_MASK_IRQ(irq_num) ;					\
-	movl	_apic_base, %eax ;					\
-	movl	$0, APIC_EOI(%eax) ;					\
+	movl	$lapic_eoi, %eax ;					\
+	movl	$0, (%eax) ;						\
 	movl	_cpl,%eax ;						\
 	testl	$IRQ_BIT(irq_num), %eax ;				\
 	jne	3f ;							\
@@ -172,10 +172,9 @@ _Xinvltlb:
 	pushl	%eax
 	movl	%cr3, %eax		/* invalidate the TLB */
 	movl	%eax, %cr3
+	movl	$lapic_eoi, %eax
 	ss				/* stack segment, avoid %ds load */
-	movl	_apic_base, %eax
-	ss
-	movl	$0, APIC_EOI(%eax)	/* End Of Interrupt to APIC */
+	movl	$0, (%eax)		/* End Of Interrupt to APIC */
 	popl	%eax
 	iret
 
diff --git a/sys/i386/isa/intr_machdep.c b/sys/i386/isa/intr_machdep.c
index 81557c3..d1caa64 100644
--- a/sys/i386/isa/intr_machdep.c
+++ b/sys/i386/isa/intr_machdep.c
@@ -34,7 +34,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)isa.c	7.2 (Berkeley) 5/13/91
- *	$Id: intr_machdep.c,v 1.1 1997/06/02 08:19:04 dfr Exp $
+ *	$Id: intr_machdep.c,v 1.2 1997/06/02 15:28:10 kato Exp $
  */
 
 #include "opt_auto_eoi.h"
@@ -268,7 +268,7 @@ isa_irq_pending(dvp)
 	struct isa_device *dvp;
 {
 	/* read APIC IRR containing the 16 ISA INTerrupts */
-	return ((lapic__irr1 & 0x00ffffff)
+	return ((lapic.irr1 & 0x00ffffff)
 		& (u_int32_t)dvp->id_irq) ? 1 : 0;
 }
 
diff --git a/sys/i386/isa/nmi.c b/sys/i386/isa/nmi.c
index 81557c3..d1caa64 100644
--- a/sys/i386/isa/nmi.c
+++ b/sys/i386/isa/nmi.c
@@ -34,7 +34,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)isa.c	7.2 (Berkeley) 5/13/91
- *	$Id: intr_machdep.c,v 1.1 1997/06/02 08:19:04 dfr Exp $
+ *	$Id: intr_machdep.c,v 1.2 1997/06/02 15:28:10 kato Exp $
  */
 
 #include "opt_auto_eoi.h"
@@ -268,7 +268,7 @@ isa_irq_pending(dvp)
 	struct isa_device *dvp;
 {
 	/* read APIC IRR containing the 16 ISA INTerrupts */
-	return ((lapic__irr1 & 0x00ffffff)
+	return ((lapic.irr1 & 0x00ffffff)
 		& (u_int32_t)dvp->id_irq) ? 1 : 0;
 }
 
diff --git a/sys/i386/isa/npx.c b/sys/i386/isa/npx.c
index aca74fa..14487c95 100644
--- a/sys/i386/isa/npx.c
+++ b/sys/i386/isa/npx.c
@@ -32,7 +32,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)npx.c	7.2 (Berkeley) 5/12/91
- *	$Id: npx.c,v 1.44 1997/05/31 09:27:31 peter Exp $
+ *	$Id: npx.c,v 1.45 1997/06/02 08:19:05 dfr Exp $
  */
 
 #include "npx.h"
@@ -63,6 +63,7 @@
 #include <machine/clock.h>
 #include <machine/specialreg.h>
 #if defined(APIC_IO)
+#include <machine/smp.h>
 #include <machine/apic.h>
 #include <machine/mpapic.h>
 #endif /* APIC_IO */
@@ -140,10 +141,8 @@ SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
 	"Floatingpoint instructions executed in hardware");
 
 static u_int	npx0_imask = SWI_CLOCK_MASK;
-#ifdef SMP
-#define npxproc	(SMPnpxproc[cpunumber()])
-struct proc	*SMPnpxproc[NCPU];
-#else
+
+#ifndef SMP	/* XXX per-cpu on smp */
 struct proc	*npxproc;
 #endif
 
@@ -172,8 +171,8 @@ asm
 	ss
 	incl	" __XSTRING(CNAME(npx_intrs_while_probing)) "
 	pushl	%eax
-	movl	" __XSTRING(CNAME(apic_base)) ",%eax	# EOI to local APIC
-	movl	$0,0xb0(,%eax,1)	# movl $0, APIC_EOI(%eax)
+	movl	$lapic_eoi,%eax		# EOI to local APIC
+	movl	$0,(%eax)		# movl $0, APIC_EOI(%eax)
 	movb	$0,%al
 	outb	%al,$0xf0		# clear BUSY# latch
 	popl	%eax