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author | dg <dg@FreeBSD.org> | 1994-08-12 06:51:12 +0000 |
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committer | dg <dg@FreeBSD.org> | 1994-08-12 06:51:12 +0000 |
commit | cc490038a0f6ece1aa559fbd7f0f2ff39eecbf5a (patch) | |
tree | c656aff1523b520b6a5e7f3897ad11ef631a40bc /sys/i386/isa/ic | |
parent | 0bf5c587d2b0703e87888f837c671426497a4ca1 (diff) | |
download | FreeBSD-src-cc490038a0f6ece1aa559fbd7f0f2ff39eecbf5a.zip FreeBSD-src-cc490038a0f6ece1aa559fbd7f0f2ff39eecbf5a.tar.gz |
New ethernet device driver from Matt Thomas:
This driver supports all the DEC EtherWORKS III NICs (DE203, DE204,
and DE205) and the later DEC EtherWORKS II NICs (DE200, DE201, DE202,
DE422). DEPCA-style boards prior to the DE200 have not been tested
and may not work.
Submitted by: Matt Thomas (thomas@lkg.dec.com)
Diffstat (limited to 'sys/i386/isa/ic')
-rw-r--r-- | sys/i386/isa/ic/am7990.h | 109 | ||||
-rw-r--r-- | sys/i386/isa/ic/lemac.h | 177 |
2 files changed, 286 insertions, 0 deletions
diff --git a/sys/i386/isa/ic/am7990.h b/sys/i386/isa/ic/am7990.h new file mode 100644 index 0000000..ea8a0e6 --- /dev/null +++ b/sys/i386/isa/ic/am7990.h @@ -0,0 +1,109 @@ +/* + * AMD 7990 (LANCE) definitions + * + * + */ + +#if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN +#define LN_BITFIELD2(a, b) b, a +#define LN_BITFIELD3(a, b, c) c, b, a +#define LN_BITFIELD4(a, b, c, d) d, c, b, a +#else +#define LN_BITFIELD2(a, b) a, b +#define LN_BITFIELD3(a, b, c) a, b, c +#define LN_BITFIELD4(a, b, c, d) a, b, c, d +#endif + +#define LN_ADDR_LO(addr) ((addr) & 0xFFFF) +#define LN_ADDR_HI(addr) (((addr) >> 16) & 0xFF) + +typedef struct { + unsigned short r_addr_lo; + unsigned short LN_BITFIELD3(r_addr_hi : 8, + : 5, + r_log2_size : 3); +} ln_ring_t; + +#define LN_MC_MASK 0x3F /* Only 6 bits of the CRC */ + +typedef struct { + unsigned short ln_mode; +#define LN_MODE_RXD 0x0001 /* ( W) Receiver Disabled */ +#define LN_MODE_TXD 0x0002 /* ( W) Transmitter Disabled */ +#define LN_MODE_LOOP 0x0004 /* ( W) Enable Loopback */ +#define LN_MODE_NOTXCRC 0x0008 /* ( W) Don't Calculate TX CRCs */ +#define LN_MODE_FRCCOLL 0x0010 /* ( W) Force Collision */ +#define LN_MODE_NORETRY 0x0020 /* ( W) No Transmit Retries */ +#define LN_MODE_INTLOOP 0x0040 /* ( W) Internal Loopback */ +#define LN_MODE_PROMISC 0x8000 /* ( W) Promiscious Mode */ + unsigned short ln_physaddr[3]; + unsigned short ln_multi_mask[4]; + ln_ring_t ln_rxring; + ln_ring_t ln_txring; +} ln_initb_t; + +typedef struct { + unsigned short d_addr_lo; + unsigned char d_addr_hi; + unsigned char d_flag; +#define LN_DFLAG_EOP 0x0001 /* (RW) End Of Packet */ +#define LN_DFLAG_SOP 0x0002 /* (RW) Start Of Packet */ +#define LN_DFLAG_RxBUFERROR 0x0004 /* (R ) Receive - Buffer Error */ +#define LN_DFLAG_TxDEFERRED 0x0004 /* (R ) Transmit - Initially Deferred */ +#define LN_DFLAG_RxBADCRC 0x0008 /* (R ) Receive - Bad Checksum */ +#define LN_DFLAG_TxONECOLL 0x0008 /* (R ) Transmit - Single Collision */ +#define LN_DFLAG_RxOVERFLOW 0x0010 /* (R ) Receive - Overflow Error */ +#define LN_DFLAG_TxMULTCOLL 0x0010 /* (R ) Transmit - Multiple Collisions */ +#define LN_DFLAG_RxFRAMING 0x0020 /* (R ) Receive - Framing Error */ +#define LN_DFLAG_RxERRSUM 0x0040 /* (R ) Receive - Error Summary */ +#define LN_DFLAG_TxERRSUM 0x0040 /* (R ) Transmit - Error Summary */ +#define LN_DFLAG_OWNER 0x0080 /* (RW) Owner (1=Am7990, 0=host) */ + signed short d_buflen; /* ( W) Two's complement */ + unsigned short d_status; +#define LN_DSTS_RxLENMASK 0x0FFF /* (R ) Recieve Length */ +#define LN_DSTS_TxTDRMASK 0x03FF /* (R ) Transmit - Time Domain Reflectometer */ +#define LN_DSTS_TxEXCCOLL 0x0400 /* (R ) Transmit - Excessive Collisions */ +#define LN_DSTS_TxCARRLOSS 0x0800 /* (R ) Transmit - Carrier Loss */ +#define LN_DSTS_TxLATECOLL 0x1000 /* (R ) Transmit - Late Collision */ +#define LN_DSTS_TxUNDERFLOW 0x4000 /* (R ) Transmit - Underflow */ +#define LN_DSTS_TxBUFERROR 0x8000 /* (R ) Transmit - Buffer Error */ +} ln_desc_t; + + + + +#define LN_CSR0 0x0000 + +#define LN_CSR0_INIT 0x0001 /* (RS) Initialize Am 7990 */ +#define LN_CSR0_START 0x0002 /* (RS) Start Am7990 */ +#define LN_CSR0_STOP 0x0004 /* (RS) Reset Am7990 */ +#define LN_CSR0_TXDEMAND 0x0008 /* (RS) Transmit On Demand */ +#define LN_CSR0_TXON 0x0010 /* (R ) Transmitter Enabled */ +#define LN_CSR0_RXON 0x0020 /* (R ) Receiver Enabled */ +#define LN_CSR0_ENABINTR 0x0040 /* (RW) Interrupt Enabled */ +#define LN_CSR0_PENDINTR 0x0080 /* (R ) Interrupt Pending */ +#define LN_CSR0_INITDONE 0x0100 /* (RC) Initialization Done */ +#define LN_CSR0_TXINT 0x0200 /* (RC) Transmit Interrupt */ +#define LN_CSR0_RXINT 0x0400 /* (RC) Receive Interrupt */ +#define LN_CSR0_MEMERROR 0x0800 /* (RC) Memory Error */ +#define LN_CSR0_MISS 0x1000 /* (RC) No Available Receive Buffers */ +#define LN_CSR0_CERR 0x2000 /* (RC) SQE failed */ +#define LN_CSR0_BABL 0x4000 /* (RC) Transmit Babble */ +#define LN_CSR0_ERRSUM 0x8000 /* (R ) Error Summary (last 4) */ +#define LN_CSR0_CLEAR 0x7F00 /* Clear Status Bit */ + +/* + * CSR1 -- Init Block Address (Low 16 Bits -- Must be Word Aligned) + * CSR2 -- Init Block Address (High 8 Bits) + */ +#define LN_CSR1 0x0001 +#define LN_CSR2 0x0002 + +/* + * CSR3 -- Hardware Control + */ + +#define LN_CSR3 0x0003 +#define LN_CSR3_BCON 0x0001 /* (RW) BM/HOLD Control */ +#define LN_CSR3_ALE 0x0002 /* (RW) ALE Control */ +#define LN_CSR3_BSWP 0x0004 /* (RW) Byte Swap */ diff --git a/sys/i386/isa/ic/lemac.h b/sys/i386/isa/ic/lemac.h new file mode 100644 index 0000000..2c919d8 --- /dev/null +++ b/sys/i386/isa/ic/lemac.h @@ -0,0 +1,177 @@ +/* + * Copyright (c) 1994 Matt Thomas (thomas@lkg.dec.com) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software withough specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $Id: lemac.h,v 1.1 1994/08/01 16:03:42 thomas Exp $ + */ +#ifndef _LEMAC_H_ +#define _LEMAC_H_ + +/* + * This is list of registers used on a DEC EtherWORKS III card. + * Each board occupies a 32 byte register space. This can be + * in either EISA or ISA space. Currently we only support ISA + * space. + */ + +#define LEMAC_REG_CS 0x00 /* Control and Status */ +#define LEMAC_REG_CTL 0x01 /* Control */ +#define LEMAC_REG_IC 0x02 /* Interrupt Control */ +#define LEMAC_REG_TS 0x03 /* Transmit Status */ +#define LEMAC_REG_RSVD1 0x04 /* Reserved (not used) */ +#define LEMAC_REG_RSVD2 0x05 /* Reserved (not used) */ +#define LEMAC_REG_FMQ 0x06 /* Free Memory Queue */ +#define LEMAC_REG_FMC 0x07 /* Free Memory Queue Count */ +#define LEMAC_REG_RQ 0x08 /* Receive Queue */ +#define LEMAC_REG_RQC 0x09 /* Receive Queue Count */ +#define LEMAC_REG_TQ 0x0A /* Transmit Queue */ +#define LEMAC_REG_TQC 0x0B /* Transmit Queue Count */ +#define LEMAC_REG_TDQ 0x0C /* Transmit Done Queue */ +#define LEMAC_REG_TDC 0x0D /* Transmit Done Queue Count */ +#define LEMAC_REG_PI1 0x0E /* Page Index #1 */ +#define LEMAC_REG_PI2 0x0F /* Page Index #2 */ +#define LEMAC_REG_DAT 0x10 /* Data */ +#define LEMAC_REG_IOP 0x11 /* I/O Page */ +#define LEMAC_REG_IOB 0x12 /* I/O Base */ +#define LEMAC_REG_MPN 0x13 /* Memory Page */ +#define LEMAC_REG_MBR 0x14 /* Memory Base */ +#define LEMAC_REG_APD 0x15 /* Address PROM */ +#define LEMAC_REG_EE1 0x16 /* EEPROM Data #1 */ +#define LEMAC_REG_EE2 0x17 /* EEPROM Data #2 */ +#define LEMAC_REG_PA0 0x18 /* Physical Address (Byte 0) */ +#define LEMAC_REG_PA1 0x19 /* Physical Address (Byte 1) */ +#define LEMAC_REG_PA2 0x1A /* Physical Address (Byte 2) */ +#define LEMAC_REG_PA3 0x1B /* Physical Address (Byte 3) */ +#define LEMAC_REG_PA4 0x1C /* Physical Address (Byte 4) */ +#define LEMAC_REG_PA5 0x1D /* Physical Address (Byte 5) */ +#define LEMAC_REG_CNF 0x1E /* Configuration Management */ +#define LEMAC_IOSPACE 0x20 /* LEMAC uses 32 bytes of IOSPACE */ + + +#define LEMAC_REG_EID0 0x80 /* EISA Identification 0 */ +#define LEMAC_REG_EID1 0x81 /* EISA Identification 1 */ +#define LEMAC_REG_EID2 0x82 /* EISA Identification 2 */ +#define LEMAC_REG_EID3 0x83 /* EISA Identification 3 */ +#define LEMAC_REG_EIC 0x84 /* EISA Control */ + +/* Control Page (Page 0) Definitions */ + +#define LEMAC_MCTBL_BITS 9 +#define LEMAC_MCTBL_OFF 512 +#define LEMAC_MCTBL_SIZE (1 << (LEMAC_MCTBL_BITS - 3)) +#define LEMAC_CRC32_POLY 0xEDB88320UL /* CRC-32 Poly -- Little Endian) */ + +/* EEPROM Definitions */ + +#define LEMAC_EEP_CKSUM 0 /* The valid checksum is 0 */ +#define LEMAC_EEP_SIZE 32 /* EEPROM is 32 bytes */ +#define LEMAC_EEP_DELAY 2000 /* 2ms = 2000us */ +#define LEMAC_EEP_PRDNM 8 /* Product Name Offset */ +#define LEMAC_EEP_PRDNMSZ 8 /* Product Name Size */ +#define LEMAC_EEP_SWFLAGS 16 /* Software Options Offset */ +#define LEMAC_EEP_SETUP 23 /* Setup Options Offset */ + +#define LEMAC_EEP_SW_SQE 0x10 /* Enable TX_SQE on Transmits */ +#define LEMAC_EEP_SW_LAB 0x08 /* Enable TX_LAB on Transmits */ +#define LEMAC_EEP_ST_DRAM 0x02 /* Enable extra DRAM */ + +#define LEMAC_ADP_ROMSZ 32 /* Size of Address PROM */ + +/* Receive Status Definitions */ + +#define LEMAC_RX_PLL 0x01 /* Phase Lock Lost */ +#define LEMAC_RX_CRC 0x02 /* CRC Error */ +#define LEMAC_RX_DBE 0x04 /* Dribble Bit Error */ +#define LEMAC_RX_MCM 0x08 /* Multicast Match */ +#define LEMAC_RX_IAM 0x10 /* Individual Address Match */ +#define LEMAC_RX_OK 0x80 /* No Errors */ + +/* Transmit Status Definitions (not valid if TXD == 0) */ + +#define LEMAC_TS_RTRYMSK 0x0F /* Retries of last TX PDU */ +#define LEMAC_TS_ECL 0x10 /* Excessive collision of ... */ +#define LEMAC_TS_LCL 0x20 /* Late collision of ... */ +#define LEMAC_TS_ID 0x40 /* Initially Deferred ... */ + +/* Transmit Control Definitions */ + +#define LEMAC_TX_ISA 0x01 /* Insert Source Address (no) */ +#define LEMAC_TX_IFC 0x02 /* Insert Frame Check (yes) */ +#define LEMAC_TX_PAD 0x04 /* Zero PAD to mininum length (yes) */ +#define LEMAC_TX_LAB 0x08 /* Less Agressive Backoff (no) */ +#define LEMAC_TX_QMD 0x10 /* Q-Mode (yes) */ +#define LEMAC_TX_STP 0x20 /* Stop on Error (yes) */ +#define LEMAC_TX_SQE 0x40 /* SQE Enable (yes) */ + +#define LEMAC_TX_FLAGS (LEMAC_TX_IFC|LEMAC_TX_PAD|LEMAC_TX_QMD|\ + LEMAC_TX_STP|LEMAC_TX_SQE) +#define LEMAC_TX_HDRSZ 4 /* Size of TX header */ + +/* Transmit Done Queue Status Definitions */ + +#define LEMAC_TDQ_COL 0x03 /* Collision Mask */ +#define LEMAC_TDQ_NOCOL 0x00 /* No Collisions */ +#define LEMAC_TDQ_ONECOL 0x01 /* One Collision */ +#define LEMAC_TDQ_MULCOL 0x02 /* Multiple Collisions */ +#define LEMAC_TDQ_EXCCOL 0x03 /* Excesive Collisions */ +#define LEMAC_TDQ_ID 0x04 /* Initially Deferred */ +#define LEMAC_TDQ_LCL 0x08 /* Late Collision (will TX_STP) */ + +/* Control / Status Definitions */ + +#define LEMAC_CS_RXD 0x01 /* Receiver Disabled */ +#define LEMAC_CS_TXD 0x02 /* Transmitter Disabled */ +#define LEMAC_CS_RNE 0x04 /* Receive Queue Not Empty */ +#define LEMAC_CS_TNE 0x08 /* Transmit Done Queue Not Empty */ +#define LEMAC_CS_MBZ4 0x10 /* MBZ */ +#define LEMAC_CS_MCE 0x20 /* Multicast Enable */ +#define LEMAC_CS_PME 0x40 /* Promiscuous Mode Enable */ +#define LEMAC_CS_RA 0x80 /* Runt Accept */ + +/* Control Definitions */ + +#define LEMAC_CTL_LED 0x02 /* LED state (inverted) */ + +/* Interrupt Control Definitions */ + +#define LEMAC_IC_RXD 0x01 /* Enable RXD Interrupt */ +#define LEMAC_IC_TXD 0x02 /* Enable TXD Interrupt */ +#define LEMAC_IC_RNE 0x04 /* Enable RNE Interrupt */ +#define LEMAC_IC_TNE 0x08 /* Enable TNE Interrupt */ +#define LEMAC_IC_ALL 0x0F /* Enable RXD,TXD,RNE,TNE */ +#define LEMAC_IC_IRQMSK 0x60 /* Interrupt Select */ +#define LEMAC_IC_IRQ5 0x00 /* Select IRQ 5 */ +#define LEMAC_IC_IRQ10 0x20 /* Select IRQ 10 */ +#define LEMAC_IC_IRQ11 0x40 /* Select IRQ 11 */ +#define LEMAC_IC_IRQ15 0x60 /* Select IRQ 15 */ +#define LEMAC_IC_IE 0x80 /* Interrupt Enable */ + +/* I/O Page Definitions */ + +#define LEMAC_IOP_EEINIT 0xC0 /* Perform a board init/reset */ +#define LEMAC_IOP_EEREAD 0xE0 /* Start a read from EEPROM */ + +/* Configuration / Management Definitions */ + +#define LEMAC_CNF_DRAM 0x02 /* Extra on-board DRAM is available */ + +#endif /* _LEMAC_H_ */ |