diff options
author | rgrimes <rgrimes@FreeBSD.org> | 1995-05-30 08:16:23 +0000 |
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committer | rgrimes <rgrimes@FreeBSD.org> | 1995-05-30 08:16:23 +0000 |
commit | c86f0c7a71e7ade3e38b325c186a9cf374e0411e (patch) | |
tree | 176f04f674860c7cfae9ac5d2ff4d4e1d73cb2b7 /sys/i386/isa/ic | |
parent | 423ba8f9bc23d93bfc244aca9b12563b1c9de90d (diff) | |
download | FreeBSD-src-c86f0c7a71e7ade3e38b325c186a9cf374e0411e.zip FreeBSD-src-c86f0c7a71e7ade3e38b325c186a9cf374e0411e.tar.gz |
Remove trailing whitespace.
Diffstat (limited to 'sys/i386/isa/ic')
-rw-r--r-- | sys/i386/isa/ic/Am7990.h | 34 | ||||
-rw-r--r-- | sys/i386/isa/ic/am7990.h | 2 | ||||
-rw-r--r-- | sys/i386/isa/ic/i82365.h | 2 | ||||
-rw-r--r-- | sys/i386/isa/ic/i8237.h | 4 | ||||
-rw-r--r-- | sys/i386/isa/ic/lemac.h | 4 | ||||
-rw-r--r-- | sys/i386/isa/ic/ncr5380.h | 6 |
6 files changed, 26 insertions, 26 deletions
diff --git a/sys/i386/isa/ic/Am7990.h b/sys/i386/isa/ic/Am7990.h index bbc6c63..fe146ee 100644 --- a/sys/i386/isa/ic/Am7990.h +++ b/sys/i386/isa/ic/Am7990.h @@ -1,6 +1,6 @@ /* * Am7990, Local Area Network Controller for Ethernet (LANCE) - * + * * Copyright (c) 1994, Paul Richards. This software may be used, * modified, copied, distributed, and sold, in both source and binary * form provided that the above copyright and these terms are retained. @@ -35,18 +35,18 @@ #define MISS 0x1000 #define MERR 0x0800 #define RINT 0x0400 -#define TINT 0x0200 -#define IDON 0x0100 +#define TINT 0x0200 +#define IDON 0x0100 #define INTR 0x0080 #define INEA 0x0040 #define RXON 0x0020 #define TXON 0x0010 #define TDMD 0x0008 -#define STOP 0x0004 +#define STOP 0x0004 #define STRT 0x0002 -#define INIT 0x0001 +#define INIT 0x0001 -/* +/* * CSR3 * * Bits 3-15 are reserved. @@ -54,12 +54,12 @@ */ #define BSWP 0x0004 -#define ACON 0x0002 +#define ACON 0x0002 #define BCON 0x0001 /* Initialisation block */ -struct init_block { +struct init_block { u_short mode; /* Mode register */ u_char padr[6]; /* Ethernet address */ u_char ladrf[8]; /* Logical address filter (multicast) */ @@ -88,7 +88,7 @@ struct init_block { #define DTX 0x0002 /* Disable the transmitter */ #define DRX 0x0001 /* Disable the receiver */ -/* +/* * Message Descriptor Structure * * Each transmit or receive descriptor ring entry (RDRE's and TDRE's) @@ -100,14 +100,14 @@ struct init_block { * 3. The status information for that particular buffer. The eight most * significant bits of md1 are collectively termed the STATUS of the * descriptor. - * + * * Descriptor md0 contains LADR 0-15, the low order 16 bits of the 24-bit - * address of the actual data buffer. Bits 0-7 of descriptor md1 contain + * address of the actual data buffer. Bits 0-7 of descriptor md1 contain * HADR, the high order 8-bits of the 24-bit data buffer address. Bits 8-15 * of md1 contain the status flags of the buffer. Descriptor md2 contains the - * buffer byte count in bits 0-11 as a two's complement number and must have + * buffer byte count in bits 0-11 as a two's complement number and must have * 1's written to bits 12-15. For the receive entry md3 has the Message Byte - * Count in bits 0-11, this is the length of the received message and is valid + * Count in bits 0-11, this is the length of the received message and is valid * only when ERR is cleared and ENP is set. For the transmit entry it contains * more status information. * @@ -116,8 +116,8 @@ struct init_block { struct mds { u_short md0; u_short md1; - short md2; - u_short md3; + short md2; + u_short md3; }; /* Receive STATUS flags for md1 */ @@ -147,8 +147,8 @@ struct mds { #define ONE 0x0800 /* Exactly one retry was needed */ #define DEF 0x0400 /* Packet transmit deferred -- channel busy */ -/* - * Transmit status flags for md2 +/* + * Transmit status flags for md2 * * Same as for receive descriptor. * diff --git a/sys/i386/isa/ic/am7990.h b/sys/i386/isa/ic/am7990.h index ea8a0e6..ce007a1 100644 --- a/sys/i386/isa/ic/am7990.h +++ b/sys/i386/isa/ic/am7990.h @@ -62,7 +62,7 @@ typedef struct { unsigned short d_status; #define LN_DSTS_RxLENMASK 0x0FFF /* (R ) Recieve Length */ #define LN_DSTS_TxTDRMASK 0x03FF /* (R ) Transmit - Time Domain Reflectometer */ -#define LN_DSTS_TxEXCCOLL 0x0400 /* (R ) Transmit - Excessive Collisions */ +#define LN_DSTS_TxEXCCOLL 0x0400 /* (R ) Transmit - Excessive Collisions */ #define LN_DSTS_TxCARRLOSS 0x0800 /* (R ) Transmit - Carrier Loss */ #define LN_DSTS_TxLATECOLL 0x1000 /* (R ) Transmit - Late Collision */ #define LN_DSTS_TxUNDERFLOW 0x4000 /* (R ) Transmit - Underflow */ diff --git a/sys/i386/isa/ic/i82365.h b/sys/i386/isa/ic/i82365.h index ab38125..b86812e 100644 --- a/sys/i386/isa/ic/i82365.h +++ b/sys/i386/isa/ic/i82365.h @@ -16,7 +16,7 @@ * PCIC Registers * Each register is given a name, and most of the bits are named too. * I should really name them all. - * + * * Finally, since the banks can be addressed with a regular syntax, * some macros are provided for that purpose. */ diff --git a/sys/i386/isa/ic/i8237.h b/sys/i386/isa/ic/i8237.h index 722194c..5493ca8 100644 --- a/sys/i386/isa/ic/i8237.h +++ b/sys/i386/isa/ic/i8237.h @@ -1,7 +1,7 @@ /* * Intel 8237 DMA Controller * - * $Id: i8237.h,v 1.2 1993/10/16 13:48:48 rgrimes Exp $ + * $Id: i8237.h,v 1.3 1994/11/01 17:26:47 ache Exp $ */ #define DMA37MD_SINGLE 0x40 /* single pass mode */ @@ -9,4 +9,4 @@ #define DMA37MD_AUTO 0x50 /* autoinitialise single pass mode */ #define DMA37MD_WRITE 0x04 /* read the device, write memory operation */ #define DMA37MD_READ 0x08 /* write the device, read memory operation */ - + diff --git a/sys/i386/isa/ic/lemac.h b/sys/i386/isa/ic/lemac.h index 2c919d8..4eee86f 100644 --- a/sys/i386/isa/ic/lemac.h +++ b/sys/i386/isa/ic/lemac.h @@ -21,7 +21,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * $Id: lemac.h,v 1.1 1994/08/01 16:03:42 thomas Exp $ + * $Id: lemac.h,v 1.1 1994/08/12 06:51:12 davidg Exp $ */ #ifndef _LEMAC_H_ #define _LEMAC_H_ @@ -128,7 +128,7 @@ /* Transmit Done Queue Status Definitions */ -#define LEMAC_TDQ_COL 0x03 /* Collision Mask */ +#define LEMAC_TDQ_COL 0x03 /* Collision Mask */ #define LEMAC_TDQ_NOCOL 0x00 /* No Collisions */ #define LEMAC_TDQ_ONECOL 0x01 /* One Collision */ #define LEMAC_TDQ_MULCOL 0x02 /* Multiple Collisions */ diff --git a/sys/i386/isa/ic/ncr5380.h b/sys/i386/isa/ic/ncr5380.h index f4eec05..ce14fec 100644 --- a/sys/i386/isa/ic/ncr5380.h +++ b/sys/i386/isa/ic/ncr5380.h @@ -14,8 +14,8 @@ * Derived from "NCR 53C80 Family SCSI Protocol Controller Data Manual" */ -#ifndef _IC_NCR_5380_H_ -#define _IC_NCR_5380_H_ +#ifndef _IC_NCR_5380_H_ +#define _IC_NCR_5380_H_ #define C80_CSDR 0 /* ro - Current SCSI Data Reg. */ #define C80_ODR 0 /* wo - Output Data Reg. */ @@ -33,7 +33,7 @@ #define ICR_ASSERT_DATA_BUS 0x01 #define ICR_BITS "\20\1dbus\2atn\3sel\4bsy\5ack\6arblost\7arb\10rst" -/* +/* * The mask to use when doing read_modify_write on ICR. */ #define ICR_MASK (~(ICR_DIFF_ENABLE | ICR_TRI_STATE_MODE)) |