diff options
author | kato <kato@FreeBSD.org> | 1999-01-03 05:03:47 +0000 |
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committer | kato <kato@FreeBSD.org> | 1999-01-03 05:03:47 +0000 |
commit | 0f0d2d450c1d6a153519a59e4b34cdb037866ac6 (patch) | |
tree | eec52e811a989ac6201b95d8f68f57c749f27210 /sys/i386/isa/ic | |
parent | 468764485dac67e8142ed504f2ee139f9fe42f50 (diff) | |
download | FreeBSD-src-0f0d2d450c1d6a153519a59e4b34cdb037866ac6.zip FreeBSD-src-0f0d2d450c1d6a153519a59e4b34cdb037866ac6.tar.gz |
Support following devices:
- on board 2nd CCU
- Midori Elec. MDC-926Rs
- Midori-Hayes ESP98
- NEC PC-9861K, PC-9801-101 PC-9801-120
- Melco IND-SP and IND-SS
- PIO-9032A/B/C
- B98-01 and B98-02
- IO-data device RSA-98II and RSA-98III
- MC-16550
- MC-RS98
- Media Inteligent RSB-2000/3000 and RSB-384
- PCMCIA modem card
Submitted by: Takahashi Yoshihiro <nyan@wyvern.cc.kogakuin.ac.jp>
Diffstat (limited to 'sys/i386/isa/ic')
-rw-r--r-- | sys/i386/isa/ic/esp.h | 10 | ||||
-rw-r--r-- | sys/i386/isa/ic/ns16550.h | 119 |
2 files changed, 114 insertions, 15 deletions
diff --git a/sys/i386/isa/ic/esp.h b/sys/i386/isa/ic/esp.h index 6621e65..bdc0c8a 100644 --- a/sys/i386/isa/ic/esp.h +++ b/sys/i386/isa/ic/esp.h @@ -26,7 +26,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id$ + * $Id: esp.h,v 1.3 1997/02/22 09:38:00 peter Exp $ */ #ifndef _IC_ESP_H_ @@ -39,8 +39,13 @@ /* * CMD1 and CMD2 are the command ports, offsets from <esp_iobase>. */ +#ifdef PC98 +#define ESP_CMD1 0x400 +#define ESP_CMD2 0x500 +#else #define ESP_CMD1 4 #define ESP_CMD2 5 +#endif /* * STAT1 and STAT2 are to get return values and status bytes; @@ -59,6 +64,9 @@ #define ESP_SETFLOWTYPE 0x08 /* set type of flow-control (2 bytes) */ #define ESP_SETRXFLOW 0x0a /* set Rx FIFO flow control levels (4 bytes) */ #define ESP_SETMODE 0x10 /* set board mode (1 byte) */ +#ifdef PC98 +#define ESP_SETCLOCK 0x23 /* set UART clock prescaler */ +#endif /* Mode bits (ESP_SETMODE). */ #define ESP_MODE_FIFO 0x02 /* act like a 16550 (compatibility mode) */ diff --git a/sys/i386/isa/ic/ns16550.h b/sys/i386/isa/ic/ns16550.h index ba33888..e258a1e 100644 --- a/sys/i386/isa/ic/ns16550.h +++ b/sys/i386/isa/ic/ns16550.h @@ -31,25 +31,12 @@ * SUCH DAMAGE. * * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 - * $Id$ + * $Id: ns16550.h,v 1.5 1997/02/22 09:38:05 peter Exp $ */ /* * NS16550 UART registers */ -#ifdef PC98 -#define com_data 0x000 /* data register (R/W) */ -#define com_dlbl 0x000 /* divisor latch low (W) */ -#define com_dlbh 0x100 /* divisor latch high (W) */ -#define com_ier 0x100 /* interrupt enable (W) */ -#define com_iir 0x200 /* interrupt identification (R) */ -#define com_fifo 0x200 /* FIFO control (W) */ -#define com_lctl 0x300 /* line control register (R/W) */ -#define com_cfcr 0x300 /* line control register (R/W) */ -#define com_mcr 0x400 /* modem control register (R/W) */ -#define com_lsr 0x500 /* line status register (R/W) */ -#define com_msr 0x600 /* modem status register (R/W) */ -#else /* IBM-PC */ #define com_data 0 /* data register (R/W) */ #define com_dlbl 0 /* divisor latch low (W) */ #define com_dlbh 1 /* divisor latch high (W) */ @@ -61,4 +48,108 @@ #define com_mcr 4 /* modem control register (R/W) */ #define com_lsr 5 /* line status register (R/W) */ #define com_msr 6 /* modem status register (R/W) */ + +#ifdef PC98 +#define com_emr com_msr /* Extension mode register for RSB-2000/3000. */ + +/* I/O-DATA RSA Serise Exrension Register */ +#define rsa_msr 0 /* Mode Status Register (R/W) */ +#define rsa_ier 1 /* Interrupt Enable Register (R/W) */ +#define rsa_srr 2 /* Status Read Register (R) */ +#define rsa_frr 2 /* FIFO Reset Register (W) */ +#define rsa_tivsr 3 /* Timer Interval Value Set Register (R/W) */ +#define rsa_tcr 4 /* Timer Control Register (W) */ + +/* + * RSA-98III RSA Mode Driver Data Sheet + * + * <<Register Map>> + * Base + 0x00 + * Mode Select Register(Read/Write) + * bit4=interrupt type(1: level, 0: edge) + * bit3=Auto RTS-CTS Flow Control Enable + * bit2=External FIFO Enable + * bit1=Reserved(Default 0)Don't Change!! + * bit0=Swap Upper 8byte and Lower 8byte in 16byte space. + * + * Base + 0x01 + * Interrupt Enable Register(Read/Write) + * bit4=Hardware Timer Interrupt Enable + * bit3=Character Time-Out Interrupt Enable + * bit2=Tx FIFO Empty Interrupt Enable + * bit1=Tx FIFO Half Full Interrupt Enable + * bit0=Rx FIFO Half Full Interrupt Enable + * + * Base + 0x02 + * Status Read Register(Read) + * bit7=Hardware Time Out Interrupt Status(1: True, 0: False) + * bit6=Character Time Out Interrupt Status + * bit5=Rx FIFO Full Flag(0: True, 1: False) + * bit4=Rx FIFO Half Full Flag + * bit3=Rx FIFO Empty Flag + * bit2=Tx FIFO Full Flag + * bit1=Tx FIFO Half Full Flag + * bit0=Tx FIFO Empty Flag + * + * Base + 0x02 + * FIFO Reset Register(Write) + * Reset Extrnal FIFO + * + * Base + 0x03 + * Timer Interval Value Set Register(Read/Write) + * Range of n: 1-255 + * Interval Value: n * 0.2ms + * + * Base + 0x04 + * Timer Control Register(Read/Write) + * bit0=Timer Enable + * + * Base + 0x08 - 0x0f + * Same as UART 16550 + * + * Special Regisgter in RSA Mode + * UART Data Register(Base + 0x08) + * Data transfer between Extrnal FIFO + * + * UART MCR(Base + 0x0c) + * bit3(OUT2[MCR_IENABLE])=1: Diable 16550 to Rx FIFO transfer + * bit2(OUT1[MCR_DRS])=1: Diable Tx FIFO to 16550 transfer + * + * <<Intrrupt and Intrrupt Reset>> + * o Reciver Line Status(from UART16550) + * Reset: Read LSR + * + * o Modem Status(from UART16550) + * Reset: Read MSR + * + * o Rx FIFO Half Full(from Extrnal FIFO) + * Reset: Read Rx FIFO under Hall Full + * + * o Character Time Out(from Extrnal FIFO) + * Reset: Read Rx FIFO or SRR + * + * o Tx FIFO Empty(from Extrnal FIFO) + * Reset: Write Tx FIFO or Read SRR + * + * o Tx FIFO Half Full(from Extrnal FIFO) + * Reset: Write Tx FIFO until Hall Full or Read SRR + * + * o Hardware Timer(from Extrnal FIFO) + * Reset: Disable Timer in TCR + * Notes: If you want to use Timer for next intrrupt, + * you must enable Timer in TCR + * + * <<Used Setting>> + * Auto RTS-CTS: Enable or Disable + * External FIFO: Enable + * Swap 8bytes: Disable + * Haredware Timer: Disable + * interrupt type: edge + * interrupt source: + * Hareware Timer + * Character Time Out + * Tx FIFO Empty + * Rx FIFO Half Full + * + */ #endif /* PC98 */ |