diff options
author | peter <peter@FreeBSD.org> | 1997-06-22 16:04:22 +0000 |
---|---|---|
committer | peter <peter@FreeBSD.org> | 1997-06-22 16:04:22 +0000 |
commit | 2dc5ff96e76a38f1a5ffd4c22e350c882f7592eb (patch) | |
tree | 281c7f0e4899a210947f7dfa14231536350272d2 /sys/i386/isa/apic_vector.s | |
parent | e0245a10b266a1abf80916d730d18966653de374 (diff) | |
download | FreeBSD-src-2dc5ff96e76a38f1a5ffd4c22e350c882f7592eb.zip FreeBSD-src-2dc5ff96e76a38f1a5ffd4c22e350c882f7592eb.tar.gz |
Preliminary support for per-cpu data pages.
This eliminates a lot of #ifdef SMP type code. Things like _curproc reside
in a data page that is unique on each cpu, eliminating the expensive macros
like: #define curproc (SMPcurproc[cpunumber()])
There are some unresolved bootstrap and address space sharing issues at
present, but Steve is waiting on this for other work. There is still some
strictly temporary code present that isn't exactly pretty.
This is part of a larger change that has run into some bumps, this part is
standalone so it should be safe. The temporary code goes away when the
full idle cpu support is finished.
Reviewed by: fsmp, dyson
Diffstat (limited to 'sys/i386/isa/apic_vector.s')
-rw-r--r-- | sys/i386/isa/apic_vector.s | 25 |
1 files changed, 12 insertions, 13 deletions
diff --git a/sys/i386/isa/apic_vector.s b/sys/i386/isa/apic_vector.s index 0817521..fa7edb0 100644 --- a/sys/i386/isa/apic_vector.s +++ b/sys/i386/isa/apic_vector.s @@ -1,6 +1,6 @@ /* * from: vector.s, 386BSD 0.1 unknown origin - * $Id: apic_vector.s,v 1.1 1997/05/26 17:58:26 fsmp Exp $ + * $Id: apic_vector.s,v 1.2 1997/05/31 08:59:51 peter Exp $ */ @@ -11,19 +11,19 @@ #define REDTBL_IDX(irq_num) (0x10 + ((irq_num) * 2)) /* - * 'lazy masking' code submitted by: Bruce Evans <bde@zeta.org.au> + * 'lazy masking' code suggested by Bruce Evans <bde@zeta.org.au> */ #define MAYBE_MASK_IRQ(irq_num) \ testl $IRQ_BIT(irq_num),iactive ; /* lazy masking */ \ je 1f ; /* NOT currently active */ \ orl $IRQ_BIT(irq_num),_imen ; /* set the mask bit */ \ - movl _io_apic_base,%ecx ; /* io apic addr */ \ + movl _ioapic,%ecx ; /* ioapic[0]addr */ \ movl $REDTBL_IDX(irq_num),(%ecx) ; /* write the index */ \ movl IOAPIC_WINDOW(%ecx),%eax ; /* current value */ \ orl $IOART_INTMASK,%eax ; /* set the mask */ \ movl %eax,IOAPIC_WINDOW(%ecx) ; /* new value */ \ - movl _apic_base, %eax ; \ - movl $0, APIC_EOI(%eax) ; \ + movl $lapic_eoi, %eax ; \ + movl $0, (%eax) ; \ orl $IRQ_BIT(irq_num), _ipending ; \ REL_MPLOCK ; /* SMP release global lock */ \ popl %es ; \ @@ -43,7 +43,7 @@ testl $IRQ_BIT(irq_num),_imen ; \ je 2f ; \ andl $~IRQ_BIT(irq_num),_imen ; /* clear mask bit */ \ - movl _io_apic_base,%ecx ; /* io apic addr */ \ + movl _ioapic,%ecx ; /* ioapic[0]addr */ \ movl $REDTBL_IDX(irq_num),(%ecx) ; /* write the index */ \ movl IOAPIC_WINDOW(%ecx),%eax ; /* current value */ \ andl $~IOART_INTMASK,%eax ; /* clear the mask */ \ @@ -72,8 +72,8 @@ IDTVEC(vec_name) ; \ GET_MPLOCK ; /* SMP Spin lock */ \ pushl _intr_unit + (irq_num) * 4 ; \ call *_intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \ - movl _apic_base, %eax ; \ - movl $0, APIC_EOI(%eax) ; \ + movl $lapic_eoi, %eax ; \ + movl $0, (%eax) ; \ addl $4,%esp ; \ incl _cnt+V_INTR ; /* book-keeping can wait */ \ movl _intr_countp + (irq_num) * 4,%eax ; \ @@ -132,8 +132,8 @@ IDTVEC(vec_name) ; \ movl %ax,%es ; \ GET_MPLOCK ; /* SMP Spin lock */ \ MAYBE_MASK_IRQ(irq_num) ; \ - movl _apic_base, %eax ; \ - movl $0, APIC_EOI(%eax) ; \ + movl $lapic_eoi, %eax ; \ + movl $0, (%eax) ; \ movl _cpl,%eax ; \ testl $IRQ_BIT(irq_num), %eax ; \ jne 3f ; \ @@ -172,10 +172,9 @@ _Xinvltlb: pushl %eax movl %cr3, %eax /* invalidate the TLB */ movl %eax, %cr3 + movl $lapic_eoi, %eax ss /* stack segment, avoid %ds load */ - movl _apic_base, %eax - ss - movl $0, APIC_EOI(%eax) /* End Of Interrupt to APIC */ + movl $0, (%eax) /* End Of Interrupt to APIC */ popl %eax iret |