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authorbde <bde@FreeBSD.org>2001-05-24 16:52:13 +0000
committerbde <bde@FreeBSD.org>2001-05-24 16:52:13 +0000
commit6d9516e26fb8eb83c9494601ea0662eecf20cc9d (patch)
treef5f38249cb654ad6df1108789bd2b22b602df845 /sys/gnu/dev
parent1fdf57d327ca8bed8af253373e4a1b50f2bc2f90 (diff)
downloadFreeBSD-src-6d9516e26fb8eb83c9494601ea0662eecf20cc9d.zip
FreeBSD-src-6d9516e26fb8eb83c9494601ea0662eecf20cc9d.tar.gz
Remove vestiges of the old, broken sound drivers.
Diffstat (limited to 'sys/gnu/dev')
-rw-r--r--sys/gnu/dev/sound/pci/emu10k1.h674
-rw-r--r--sys/gnu/dev/sound/pci/maestro3_dsp.h214
-rw-r--r--sys/gnu/dev/sound/pci/maestro3_reg.h692
3 files changed, 0 insertions, 1580 deletions
diff --git a/sys/gnu/dev/sound/pci/emu10k1.h b/sys/gnu/dev/sound/pci/emu10k1.h
deleted file mode 100644
index 0ee34c6..0000000
--- a/sys/gnu/dev/sound/pci/emu10k1.h
+++ /dev/null
@@ -1,674 +0,0 @@
-/*
- **********************************************************************
- * emu10k1.h, derived from 8010.h
- * Copyright 1999, 2000 Creative Labs, Inc.
- *
- **********************************************************************
- *
- * Date Author Summary of changes
- * ---- ------ ------------------
- * October 20, 1999 Bertrand Lee base code release
- * November 2, 1999 Alan Cox Cleaned of 8bit chars, DOS
- * line endings
- * December 8, 1999 Jon Taylor Added lots of new register info
- *
- **********************************************************************
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this program; if not, write to the Free
- * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139,
- * USA.
- *
- *
- **********************************************************************
- * $FreeBSD$
- */
-
-
-#ifndef EMU10K1_H
-#define EMU10K1_H
-
-/* ------------------- DEFINES -------------------- */
-
-#define EMUPAGESIZE 4096 /* don't change */
-#define MAXREQVOICES 8
-#define MAXPAGES (32768 * 64 / EMUPAGESIZE) /* WAVEOUT_MAXBUFSIZE * NUM_G / EMUPAGESIZE */
-#define RESERVED 0
-#define NUM_MIDI 16
-#define NUM_G 64 /* use all channels */
-#define NUM_FXSENDS 4
-
-
-#define TMEMSIZE 256*1024
-#define TMEMSIZEREG 4
-
-#define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
-
-/************************************************************************************************/
-/* PCI function 0 registers, address = <val> + PCIBASE0 */
-/************************************************************************************************/
-
-#define PTR 0x00 /* Indexed register set pointer register */
- /* NOTE: The CHANNELNUM and ADDRESS words can */
- /* be modified independently of each other. */
-#define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
- /* channel number of the register to be */
- /* accessed. For non per-channel registers the */
- /* value should be set to zero. */
-#define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */
-
-#define DATA 0x04 /* Indexed register set data register */
-
-#define IPR 0x08 /* Global interrupt pending register */
- /* Clear pending interrupts by writing a 1 to */
- /* the relevant bits and zero to the other bits */
-#define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */
-#define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */
-#define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */
-#define IPR_PCIERROR 0x00200000 /* PCI bus error */
-#define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */
-#define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */
-#define IPR_MUTE 0x00040000 /* Mute button pressed */
-#define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */
-#define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */
-#define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */
-#define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */
-#define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */
-#define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */
-#define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */
-#define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
-#define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */
-#define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */
-#define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */
-#define IPR_CHANNELLOOP 0x00000040 /* One or more channel loop interrupts pending */
-#define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */
- /* Highest set channel in CLIPL or CLIPH. When */
- /* IP is written with CL set, the bit in CLIPL */
- /* or CLIPH corresponding to the CIN value */
- /* written will be cleared. */
-
-#define INTE 0x0c /* Interrupt enable register */
-#define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */
-#define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
-#define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */
-#define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */
-#define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */
-#define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */
-#define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
-#define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */
-#define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */
-#define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */
-#define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
-#define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
-#define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
-#define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
-#define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */
-#define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
-#define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */
-#define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */
-
-#define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */
- /* NOTE: There is no reason to use this under */
- /* Linux, and it will cause odd hardware */
- /* behavior and possibly random segfaults and */
- /* lockups if enabled. */
-
-#define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */
- /* NOTE: This bit must always be enabled */
-#define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */
-#define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */
-#define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */
-#define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */
-#define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */
-#define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */
-#define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */
-#define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */
-#define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */
-#define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */
-#define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */
-#define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
-#define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
-
-#define WC 0x10 /* Wall Clock register */
-#define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */
-#define WC_SAMPLECOUNTER 0x14060010
-#define WC_CURRENTCHANNEL 0x0000003F /* Channel [0..63] currently being serviced */
- /* NOTE: Each channel takes 1/64th of a sample */
- /* period to be serviced. */
-
-#define HCFG 0x14 /* Hardware config register */
- /* NOTE: There is no reason to use the legacy */
- /* SoundBlaster emulation stuff described below */
- /* under Linux, and all kinds of weird hardware */
- /* behavior can result if you try. Don't. */
-#define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */
-#define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */
-#define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */
-#define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */
-#define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */
-#define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */
-#define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */
-#define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */
-#define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */
-#define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */
-#define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */
-#define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */
- /* NOTE: The rest of the bits in this register */
- /* _are_ relevant under Linux. */
-#define HCFG_CODECFORMAT_MASK 0x00070000 /* CODEC format */
-#define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
-#define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
-#define HCFG_GPINPUT0 0x00004000 /* External pin112 */
-#define HCFG_GPINPUT1 0x00002000 /* External pin110 */
-#define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */
-#define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */
-#define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */
- /* 1 = Force all 3 async digital inputs to use */
- /* the same async sample rate tracker (ZVIDEO) */
-#define HCFG_AC3ENABLE_MASK 0x0x0000e0 /* AC3 async input control - Not implemented */
-#define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */
-#define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */
-#define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */
- /* will automatically mute their output when */
- /* they are not rate-locked to the external */
- /* async audio source */
-#define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
- /* NOTE: This should generally never be used. */
-#define HCFG_LOCKTANKCACHE 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */
- /* NOTE: This should generally never be used. */
-#define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */
- /* NOTE: This is a 'cheap' way to implement a */
- /* master mute function on the mute button, and */
- /* in general should not be used unless a more */
- /* sophisticated master mute function has not */
- /* been written. */
-#define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
- /* Should be set to 1 when the EMU10K1 is */
- /* completely initialized. */
-
-#define MUDATA 0x18 /* MPU401 data register (8 bits) */
-
-#define MUCMD 0x19 /* MPU401 command register (8 bits) */
-#define MUCMD_RESET 0xff /* RESET command */
-#define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */
- /* NOTE: All other commands are ignored */
-
-#define MUSTAT MUCMD /* MPU401 status register (8 bits) */
-#define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */
-#define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */
-
-#define TIMER 0x1a /* Timer terminal count register */
- /* NOTE: After the rate is changed, a maximum */
- /* of 1024 sample periods should be allowed */
- /* before the new rate is guaranteed accurate. */
-#define TIMER_RATE_MASK 0x000003ff /* Timer interrupt rate in sample periods */
- /* 0 == 1024 periods, [1..4] are not useful */
-#define TIMER_RATE 0x0a00001a
-
-#define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
-
-#define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
-#define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
-#define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */
-
-/************************************************************************************************/
-/* PCI function 1 registers, address = <val> + PCIBASE1 */
-/************************************************************************************************/
-
-#define JOYSTICK1 0x00 /* Analog joystick port register */
-#define JOYSTICK2 0x01 /* Analog joystick port register */
-#define JOYSTICK3 0x02 /* Analog joystick port register */
-#define JOYSTICK4 0x03 /* Analog joystick port register */
-#define JOYSTICK5 0x04 /* Analog joystick port register */
-#define JOYSTICK6 0x05 /* Analog joystick port register */
-#define JOYSTICK7 0x06 /* Analog joystick port register */
-#define JOYSTICK8 0x07 /* Analog joystick port register */
-
-/* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */
-/* When reading, use these bitfields: */
-#define JOYSTICK_BUTTONS 0x0f /* Joystick button data */
-#define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */
-
-
-/********************************************************************************************************/
-/* AC97 pointer-offset register set, accessed through the AC97ADDRESS and AC97DATA registers */
-/********************************************************************************************************/
-
-#define AC97_RESET 0x00
-#define AC97_MASTERVOLUME 0x02 /* Master volume */
-#define AC97_HEADPHONEVOLUME 0x04 /* Headphone volume */
-#define AC97_MASTERVOLUMEMONO 0x06 /* Mast volume mono */
-#define AC97_MASTERTONE 0x08
-#define AC97_PCBEEPVOLUME 0x0a /* PC speaker system beep volume */
-#define AC97_PHONEVOLUME 0x0c
-#define AC97_MICVOLUME 0x0e
-#define AC97_LINEINVOLUME 0x10
-#define AC97_CDVOLUME 0x12
-#define AC97_VIDEOVOLUME 0x14
-#define AC97_AUXVOLUME 0x16
-#define AC97_PCMOUTVOLUME 0x18
-#define AC97_RECORDSELECT 0x1a
-#define AC97_RECORDGAIN 0x1c
-#define AC97_RECORDGAINMIC 0x1e
-#define AC97_GENERALPUPOSE 0x20
-#define AC97_3DCONTROL 0x22
-#define AC97_MODEMRATE 0x24
-#define AC97_POWERDOWN 0x26
-#define AC97_VENDORID1 0x7c
-#define AC97_VENDORID2 0x7e
-#define AC97_ZVIDEOVOLUME 0xec
-#define AC97_AC3VOLUME 0xed
-
-/********************************************************************************************************/
-/* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
-/********************************************************************************************************/
-
-#define CPF 0x00 /* Current pitch and fraction register */
-#define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */
-#define CPF_CURRENTPITCH 0x10100000
-#define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */
-#define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */
-#define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */
-
-#define PTRX 0x01 /* Pitch target and send A/B amounts register */
-#define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */
-#define PTRX_PITCHTARGET 0x10100001
-#define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A */
-#define PTRX_FXSENDAMOUNT_A 0x08080001
-#define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */
-#define PTRX_FXSENDAMOUNT_B 0x08000001
-
-#define CVCF 0x02 /* Current volume and filter cutoff register */
-#define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */
-#define CVCF_CURRENTVOL 0x10100002
-#define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */
-#define CVCF_CURRENTFILTER 0x10000002
-
-#define VTFT 0x03 /* Volume target and filter cutoff target register */
-#define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */
-#define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */
-
-#define Z1 0x05 /* Filter delay memory 1 register */
-
-#define Z2 0x04 /* Filter delay memory 2 register */
-
-#define PSST 0x06 /* Send C amount and loop start address register */
-#define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */
-
-#define PSST_FXSENDAMOUNT_C 0x08180006
-
-#define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */
-#define PSST_LOOPSTARTADDR 0x18000006
-
-#define DSL 0x07 /* Send D amount and loop start address register */
-#define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */
-
-#define DSL_FXSENDAMOUNT_D 0x08180007
-
-#define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */
-#define DSL_LOOPENDADDR 0x18000007
-
-#define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */
-#define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */
-#define CCCA_INTERPROMMASK 0x0e000000 /* Selects passband of interpolation ROM */
- /* 1 == full band, 7 == lowpass */
- /* ROM 0 is used when pitch shifting downward or less */
- /* then 3 semitones upward. Increasingly higher ROM */
- /* numbers are used, typically in steps of 3 semitones, */
- /* as upward pitch shifting is performed. */
-#define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */
-#define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */
-#define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */
-#define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */
-#define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */
-#define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */
-#define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */
-#define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */
-#define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
-#define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */
-#define CCCA_CURRADDR 0x18000008
-
-#define CCR 0x09 /* Cache control register */
-#define CCR_CACHEINVALIDSIZE 0x07190009
-#define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples cache for this channel */
-#define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */
-#define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */
-#define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */
-#define CCR_READADDRESS 0x06100009
-#define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */
-#define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */
- /* NOTE: This is valid only if CACHELOOPFLAG is set */
-#define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */
-#define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
-
-#define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */
- /* NOTE: This register is normally not used */
-#define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */
-
-#define FXRT 0x0b /* Effects send routing register */
- /* NOTE: It is illegal to assign the same routing to */
- /* two effects sends. */
-#define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */
-#define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */
-#define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
-#define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
-
-#define MAPA 0x0c /* Cache map A */
-
-#define MAPB 0x0d /* Cache map B */
-
-#define MAP_PTE_MASK 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */
-#define MAP_PTI_MASK 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
-
-#define ENVVOL 0x10 /* Volume envelope register */
-#define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */
- /* 0x8000-n == 666*n usec delay */
-
-#define ATKHLDV 0x11 /* Volume envelope hold and attack register */
-#define ATKHLDV_PHASE0 0x00008000 /* 0 = Begin attack phase */
-#define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
-#define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */
- /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */
-
-#define DCYSUSV 0x12 /* Volume envelope sustain and decay register */
-#define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
-#define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
-#define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1 = Inhibit envelope engine from writing values in */
- /* this channel and from writing to pitch, filter and */
- /* volume targets. */
-#define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */
- /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
-
-#define LFOVAL1 0x13 /* Modulation LFO value */
-#define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */
- /* 0x8000-n == 666*n usec delay */
-
-#define ENVVAL 0x14 /* Modulation envelope register */
-#define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */
- /* 0x8000-n == 666*n usec delay */
-
-#define ATKHLDM 0x15 /* Modulation envelope hold and attack register */
-#define ATKHLDM_PHASE0 0x00008000 /* 0 = Begin attack phase */
-#define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
-#define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */
- /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */
-
-#define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */
-#define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
-#define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
-#define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */
- /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
-
-#define LFOVAL2 0x17 /* Vibrato LFO register */
-#define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */
- /* 0x8000-n == 666*n usec delay */
-
-#define IP 0x18 /* Initial pitch register */
-#define IP_MASK 0x0000ffff /* Exponential initial pitch shift */
- /* 4 bits of octave, 12 bits of fractional octave */
-#define IP_UNITY 0x0000e000 /* Unity pitch shift */
-
-#define IFATN 0x19 /* Initial filter cutoff and attenuation register */
-#define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */
- /* 6 most significant bits are semitones */
- /* 2 least significant bits are fractions */
-#define IFATN_FILTERCUTOFF 0x08080019
-#define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */
-#define IFATN_ATTENUATION 0x08000019
-
-
-#define PEFE 0x1a /* Pitch envelope and filter envelope amount register */
-#define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */
- /* Signed 2's complement, +/- one octave peak extremes */
-#define PEFE_PITCHAMOUNT 0x0808001a
-#define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */
- /* Signed 2's complement, +/- six octaves peak extremes */
-#define PEFE_FILTERAMOUNT 0x0800001a
-#define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */
-#define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */
- /* Signed 2's complement, +/- one octave extremes */
-#define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */
- /* Signed 2's complement, +/- three octave extremes */
-
-
-#define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */
-#define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */
- /* Signed 2's complement, with +/- 12dB extremes */
-
-#define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */
-#define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */
- /* Signed 2's complement, +/- one octave extremes */
-#define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */
- /* 0.039Hz steps, maximum of 9.85 Hz. */
-
-#define TEMPENV 0x1e /* Tempory envelope register */
-#define TEMPENV_MASK 0x0000ffff /* 16-bit value */
- /* NOTE: All channels contain internal variables; do */
- /* not write to these locations. */
-
-#define CD0 0x20 /* Cache data 0 register */
-#define CD1 0x21 /* Cache data 1 register */
-#define CD2 0x22 /* Cache data 2 register */
-#define CD3 0x23 /* Cache data 3 register */
-#define CD4 0x24 /* Cache data 4 register */
-#define CD5 0x25 /* Cache data 5 register */
-#define CD6 0x26 /* Cache data 6 register */
-#define CD7 0x27 /* Cache data 7 register */
-#define CD8 0x28 /* Cache data 8 register */
-#define CD9 0x29 /* Cache data 9 register */
-#define CDA 0x2a /* Cache data A register */
-#define CDB 0x2b /* Cache data B register */
-#define CDC 0x2c /* Cache data C register */
-#define CDD 0x2d /* Cache data D register */
-#define CDE 0x2e /* Cache data E register */
-#define CDF 0x2f /* Cache data F register */
-
-#define PTB 0x40 /* Page table base register */
-#define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */
-
-#define TCB 0x41 /* Tank cache base register */
-#define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */
-
-#define ADCCR 0x42 /* ADC sample rate/stereo control register */
-#define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */
-#define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */
- /* NOTE: To guarantee phase coherency, both channels */
- /* must be disabled prior to enabling both channels. */
-#define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */
-#define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
-#define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
-#define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
-#define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */
-#define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */
-#define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */
-#define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */
-#define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */
-
-#define FXWC 0x43 /* FX output write channels register */
- /* When set, each bit enables the writing of the */
- /* corresponding FX output channel into host memory */
-
-#define TCBS 0x44 /* Tank cache buffer size register */
-#define TCBS_MASK 0x00000007 /* Tank cache buffer size field */
-#define TCBS_BUFFSIZE_16K 0x00000000
-#define TCBS_BUFFSIZE_32K 0x00000001
-#define TCBS_BUFFSIZE_64K 0x00000002
-#define TCBS_BUFFSIZE_128K 0x00000003
-#define TCBS_BUFFSIZE_256K 0x00000004
-#define TCBS_BUFFSIZE_512K 0x00000005
-#define TCBS_BUFFSIZE_1024K 0x00000006
-#define TCBS_BUFFSIZE_2048K 0x00000007
-
-#define MICBA 0x45 /* AC97 microphone buffer address register */
-#define MICBA_MASK 0xfffff000 /* 20 bit base address */
-
-#define ADCBA 0x46 /* ADC buffer address register */
-#define ADCBA_MASK 0xfffff000 /* 20 bit base address */
-
-#define FXBA 0x47 /* FX Buffer Address */
-#define FXBA_MASK 0xfffff000 /* 20 bit base address */
-
-#define MICBS 0x49 /* Microphone buffer size register */
-
-#define ADCBS 0x4a /* ADC buffer size register */
-
-#define FXBS 0x4b /* FX buffer size register */
-
-/* The following mask values define the size of the ADC, MIX and FX buffers in bytes */
-#define ADCBS_BUFSIZE_NONE 0x00000000
-#define ADCBS_BUFSIZE_384 0x00000001
-#define ADCBS_BUFSIZE_448 0x00000002
-#define ADCBS_BUFSIZE_512 0x00000003
-#define ADCBS_BUFSIZE_640 0x00000004
-#define ADCBS_BUFSIZE_768 0x00000005
-#define ADCBS_BUFSIZE_896 0x00000006
-#define ADCBS_BUFSIZE_1024 0x00000007
-#define ADCBS_BUFSIZE_1280 0x00000008
-#define ADCBS_BUFSIZE_1536 0x00000009
-#define ADCBS_BUFSIZE_1792 0x0000000a
-#define ADCBS_BUFSIZE_2048 0x0000000b
-#define ADCBS_BUFSIZE_2560 0x0000000c
-#define ADCBS_BUFSIZE_3072 0x0000000d
-#define ADCBS_BUFSIZE_3584 0x0000000e
-#define ADCBS_BUFSIZE_4096 0x0000000f
-#define ADCBS_BUFSIZE_5120 0x00000010
-#define ADCBS_BUFSIZE_6144 0x00000011
-#define ADCBS_BUFSIZE_7168 0x00000012
-#define ADCBS_BUFSIZE_8192 0x00000013
-#define ADCBS_BUFSIZE_10240 0x00000014
-#define ADCBS_BUFSIZE_12288 0x00000015
-#define ADCBS_BUFSIZE_14366 0x00000016
-#define ADCBS_BUFSIZE_16384 0x00000017
-#define ADCBS_BUFSIZE_20480 0x00000018
-#define ADCBS_BUFSIZE_24576 0x00000019
-#define ADCBS_BUFSIZE_28672 0x0000001a
-#define ADCBS_BUFSIZE_32768 0x0000001b
-#define ADCBS_BUFSIZE_40960 0x0000001c
-#define ADCBS_BUFSIZE_49152 0x0000001d
-#define ADCBS_BUFSIZE_57344 0x0000001e
-#define ADCBS_BUFSIZE_65536 0x0000001f
-
-
-#define CDCS 0x50 /* CD-ROM digital channel status register */
-
-#define GPSCS 0x51 /* General Purpose SPDIF channel status register*/
-
-#define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
-
-#define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
-
-#define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
-
-#define SPCS1 0x55 /* SPDIF output Channel Status 1 register */
-
-#define SPCS2 0x56 /* SPDIF output Channel Status 2 register */
-
-#define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
-#define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
-#define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
-#define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
-#define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
-#define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
-#define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
-#define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
-#define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
-#define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
-#define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
-#define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
-#define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
-#define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
-#define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
-#define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
-#define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
-#define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
-#define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
-#define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
-#define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
-#define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
-#define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
-
-/* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */
-#define CLIEL 0x58 /* Channel loop interrupt enable low register */
-
-#define CLIEH 0x59 /* Channel loop interrupt enable high register */
-
-#define CLIPL 0x5a /* Channel loop interrupt pending low register */
-
-#define CLIPH 0x5b /* Channel loop interrupt pending high register */
-
-#define SOLEL 0x5c /* Stop on loop enable low register */
-
-#define SOLEH 0x5d /* Stop on loop enable high register */
-
-#define SPBYPASS 0x5e /* SPDIF BYPASS mode register */
-#define SPBYPASS_ENABLE 0x00000001 /* Enable SPDIF bypass mode */
-
-#define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
-
-#define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */
-
-#define ZVSRCS 0x62 /* ZVideo sample rate converter status */
- /* NOTE: This one has no SPDIFLOCKED field */
- /* Assumes sample lock */
-
-/* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */
-#define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */
-#define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */
-#define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */
-
-#define MICIDX 0x63 /* Microphone recording buffer index register */
-#define MICIDX_MASK 0x0000ffff /* 16-bit value */
-#define MICIDX_IDX 0x10000063
-
-#define ADCIDX 0x64 /* ADC recording buffer index register */
-#define ADCIDX_MASK 0x0000ffff /* 16 bit index field */
-#define ADCIDX_IDX 0x10000064
-
-#define FXIDX 0x65 /* FX recording buffer index register */
-#define FXIDX_MASK 0x0000ffff /* 16-bit value */
-#define FXIDX_IDX 0x10000065
-
-/* Each FX general purpose register is 32 bits in length, all bits are used */
-#define FXGPREGBASE 0x100 /* FX general purpose registers base */
-
-/* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
-/* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
-/* locations are for external TRAM. */
-#define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
-#define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
-
-/* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */
-#define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
-#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
-#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
-#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
-#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
-#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
-
-#define MICROCODEBASE 0x400 /* Microcode data base address */
-
-/* Each DSP microcode instruction is mapped into 2 doublewords */
-/* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */
-#define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
-#define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
-#define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
-#define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
-#define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
-
-#define ENABLE 0xffffffff
-#define DISABLE 0x00000000
-
-#define ENV_ON 0x80
-#define ENV_OFF 0x00
-
-#endif /* EMU10K1_H */
diff --git a/sys/gnu/dev/sound/pci/maestro3_dsp.h b/sys/gnu/dev/sound/pci/maestro3_dsp.h
deleted file mode 100644
index 9c14f33..0000000
--- a/sys/gnu/dev/sound/pci/maestro3_dsp.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/* $FreeBSD$ */
-/*
- * ESS Technology allegro audio driver.
- *
- * Copyright (C) 1992-2000 Don Kim (don.kim@esstech.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Hacked for the maestro3 driver by zab
- */
-
-/*
- * DSP Code images
- */
-
-u_int16_t assp_kernel_image[] = {
- 0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4,
- 0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
- 0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
- 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4,
- 0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08,
- 0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909,
- 0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41,
- 0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308,
- 0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910,
- 0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00,
- 0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026,
- 0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0,
- 0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012,
- 0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A,
- 0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000,
- 0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05,
- 0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26,
- 0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300,
- 0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88,
- 0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008,
- 0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80,
- 0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71,
- 0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A,
- 0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100,
- 0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900,
- 0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903,
- 0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309,
- 0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B,
- 0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540,
- 0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C,
- 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380,
- 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340,
- 0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041,
- 0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18,
- 0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40,
- 0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9,
- 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8,
- 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A,
- 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80,
- 0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40,
- 0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80,
- 0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A,
- 0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F,
- 0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1,
- 0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034,
- 0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E,
- 0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977,
- 0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B,
- 0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388,
- 0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80,
- 0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473,
- 0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473,
- 0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880,
- 0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80,
- 0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6,
- 0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909,
- 0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED,
- 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005,
- 0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388,
- 0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4,
- 0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100,
- 0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10,
- 0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070,
- 0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71,
- 0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A,
- 0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061,
- 0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A,
- 0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6,
- 0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A,
- 0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6,
- 0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358,
- 0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6,
- 0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9,
- 0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379,
- 0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6,
- 0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C,
- 0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166,
- 0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B,
- 0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A,
- 0xBE3A,
-};
-
-/*
- * Mini sample rate converter code image
- * that is to be loaded at 0x400 on the DSP.
- */
-u_int16_t assp_minisrc_image[] = {
- 0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412,
- 0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
- 0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
- 0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
- 0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
- 0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
- 0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD,
- 0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
- 0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0,
- 0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
- 0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
- 0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0,
- 0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484,
- 0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80,
- 0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624,
- 0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4,
- 0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027,
- 0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903,
- 0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809,
- 0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46,
- 0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
- 0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
- 0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516,
- 0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
- 0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
- 0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180,
- 0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
- 0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
- 0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
- 0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
- 0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
- 0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-};
-
-u_int16_t minisrc_lpf_image[] = {
- 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
- 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
-};
-
-/*
- * an arbitrary volume we set the internal volume settings to so that the
- * ac97 volume range is a little less insane. 0x7fff is max.
- */
-#define ARB_VOLUME 0x6800
-
-static struct play_vals {
- u_int16_t addr, val;
-} pv[] = {
- {CDATA_LEFT_VOLUME, ARB_VOLUME},
- {CDATA_RIGHT_VOLUME, ARB_VOLUME},
- {SRC3_DIRECTION_OFFSET, 0} ,
- /* +1, +2 are stereo/16 bit */
- {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
- {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
- {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
- {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
- {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
- {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
- {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
- {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
- {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
- {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
- {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
- {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
- {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
- {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
- {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
- {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
- {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
-};
-
-static struct rec_vals {
- u_int16_t addr, val;
-} rv[] = {
- {CDATA_LEFT_VOLUME, ARB_VOLUME},
- {CDATA_RIGHT_VOLUME, ARB_VOLUME},
- {SRC3_DIRECTION_OFFSET, 1},
- /* +1, +2 are stereo/16 bit */
- {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
- {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
- {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
- {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
- {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
- {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
- {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
- {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
- {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
- {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
- {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
- {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
- {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
- {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
- {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
- {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
- {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
- {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
- {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
-};
diff --git a/sys/gnu/dev/sound/pci/maestro3_reg.h b/sys/gnu/dev/sound/pci/maestro3_reg.h
deleted file mode 100644
index f74ed30..0000000
--- a/sys/gnu/dev/sound/pci/maestro3_reg.h
+++ /dev/null
@@ -1,692 +0,0 @@
-/* $FreeBSD$ */
-/*
- * ESS Technology allegro audio driver.
- *
- * Copyright (C) 1992-2000 Don Kim (don.kim@esstech.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Hacked for the maestro3 driver by zab
- */
-
-/* Allegro PCI configuration registers */
-#define PCI_LEGACY_AUDIO_CTRL 0x40
-#define SOUND_BLASTER_ENABLE 0x00000001
-#define FM_SYNTHESIS_ENABLE 0x00000002
-#define GAME_PORT_ENABLE 0x00000004
-#define MPU401_IO_ENABLE 0x00000008
-#define MPU401_IRQ_ENABLE 0x00000010
-#define ALIAS_10BIT_IO 0x00000020
-#define SB_DMA_MASK 0x000000C0
-#define SB_DMA_0 0x00000040
-#define SB_DMA_1 0x00000040
-#define SB_DMA_R 0x00000080
-#define SB_DMA_3 0x000000C0
-#define SB_IRQ_MASK 0x00000700
-#define SB_IRQ_5 0x00000000
-#define SB_IRQ_7 0x00000100
-#define SB_IRQ_9 0x00000200
-#define SB_IRQ_10 0x00000300
-#define MIDI_IRQ_MASK 0x00003800
-#define SERIAL_IRQ_ENABLE 0x00004000
-#define DISABLE_LEGACY 0x00008000
-
-#define PCI_ALLEGRO_CONFIG 0x50
-#define SB_ADDR_240 0x00000004
-#define MPU_ADDR_MASK 0x00000018
-#define MPU_ADDR_330 0x00000000
-#define MPU_ADDR_300 0x00000008
-#define MPU_ADDR_320 0x00000010
-#define MPU_ADDR_340 0x00000018
-#define USE_PCI_TIMING 0x00000040
-#define POSTED_WRITE_ENABLE 0x00000080
-#define DMA_POLICY_MASK 0x00000700
-#define DMA_DDMA 0x00000000
-#define DMA_TDMA 0x00000100
-#define DMA_PCPCI 0x00000200
-#define DMA_WBDMA16 0x00000400
-#define DMA_WBDMA4 0x00000500
-#define DMA_WBDMA2 0x00000600
-#define DMA_WBDMA1 0x00000700
-#define DMA_SAFE_GUARD 0x00000800
-#define HI_PERF_GP_ENABLE 0x00001000
-#define PIC_SNOOP_MODE_0 0x00002000
-#define PIC_SNOOP_MODE_1 0x00004000
-#define SOUNDBLASTER_IRQ_MASK 0x00008000
-#define RING_IN_ENABLE 0x00010000
-#define SPDIF_TEST_MODE 0x00020000
-#define CLK_MULT_MODE_SELECT_2 0x00040000
-#define EEPROM_WRITE_ENABLE 0x00080000
-#define CODEC_DIR_IN 0x00100000
-#define HV_BUTTON_FROM_GD 0x00200000
-#define REDUCED_DEBOUNCE 0x00400000
-#define HV_CTRL_ENABLE 0x00800000
-#define SPDIF_ENABLE 0x01000000
-#define CLK_DIV_SELECT 0x06000000
-#define CLK_DIV_BY_48 0x00000000
-#define CLK_DIV_BY_49 0x02000000
-#define CLK_DIV_BY_50 0x04000000
-#define CLK_DIV_RESERVED 0x06000000
-#define PM_CTRL_ENABLE 0x08000000
-#define CLK_MULT_MODE_SELECT 0x30000000
-#define CLK_MULT_MODE_SHIFT 28
-#define CLK_MULT_MODE_0 0x00000000
-#define CLK_MULT_MODE_1 0x10000000
-#define CLK_MULT_MODE_2 0x20000000
-#define CLK_MULT_MODE_3 0x30000000
-#define INT_CLK_SELECT 0x40000000
-#define INT_CLK_MULT_RESET 0x80000000
-
-/* M3 */
-#define INT_CLK_SRC_NOT_PCI 0x00100000
-#define INT_CLK_MULT_ENABLE 0x80000000
-
-#define PCI_ACPI_CONTROL 0x54
-#define PCI_ACPI_D0 0x00000000
-#define PCI_ACPI_D1 0xB4F70000
-#define PCI_ACPI_D2 0xB4F7B4F7
-
-#define PCI_USER_CONFIG 0x58
-#define EXT_PCI_MASTER_ENABLE 0x00000001
-#define SPDIF_OUT_SELECT 0x00000002
-#define TEST_PIN_DIR_CTRL 0x00000004
-#define AC97_CODEC_TEST 0x00000020
-#define TRI_STATE_BUFFER 0x00000080
-#define IN_CLK_12MHZ_SELECT 0x00000100
-#define MULTI_FUNC_DISABLE 0x00000200
-#define EXT_MASTER_PAIR_SEL 0x00000400
-#define PCI_MASTER_SUPPORT 0x00000800
-#define STOP_CLOCK_ENABLE 0x00001000
-#define EAPD_DRIVE_ENABLE 0x00002000
-#define REQ_TRI_STATE_ENABLE 0x00004000
-#define REQ_LOW_ENABLE 0x00008000
-#define MIDI_1_ENABLE 0x00010000
-#define MIDI_2_ENABLE 0x00020000
-#define SB_AUDIO_SYNC 0x00040000
-#define HV_CTRL_TEST 0x00100000
-#define SOUNDBLASTER_TEST 0x00400000
-
-#define PCI_USER_CONFIG_C 0x5C
-
-#define PCI_DDMA_CTRL 0x60
-#define DDMA_ENABLE 0x00000001
-
-
-/* Allegro registers */
-#define HOST_INT_CTRL 0x18
-#define SB_INT_ENABLE 0x0001
-#define MPU401_INT_ENABLE 0x0002
-#define ASSP_INT_ENABLE 0x0010
-#define RING_INT_ENABLE 0x0020
-#define HV_INT_ENABLE 0x0040
-#define CLKRUN_GEN_ENABLE 0x0100
-#define HV_CTRL_TO_PME 0x0400
-#define SOFTWARE_RESET_ENABLE 0x8000
-
-/*
- * should be using the above defines, probably.
- */
-#define REGB_ENABLE_RESET 0x01
-#define REGB_STOP_CLOCK 0x10
-
-#define HOST_INT_STATUS 0x1A
-#define SB_INT_PENDING 0x01
-#define MPU401_INT_PENDING 0x02
-#define ASSP_INT_PENDING 0x10
-#define RING_INT_PENDING 0x20
-#define HV_INT_PENDING 0x40
-
-#define HARDWARE_VOL_CTRL 0x1B
-#define SHADOW_MIX_REG_VOICE 0x1C
-#define HW_VOL_COUNTER_VOICE 0x1D
-#define SHADOW_MIX_REG_MASTER 0x1E
-#define HW_VOL_COUNTER_MASTER 0x1F
-
-#define CODEC_COMMAND 0x30
-#define CODEC_READ_B 0x80
-
-#define CODEC_STATUS 0x30
-#define CODEC_BUSY_B 0x01
-
-#define CODEC_DATA 0x32
-
-#define RING_BUS_CTRL_A 0x36
-#define RAC_PME_ENABLE 0x0100
-#define RAC_SDFS_ENABLE 0x0200
-#define LAC_PME_ENABLE 0x0400
-#define LAC_SDFS_ENABLE 0x0800
-#define SERIAL_AC_LINK_ENABLE 0x1000
-#define IO_SRAM_ENABLE 0x2000
-#define IIS_INPUT_ENABLE 0x8000
-
-#define RING_BUS_CTRL_B 0x38
-#define SECOND_CODEC_ID_MASK 0x0003
-#define SPDIF_FUNC_ENABLE 0x0010
-#define SECOND_AC_ENABLE 0x0020
-#define SB_MODULE_INTF_ENABLE 0x0040
-#define SSPE_ENABLE 0x0040
-#define M3I_DOCK_ENABLE 0x0080
-
-#define SDO_OUT_DEST_CTRL 0x3A
-#define COMMAND_ADDR_OUT 0x0003
-#define PCM_LR_OUT_LOCAL 0x0000
-#define PCM_LR_OUT_REMOTE 0x0004
-#define PCM_LR_OUT_MUTE 0x0008
-#define PCM_LR_OUT_BOTH 0x000C
-#define LINE1_DAC_OUT_LOCAL 0x0000
-#define LINE1_DAC_OUT_REMOTE 0x0010
-#define LINE1_DAC_OUT_MUTE 0x0020
-#define LINE1_DAC_OUT_BOTH 0x0030
-#define PCM_CLS_OUT_LOCAL 0x0000
-#define PCM_CLS_OUT_REMOTE 0x0040
-#define PCM_CLS_OUT_MUTE 0x0080
-#define PCM_CLS_OUT_BOTH 0x00C0
-#define PCM_RLF_OUT_LOCAL 0x0000
-#define PCM_RLF_OUT_REMOTE 0x0100
-#define PCM_RLF_OUT_MUTE 0x0200
-#define PCM_RLF_OUT_BOTH 0x0300
-#define LINE2_DAC_OUT_LOCAL 0x0000
-#define LINE2_DAC_OUT_REMOTE 0x0400
-#define LINE2_DAC_OUT_MUTE 0x0800
-#define LINE2_DAC_OUT_BOTH 0x0C00
-#define HANDSET_OUT_LOCAL 0x0000
-#define HANDSET_OUT_REMOTE 0x1000
-#define HANDSET_OUT_MUTE 0x2000
-#define HANDSET_OUT_BOTH 0x3000
-#define IO_CTRL_OUT_LOCAL 0x0000
-#define IO_CTRL_OUT_REMOTE 0x4000
-#define IO_CTRL_OUT_MUTE 0x8000
-#define IO_CTRL_OUT_BOTH 0xC000
-
-#define SDO_IN_DEST_CTRL 0x3C
-#define STATUS_ADDR_IN 0x0003
-#define PCM_LR_IN_LOCAL 0x0000
-#define PCM_LR_IN_REMOTE 0x0004
-#define PCM_LR_RESERVED 0x0008
-#define PCM_LR_IN_BOTH 0x000C
-#define LINE1_ADC_IN_LOCAL 0x0000
-#define LINE1_ADC_IN_REMOTE 0x0010
-#define LINE1_ADC_IN_MUTE 0x0020
-#define MIC_ADC_IN_LOCAL 0x0000
-#define MIC_ADC_IN_REMOTE 0x0040
-#define MIC_ADC_IN_MUTE 0x0080
-#define LINE2_DAC_IN_LOCAL 0x0000
-#define LINE2_DAC_IN_REMOTE 0x0400
-#define LINE2_DAC_IN_MUTE 0x0800
-#define HANDSET_IN_LOCAL 0x0000
-#define HANDSET_IN_REMOTE 0x1000
-#define HANDSET_IN_MUTE 0x2000
-#define IO_STATUS_IN_LOCAL 0x0000
-#define IO_STATUS_IN_REMOTE 0x4000
-
-#define SPDIF_IN_CTRL 0x3E
-#define SPDIF_IN_ENABLE 0x0001
-
-#define GPIO_DATA 0x60
-#define GPIO_DATA_MASK 0x0FFF
-#define GPIO_HV_STATUS 0x3000
-#define GPIO_PME_STATUS 0x4000
-
-#define GPIO_MASK 0x64
-#define GPIO_DIRECTION 0x68
-#define GPO_PRIMARY_AC97 0x0001
-#define GPI_LINEOUT_SENSE 0x0004
-#define GPO_SECONDARY_AC97 0x0008
-#define GPI_VOL_DOWN 0x0010
-#define GPI_VOL_UP 0x0020
-#define GPI_IIS_CLK 0x0040
-#define GPI_IIS_LRCLK 0x0080
-#define GPI_IIS_DATA 0x0100
-#define GPI_DOCKING_STATUS 0x0100
-#define GPI_HEADPHONE_SENSE 0x0200
-#define GPO_EXT_AMP_SHUTDOWN 0x1000
-
-/* M3 */
-#define GPO_M3_EXT_AMP_SHUTDN 0x0002
-
-#define ASSP_INDEX_PORT 0x80
-#define ASSP_MEMORY_PORT 0x82
-#define ASSP_DATA_PORT 0x84
-
-#define MPU401_DATA_PORT 0x98
-#define MPU401_STATUS_PORT 0x99
-
-#define CLK_MULT_DATA_PORT 0x9C
-
-#define ASSP_CONTROL_A 0xA2
-#define ASSP_0_WS_ENABLE 0x01
-#define ASSP_CTRL_A_RESERVED1 0x02
-#define ASSP_CTRL_A_RESERVED2 0x04
-#define ASSP_CLK_49MHZ_SELECT 0x08
-#define FAST_PLU_ENABLE 0x10
-#define ASSP_CTRL_A_RESERVED3 0x20
-#define DSP_CLK_36MHZ_SELECT 0x40
-
-#define ASSP_CONTROL_B 0xA4
-#define RESET_ASSP 0x00
-#define RUN_ASSP 0x01
-#define ENABLE_ASSP_CLOCK 0x00
-#define STOP_ASSP_CLOCK 0x10
-#define RESET_TOGGLE 0x40
-
-#define ASSP_CONTROL_C 0xA6
-#define ASSP_HOST_INT_ENABLE 0x01
-#define FM_ADDR_REMAP_DISABLE 0x02
-#define HOST_WRITE_PORT_ENABLE 0x08
-
-#define ASSP_HOST_INT_STATUS 0xAC
-#define DSP2HOST_REQ_PIORECORD 0x01
-#define DSP2HOST_REQ_I2SRATE 0x02
-#define DSP2HOST_REQ_TIMER 0x04
-
-/* AC97 registers */
-/* XXX fix this crap up */
-/*#define AC97_RESET 0x00*/
-
-#define AC97_VOL_MUTE_B 0x8000
-#define AC97_VOL_M 0x1F
-#define AC97_LEFT_VOL_S 8
-
-#define AC97_MASTER_VOL 0x02
-#define AC97_LINE_LEVEL_VOL 0x04
-#define AC97_MASTER_MONO_VOL 0x06
-#define AC97_PC_BEEP_VOL 0x0A
-#define AC97_PC_BEEP_VOL_M 0x0F
-#define AC97_SROUND_MASTER_VOL 0x38
-#define AC97_PC_BEEP_VOL_S 1
-
-/*#define AC97_PHONE_VOL 0x0C
-#define AC97_MIC_VOL 0x0E*/
-#define AC97_MIC_20DB_ENABLE 0x40
-
-/*#define AC97_LINEIN_VOL 0x10
-#define AC97_CD_VOL 0x12
-#define AC97_VIDEO_VOL 0x14
-#define AC97_AUX_VOL 0x16*/
-#define AC97_PCM_OUT_VOL 0x18
-/*#define AC97_RECORD_SELECT 0x1A*/
-#define AC97_RECORD_MIC 0x00
-#define AC97_RECORD_CD 0x01
-#define AC97_RECORD_VIDEO 0x02
-#define AC97_RECORD_AUX 0x03
-#define AC97_RECORD_MONO_MUX 0x02
-#define AC97_RECORD_DIGITAL 0x03
-#define AC97_RECORD_LINE 0x04
-#define AC97_RECORD_STEREO 0x05
-#define AC97_RECORD_MONO 0x06
-#define AC97_RECORD_PHONE 0x07
-
-/*#define AC97_RECORD_GAIN 0x1C*/
-#define AC97_RECORD_VOL_M 0x0F
-
-/*#define AC97_GENERAL_PURPOSE 0x20*/
-#define AC97_POWER_DOWN_CTRL 0x26
-#define AC97_ADC_READY 0x0001
-#define AC97_DAC_READY 0x0002
-#define AC97_ANALOG_READY 0x0004
-#define AC97_VREF_ON 0x0008
-#define AC97_PR0 0x0100
-#define AC97_PR1 0x0200
-#define AC97_PR2 0x0400
-#define AC97_PR3 0x0800
-#define AC97_PR4 0x1000
-
-#define AC97_RESERVED1 0x28
-
-#define AC97_VENDOR_TEST 0x5A
-
-#define AC97_CLOCK_DELAY 0x5C
-#define AC97_LINEOUT_MUX_SEL 0x0001
-#define AC97_MONO_MUX_SEL 0x0002
-#define AC97_CLOCK_DELAY_SEL 0x1F
-#define AC97_DAC_CDS_SHIFT 6
-#define AC97_ADC_CDS_SHIFT 11
-
-#define AC97_MULTI_CHANNEL_SEL 0x74
-
-/*#define AC97_VENDOR_ID1 0x7C
-#define AC97_VENDOR_ID2 0x7E*/
-
-/*
- * ASSP control regs
- */
-#define DSP_PORT_TIMER_COUNT 0x06
-
-#define DSP_PORT_MEMORY_INDEX 0x80
-
-#define DSP_PORT_MEMORY_TYPE 0x82
-#define MEMTYPE_INTERNAL_CODE 0x0002
-#define MEMTYPE_INTERNAL_DATA 0x0003
-#define MEMTYPE_MASK 0x0003
-
-#define DSP_PORT_MEMORY_DATA 0x84
-
-#define DSP_PORT_CONTROL_REG_A 0xA2
-#define DSP_PORT_CONTROL_REG_B 0xA4
-#define DSP_PORT_CONTROL_REG_C 0xA6
-
-#define REV_A_CODE_MEMORY_BEGIN 0x0000
-#define REV_A_CODE_MEMORY_END 0x0FFF
-#define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
-#define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
-
-#define REV_B_CODE_MEMORY_BEGIN 0x0000
-#define REV_B_CODE_MEMORY_END 0x0BFF
-#define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
-#define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
-
-#define REV_A_DATA_MEMORY_BEGIN 0x1000
-#define REV_A_DATA_MEMORY_END 0x2FFF
-#define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
-#define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
-
-#define REV_B_DATA_MEMORY_BEGIN 0x1000
-#define REV_B_DATA_MEMORY_END 0x2BFF
-#define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
-#define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
-
-
-#define NUM_UNITS_KERNEL_CODE 16
-#define NUM_UNITS_KERNEL_DATA 2
-
-#define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
-#define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
-
-/*
- * Kernel data layout
- */
-
-#define DP_SHIFT_COUNT 7
-
-#define KDATA_BASE_ADDR 0x1000
-#define KDATA_BASE_ADDR2 0x1080
-
-#define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
-#define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
-#define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
-#define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
-#define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
-#define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
-#define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
-#define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
-#define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
-
-#define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
-#define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
-
-#define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
-#define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
-#define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
-#define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
-#define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
-#define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
-#define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
-#define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
-#define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
-#define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
-
-#define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
-#define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
-
-#define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
-#define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
-
-#define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
-#define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
-
-#define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
-#define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
-#define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
-
-#define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
-#define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
-#define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
-#define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
-#define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
-
-#define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
-#define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
-#define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
-
-#define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
-#define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
-#define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
-
-#define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
-#define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
-#define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
-#define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
-#define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
-#define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
-#define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
-#define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
-#define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
-#define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
-
-#define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
-#define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
-#define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
-
-#define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
-#define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
-
-#define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
-#define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
-#define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
-
-#define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
-#define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
-#define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
-#define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
-#define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
-#define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
-
-#define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
-#define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
-#define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
-#define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
-#define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
-#define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
-
-#define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
-#define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
-#define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
-#define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
-#define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
-#define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
-
-#define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
-#define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
-#define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
-#define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
-
-#define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
-#define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
-
-#define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
-#define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
-
-#define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
-#define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
-#define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
-#define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
-#define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
-
-#define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
-#define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
-
-#define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
-#define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
-#define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
-
-#define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
-#define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
-
-#define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
-
-#define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
-#define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
-#define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
-#define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
-#define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
-#define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
-#define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
-#define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
-#define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
-#define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
-#define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
-#define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
-
-#define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
-#define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
-#define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
-#define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
-
-#define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
-#define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
-
-#define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
-#define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
-#define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
-#define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
-
-#define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
-#define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
-#define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
-#define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
-#define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
-
-/*
- * second 'segment' (?) reserved for mixer
- * buffers..
- */
-
-#define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
-#define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
-#define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
-#define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
-#define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
-#define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
-#define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
-#define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
-#define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
-#define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
-#define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
-#define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
-#define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
-#define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
-#define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
-#define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
-
-#define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
-#define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
-#define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
-#define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
-#define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
-#define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
-#define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
-#define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
-#define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
-#define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
-#define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
-
-#define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
-#define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
-#define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
-#define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
-#define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
-#define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
-
-#define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
-#define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
-#define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
-#define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
-
-/*
- * client data area offsets
- */
-#define CDATA_INSTANCE_READY 0x00
-
-#define CDATA_HOST_SRC_ADDRL 0x01
-#define CDATA_HOST_SRC_ADDRH 0x02
-#define CDATA_HOST_SRC_END_PLUS_1L 0x03
-#define CDATA_HOST_SRC_END_PLUS_1H 0x04
-#define CDATA_HOST_SRC_CURRENTL 0x05
-#define CDATA_HOST_SRC_CURRENTH 0x06
-
-#define CDATA_IN_BUF_CONNECT 0x07
-#define CDATA_OUT_BUF_CONNECT 0x08
-
-#define CDATA_IN_BUF_BEGIN 0x09
-#define CDATA_IN_BUF_END_PLUS_1 0x0A
-#define CDATA_IN_BUF_HEAD 0x0B
-#define CDATA_IN_BUF_TAIL 0x0C
-#define CDATA_OUT_BUF_BEGIN 0x0D
-#define CDATA_OUT_BUF_END_PLUS_1 0x0E
-#define CDATA_OUT_BUF_HEAD 0x0F
-#define CDATA_OUT_BUF_TAIL 0x10
-
-#define CDATA_DMA_CONTROL 0x11
-#define CDATA_RESERVED 0x12
-
-#define CDATA_FREQUENCY 0x13
-#define CDATA_LEFT_VOLUME 0x14
-#define CDATA_RIGHT_VOLUME 0x15
-#define CDATA_LEFT_SUR_VOL 0x16
-#define CDATA_RIGHT_SUR_VOL 0x17
-
-#define CDATA_HEADER_LEN 0x18
-
-#define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
-#define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1)
-#define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2)
-#define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3)
-#define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8)
-#define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10)
-#define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16)
-#define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17)
-
-#define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
-#define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
-#define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
-#define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
-#define MINISRC_BIQUAD_STAGE 2
-#define MINISRC_COEF_LOC 0X175
-
-#define DMACONTROL_BLOCK_MASK 0x000F
-#define DMAC_BLOCK0_SELECTOR 0x0000
-#define DMAC_BLOCK1_SELECTOR 0x0001
-#define DMAC_BLOCK2_SELECTOR 0x0002
-#define DMAC_BLOCK3_SELECTOR 0x0003
-#define DMAC_BLOCK4_SELECTOR 0x0004
-#define DMAC_BLOCK5_SELECTOR 0x0005
-#define DMAC_BLOCK6_SELECTOR 0x0006
-#define DMAC_BLOCK7_SELECTOR 0x0007
-#define DMAC_BLOCK8_SELECTOR 0x0008
-#define DMAC_BLOCK9_SELECTOR 0x0009
-#define DMAC_BLOCKA_SELECTOR 0x000A
-#define DMAC_BLOCKB_SELECTOR 0x000B
-#define DMAC_BLOCKC_SELECTOR 0x000C
-#define DMAC_BLOCKD_SELECTOR 0x000D
-#define DMAC_BLOCKE_SELECTOR 0x000E
-#define DMAC_BLOCKF_SELECTOR 0x000F
-#define DMACONTROL_PAGE_MASK 0x00F0
-#define DMAC_PAGE0_SELECTOR 0x0030
-#define DMAC_PAGE1_SELECTOR 0x0020
-#define DMAC_PAGE2_SELECTOR 0x0010
-#define DMAC_PAGE3_SELECTOR 0x0000
-#define DMACONTROL_AUTOREPEAT 0x1000
-#define DMACONTROL_STOPPED 0x2000
-#define DMACONTROL_DIRECTION 0x0100
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