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authorbz <bz@FreeBSD.org>2014-03-22 13:06:32 +0000
committerbz <bz@FreeBSD.org>2014-03-22 13:06:32 +0000
commit260ba47599729a7cb2f104c437c909e8109aa2d2 (patch)
tree7fb69f71e51c3eb12815254713cc5d238b934626 /sys/fs/udf/ecma167-udf.h
parent3bc7f167e052261843a975e4e487fa9da3647a87 (diff)
downloadFreeBSD-src-260ba47599729a7cb2f104c437c909e8109aa2d2.zip
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For BERI on NetFPGA assume HZ=100 by default.
Remove the uart support in favour of a "jtag-uart" interface imitation providing a much simpler interface, directly exported to the host, allowing the toolchain to be shared with BERI on Altera. [1] Submitted by: Jong Hun HAN (jong.han cl.cam.ac.uk) [1] MFC after: 2 weeks
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