diff options
| author | eadler <eadler@FreeBSD.org> | 2014-02-04 03:36:42 +0000 |
|---|---|---|
| committer | eadler <eadler@FreeBSD.org> | 2014-02-04 03:36:42 +0000 |
| commit | ec294fd7f5fc5de11ed889d6c2d701f918d1ecfb (patch) | |
| tree | 7e76e370b9406b0383b17bd343084addb4ad6a25 /sys/dev | |
| parent | d374d7f398b846dc59d8a5ec3c7bfb318cf880af (diff) | |
| download | FreeBSD-src-ec294fd7f5fc5de11ed889d6c2d701f918d1ecfb.zip FreeBSD-src-ec294fd7f5fc5de11ed889d6c2d701f918d1ecfb.tar.gz | |
MFC r258779,r258780,r258787,r258822:
Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this
shifts into the sign bit. Instead use (1U << 31) which gets the
expected result.
Similar to the (1 << 31) case it is not defined to do (2 << 30).
This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.
A similar change was made in OpenBSD.
Diffstat (limited to 'sys/dev')
65 files changed, 467 insertions, 252 deletions
diff --git a/sys/dev/aac/aacvar.h b/sys/dev/aac/aacvar.h index 0950a2f..bcedff5 100644 --- a/sys/dev/aac/aacvar.h +++ b/sys/dev/aac/aacvar.h @@ -412,7 +412,7 @@ struct aac_softc #define AAC_FLAGS_RAW_IO (1 << 12) /* Raw I/O interface */ #define AAC_FLAGS_ARRAY_64BIT (1 << 13) /* 64-bit array size */ #define AAC_FLAGS_LBA_64BIT (1 << 14) /* 64-bit LBA support */ -#define AAC_FLAGS_NOMSI (1 << 31) /* Broken MSI */ +#define AAC_FLAGS_NOMSI (1U << 31) /* Broken MSI */ u_int32_t supported_options; u_int32_t scsi_method_id; diff --git a/sys/dev/acpica/acpi_video.c b/sys/dev/acpica/acpi_video.c index cda45db..5b9e526 100644 --- a/sys/dev/acpica/acpi_video.c +++ b/sys/dev/acpica/acpi_video.c @@ -132,7 +132,7 @@ static void vo_set_device_state(ACPI_HANDLE, UINT32); #define DOD_HEAD_ID_BITS 3 #define DOD_HEAD_ID_MASK \ (((1 << DOD_HEAD_ID_BITS) - 1) << DOD_HEAD_ID_SHIFT) -#define DOD_DEVID_SCHEME_STD (1 << 31) +#define DOD_DEVID_SCHEME_STD (1U << 31) /* _BCL related constants */ #define BCL_FULLPOWER 0 @@ -149,7 +149,7 @@ static void vo_set_device_state(ACPI_HANDLE, UINT32); #define DSS_INACTIVE 0 #define DSS_ACTIVE (1 << 0) #define DSS_SETNEXT (1 << 30) -#define DSS_COMMIT (1 << 31) +#define DSS_COMMIT (1U << 31) static device_method_t acpi_video_methods[] = { DEVMETHOD(device_identify, acpi_video_identify), diff --git a/sys/dev/agp/agp_i810.c b/sys/dev/agp/agp_i810.c index 414a7a5..725aa99 100644 --- a/sys/dev/agp/agp_i810.c +++ b/sys/dev/agp/agp_i810.c @@ -2226,10 +2226,10 @@ agp_i830_chipset_flush(device_t dev) sc = device_get_softc(dev); pmap_invalidate_cache(); hic = bus_read_4(sc->sc_res[0], AGP_I830_HIC); - bus_write_4(sc->sc_res[0], AGP_I830_HIC, hic | (1 << 31)); + bus_write_4(sc->sc_res[0], AGP_I830_HIC, hic | (1U << 31)); for (i = 0; i < 20000 /* 1 sec */; i++) { hic = bus_read_4(sc->sc_res[0], AGP_I830_HIC); - if ((hic & (1 << 31)) == 0) + if ((hic & (1U << 31)) == 0) break; DELAY(50); } diff --git a/sys/dev/ahci/ahci.h b/sys/dev/ahci/ahci.h index e1895e4..7da30db 100644 --- a/sys/dev/ahci/ahci.h +++ b/sys/dev/ahci/ahci.h @@ -321,7 +321,7 @@ struct ahci_dma_prd { u_int32_t dbc; /* 0 based */ #define AHCI_PRD_MASK 0x003fffff /* max 4MB */ #define AHCI_PRD_MAX (AHCI_PRD_MASK + 1) -#define AHCI_PRD_IPC (1 << 31) +#define AHCI_PRD_IPC (1U << 31) } __packed; struct ahci_cmd_tab { diff --git a/sys/dev/bktr/bktr_core.c b/sys/dev/bktr/bktr_core.c index bb2ae33..c38afe5 100644 --- a/sys/dev/bktr/bktr_core.c +++ b/sys/dev/bktr/bktr_core.c @@ -2599,7 +2599,7 @@ dump_bt848( bktr_ptr_t bktr ) #define BKTR_TEST_RISC_STATUS_BIT0 (1 << 28) #define BKTR_TEST_RISC_STATUS_BIT1 (1 << 29) #define BKTR_TEST_RISC_STATUS_BIT2 (1 << 30) -#define BKTR_TEST_RISC_STATUS_BIT3 (1 << 31) +#define BKTR_TEST_RISC_STATUS_BIT3 (1U << 31) static bool_t notclipped (bktr_reg_t * bktr, int x, int width) { int i; diff --git a/sys/dev/cesa/cesa.h b/sys/dev/cesa/cesa.h index 7bf2ff5..28536d5 100644 --- a/sys/dev/cesa/cesa.h +++ b/sys/dev/cesa/cesa.h @@ -297,8 +297,8 @@ struct cesa_chain_info { #define CESA_CSH_AES_KLEN_MASK (3 << 24) #define CESA_CSHD_FRAG_FIRST (1 << 30) -#define CESA_CSHD_FRAG_LAST (2 << 30) -#define CESA_CSHD_FRAG_MIDDLE (3 << 30) +#define CESA_CSHD_FRAG_LAST (2U << 30) +#define CESA_CSHD_FRAG_MIDDLE (3U << 30) /* CESA registers definitions */ #define CESA_ICR 0xDE20 diff --git a/sys/dev/drm/i915_reg.h b/sys/dev/drm/i915_reg.h index fce9992..0e2ff21 100644 --- a/sys/dev/drm/i915_reg.h +++ b/sys/dev/drm/i915_reg.h @@ -349,7 +349,7 @@ __FBSDID("$FreeBSD$"); #define VGA1_PD_P1_MASK (0x1f << 8) #define DPLL_A 0x06014 #define DPLL_B 0x06018 -#define DPLL_VCO_ENABLE (1 << 31) +#define DPLL_VCO_ENABLE (1U << 31) #define DPLL_DVO_HIGH_SPEED (1 << 30) #define DPLL_SYNCLOCK_ENABLE (1 << 29) #define DPLL_VGA_MODE_DIS (1 << 28) @@ -653,7 +653,7 @@ __FBSDID("$FreeBSD$"); /* SDVO port control */ #define SDVOB 0x61140 #define SDVOC 0x61160 -#define SDVO_ENABLE (1 << 31) +#define SDVO_ENABLE (1U << 31) #define SDVO_PIPE_B_SELECT (1 << 30) #define SDVO_STALL_SELECT (1 << 29) #define SDVO_INTERRUPT_ENABLE (1 << 26) @@ -690,7 +690,7 @@ __FBSDID("$FreeBSD$"); #define DVOA 0x61120 #define DVOB 0x61140 #define DVOC 0x61160 -#define DVO_ENABLE (1 << 31) +#define DVO_ENABLE (1U << 31) #define DVO_PIPE_B_SELECT (1 << 30) #define DVO_PIPE_STALL_UNUSED (0 << 28) #define DVO_PIPE_STALL (1 << 28) @@ -726,7 +726,7 @@ __FBSDID("$FreeBSD$"); * Enables the LVDS port. This bit must be set before DPLLs are enabled, as * the DPLL semantics change when the LVDS is assigned to that pipe. */ -#define LVDS_PORT_EN (1 << 31) +#define LVDS_PORT_EN (1U << 31) /* Selects pipe B for LVDS data. Must be set on pre-965. */ #define LVDS_PIPEB_SELECT (1 << 30) /* @@ -762,7 +762,7 @@ __FBSDID("$FreeBSD$"); /* Panel power sequencing */ #define PP_STATUS 0x61200 -#define PP_ON (1 << 31) +#define PP_ON (1U << 31) /* * Indicates that all dependencies of the panel are on: * @@ -783,7 +783,7 @@ __FBSDID("$FreeBSD$"); /* Panel fitting */ #define PFIT_CONTROL 0x61230 -#define PFIT_ENABLE (1 << 31) +#define PFIT_ENABLE (1U << 31) #define PFIT_PIPE_MASK (3 << 29) #define PFIT_PIPE_SHIFT 29 #define VERT_INTERP_DISABLE (0 << 10) @@ -826,7 +826,7 @@ __FBSDID("$FreeBSD$"); /* TV port control */ #define TV_CTL 0x68000 /** Enables the TV encoder */ -# define TV_ENC_ENABLE (1 << 31) +# define TV_ENC_ENABLE (1U << 31) /** Sources the TV encoder input from pipe B instead of A. */ # define TV_ENC_PIPEB_SELECT (1 << 30) /** Outputs composite video (DAC A only) */ @@ -897,7 +897,7 @@ __FBSDID("$FreeBSD$"); * * This gets cleared when TV_DAC_STATE_EN is cleared */ -# define TVDAC_STATE_CHG (1 << 31) +# define TVDAC_STATE_CHG (1U << 31) # define TVDAC_SENSE_MASK (7 << 28) /** Reports that DAC A voltage is above the detect threshold */ # define TVDAC_A_SENSE (1 << 30) @@ -1024,7 +1024,7 @@ __FBSDID("$FreeBSD$"); #define TV_H_CTL_2 0x68034 /** Enables the colorburst (needed for non-component color) */ -# define TV_BURST_ENA (1 << 31) +# define TV_BURST_ENA (1U << 31) /** Offset of the colorburst from the start of hsync, in pixels minus one. */ # define TV_HBURST_START_SHIFT 16 # define TV_HBURST_START_MASK 0x1fff0000 @@ -1069,7 +1069,7 @@ __FBSDID("$FreeBSD$"); #define TV_V_CTL_3 0x68044 /** Enables generation of the equalization signal */ -# define TV_EQUAL_ENA (1 << 31) +# define TV_EQUAL_ENA (1U << 31) /** Length of vsync, in half lines */ # define TV_VEQ_LEN_MASK 0x007f0000 # define TV_VEQ_LEN_SHIFT 16 @@ -1143,7 +1143,7 @@ __FBSDID("$FreeBSD$"); #define TV_SC_CTL_1 0x68060 /** Turns on the first subcarrier phase generation DDA */ -# define TV_SC_DDA1_EN (1 << 31) +# define TV_SC_DDA1_EN (1U << 31) /** Turns on the first subcarrier phase generation DDA */ # define TV_SC_DDA2_EN (1 << 30) /** Turns on the first subcarrier phase generation DDA */ @@ -1206,7 +1206,7 @@ __FBSDID("$FreeBSD$"); * If set, the rest of the registers are ignored, and the calculated values can * be read back from the register. */ -# define TV_AUTO_SCALE (1 << 31) +# define TV_AUTO_SCALE (1U << 31) /** * Disables the vertical filter. * @@ -1269,7 +1269,7 @@ __FBSDID("$FreeBSD$"); # define TV_VSCALE_IP_FRAC_SHIFT 0 #define TV_CC_CONTROL 0x68090 -# define TV_CC_ENABLE (1 << 31) +# define TV_CC_ENABLE (1U << 31) /** * Specifies which field to send the CC data in. * @@ -1285,7 +1285,7 @@ __FBSDID("$FreeBSD$"); # define TV_CC_LINE_SHIFT 0 #define TV_CC_DATA 0x68094 -# define TV_CC_RDY (1 << 31) +# define TV_CC_RDY (1U << 31) /** Second word of CC data to be transmitted. */ # define TV_CC_DATA_2_MASK 0x007f0000 # define TV_CC_DATA_2_SHIFT 16 @@ -1469,7 +1469,7 @@ __FBSDID("$FreeBSD$"); /* VBIOS regs */ #define VGACNTRL 0x71400 -# define VGA_DISP_DISABLE (1 << 31) +# define VGA_DISP_DISABLE (1U << 31) # define VGA_2X_MODE (1 << 30) # define VGA_PIPE_B_SELECT (1 << 29) diff --git a/sys/dev/drm/mach64_drv.h b/sys/dev/drm/mach64_drv.h index 7d68c46..14c590e 100644 --- a/sys/dev/drm/mach64_drv.h +++ b/sys/dev/drm/mach64_drv.h @@ -202,7 +202,7 @@ extern void mach64_driver_irq_uninstall(struct drm_device *dev); # define MACH64_CIRCULAR_BUF_SIZE_32KB (1 << 0) # define MACH64_CIRCULAR_BUF_SIZE_64KB (2 << 0) # define MACH64_CIRCULAR_BUF_SIZE_128KB (3 << 0) -# define MACH64_LAST_DESCRIPTOR (1 << 31) +# define MACH64_LAST_DESCRIPTOR (1U << 31) #define MACH64_BM_HOSTDATA 0x0644 #define MACH64_BM_STATUS 0x018c #define MACH64_BM_SYSTEM_MEM_ADDR 0x0184 @@ -316,7 +316,7 @@ extern void mach64_driver_irq_uninstall(struct drm_device *dev); #define MACH64_FIFO_STAT 0x0710 # define MACH64_FIFO_SLOT_MASK 0x0000ffff -# define MACH64_FIFO_ERR (1 << 31) +# define MACH64_FIFO_ERR (1U << 31) #define MACH64_GEN_TEST_CNTL 0x04d0 # define MACH64_GUI_ENGINE_ENABLE (1 << 8) @@ -442,7 +442,7 @@ extern void mach64_driver_irq_uninstall(struct drm_device *dev); # define MACH64_CRTC2_VLINE_SYNC (1 << 28) /* LT Pro */ /* 0=even, 1=odd */ # define MACH64_CRTC_SNAPSHOT2_INT_EN (1 << 29) /* LT Pro */ # define MACH64_CRTC_SNAPSHOT2_INT (1 << 30) /* LT Pro */ -# define MACH64_CRTC_VBLANK2_INT (1 << 31) +# define MACH64_CRTC_VBLANK2_INT (1U << 31) # define MACH64_CRTC_INT_ENS \ ( \ MACH64_CRTC_VBLANK_INT_EN | \ diff --git a/sys/dev/drm/mga_drv.h b/sys/dev/drm/mga_drv.h index 01c5c9d..52a7baf 100644 --- a/sys/dev/drm/mga_drv.h +++ b/sys/dev/drm/mga_drv.h @@ -458,7 +458,7 @@ do { \ # define MGA_BLTMOD_BU24RGB (15 << 25) # define MGA_PATTERN (1 << 29) # define MGA_TRANSC (1 << 30) -# define MGA_CLIPDIS (1 << 31) +# define MGA_CLIPDIS (1U << 31) #define MGA_DWGSYNC 0x2c4c #define MGA_FCOL 0x1c24 @@ -526,7 +526,7 @@ do { \ #define MGA_TEXCTL2 0x2c3c # define MGA_DUALTEX (1 << 7) # define MGA_G400_TC2_MAGIC (1 << 15) -# define MGA_MAP1_ENABLE (1 << 31) +# define MGA_MAP1_ENABLE (1U << 31) #define MGA_TEXFILTER 0x2c58 #define MGA_TEXHEIGHT 0x2c2c #define MGA_TEXORG 0x2c24 diff --git a/sys/dev/drm/r128_drv.h b/sys/dev/drm/r128_drv.h index ee7d8f9..7ad3496 100644 --- a/sys/dev/drm/r128_drv.h +++ b/sys/dev/drm/r128_drv.h @@ -227,7 +227,7 @@ extern long r128_compat_ioctl(struct file *filp, unsigned int cmd, # define R128_ROP3_P 0x00f00000 #define R128_DP_WRITE_MASK 0x16cc #define R128_DST_PITCH_OFFSET_C 0x1c80 -# define R128_DST_TILE (1 << 31) +# define R128_DST_TILE (1U << 31) #define R128_GEN_INT_CNTL 0x0040 # define R128_CRTC_VBLANK_INT_EN (1 << 0) @@ -246,7 +246,7 @@ extern long r128_compat_ioctl(struct file *filp, unsigned int cmd, #define R128_GUI_STAT 0x1740 # define R128_GUI_FIFOCNT_MASK 0x0fff -# define R128_GUI_ACTIVE (1 << 31) +# define R128_GUI_ACTIVE (1U << 31) #define R128_MCLK_CNTL 0x000f # define R128_FORCE_GCP (1 << 16) @@ -258,7 +258,7 @@ extern long r128_compat_ioctl(struct file *filp, unsigned int cmd, # define R128_PC_FLUSH_GUI (3 << 0) # define R128_PC_RI_GUI (1 << 2) # define R128_PC_FLUSH_ALL 0x00ff -# define R128_PC_BUSY (1 << 31) +# define R128_PC_BUSY (1U << 31) #define R128_PCI_GART_PAGE 0x017c #define R128_PRIM_TEX_CNTL_C 0x1cb0 @@ -302,7 +302,7 @@ extern long r128_compat_ioctl(struct file *filp, unsigned int cmd, #define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c #define R128_PM4_BUFFER_DL_RPTR 0x0710 #define R128_PM4_BUFFER_DL_WPTR 0x0714 -# define R128_PM4_BUFFER_DL_DONE (1 << 31) +# define R128_PM4_BUFFER_DL_DONE (1U << 31) #define R128_PM4_VC_FPU_SETUP 0x071c @@ -312,7 +312,7 @@ extern long r128_compat_ioctl(struct file *filp, unsigned int cmd, #define R128_PM4_STAT 0x07b8 # define R128_PM4_FIFOCNT_MASK 0x0fff # define R128_PM4_BUSY (1 << 16) -# define R128_PM4_GUI_ACTIVE (1 << 31) +# define R128_PM4_GUI_ACTIVE (1U << 31) #define R128_PM4_MICROCODE_ADDR 0x07d4 #define R128_PM4_MICROCODE_RADDR 0x07d8 diff --git a/sys/dev/drm/r300_reg.h b/sys/dev/drm/r300_reg.h index 6df4611..0508771 100644 --- a/sys/dev/drm/r300_reg.h +++ b/sys/dev/drm/r300_reg.h @@ -1205,7 +1205,7 @@ __FBSDID("$FreeBSD$"); # define R300_FPI0_OUTC_FRC (9 << 23) # define R300_FPI0_OUTC_REPL_ALPHA (10 << 23) # define R300_FPI0_OUTC_SAT (1 << 30) -# define R300_FPI0_INSERT_NOP (1 << 31) +# define R300_FPI0_INSERT_NOP (1U << 31) #define R300_PFS_INSTR2_0 0x49C0 # define R300_FPI2_ARGA_SRC0C_X 0 @@ -1252,7 +1252,7 @@ __FBSDID("$FreeBSD$"); # define R300_FPI2_OUTA_RCP (10 << 23) # define R300_FPI2_OUTA_RSQ (11 << 23) # define R300_FPI2_OUTA_SAT (1 << 30) -# define R300_FPI2_UNKNOWN_31 (1 << 31) +# define R300_FPI2_UNKNOWN_31 (1U << 31) /* END: Fragment program instruction set */ /* Fog state and color */ @@ -1452,7 +1452,7 @@ __FBSDID("$FreeBSD$"); # define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1) # define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1) # define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31) -# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31) +# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1U << 31) #define R300_ZB_BW_CNTL 0x4f1c # define R300_HIZ_DISABLE (0 << 0) diff --git a/sys/dev/drm/r600_blit.c b/sys/dev/drm/r600_blit.c index d3c41ae..f6097ee 100644 --- a/sys/dev/drm/r600_blit.c +++ b/sys/dev/drm/r600_blit.c @@ -1428,12 +1428,12 @@ set_scissors(drm_radeon_private_t *dev_priv, int x1, int y1, int x2, int y2) OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2)); OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2); - OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31)); + OUT_RING((x1 << 0) | (y1 << 16) | (1U << 31)); OUT_RING((x2 << 0) | (y2 << 16)); OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2)); OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2); - OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31)); + OUT_RING((x1 << 0) | (y1 << 16) | (1U << 31)); OUT_RING((x2 << 0) | (y2 << 16)); ADVANCE_RING(); } diff --git a/sys/dev/drm/radeon_cp.c b/sys/dev/drm/radeon_cp.c index 0a486af..5d2f4c7 100644 --- a/sys/dev/drm/radeon_cp.c +++ b/sys/dev/drm/radeon_cp.c @@ -542,7 +542,7 @@ static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv) #if 0 u32 tmp; - tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); + tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1U << 31); RADEON_WRITE(RADEON_CP_RB_WPTR, tmp); #endif } diff --git a/sys/dev/drm/radeon_drv.h b/sys/dev/drm/radeon_drv.h index d90d7cf..e830a83 100644 --- a/sys/dev/drm/radeon_drv.h +++ b/sys/dev/drm/radeon_drv.h @@ -659,7 +659,7 @@ extern int r600_cs_init(struct drm_device *dev); # define RS480_GTW_LAC_EN (1 << 25) # define RS480_2LEVEL_GART (0 << 30) # define RS480_1LEVEL_GART (1 << 30) -# define RS480_PDC_EN (1 << 31) +# define RS480_PDC_EN (1U << 31) #define RS480_GART_BASE 0x2c #define RS480_GART_CACHE_CNTRL 0x2e # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ @@ -775,7 +775,7 @@ extern int r600_cs_init(struct drm_device *dev); # define R300_SUBPIXEL_1_12 (0 << 16) # define R300_SUBPIXEL_1_16 (1 << 16) #define R300_DST_PIPE_CONFIG 0x170c -# define R300_PIPE_AUTO_CONFIG (1 << 31) +# define R300_PIPE_AUTO_CONFIG (1U << 31) #define R300_RB2D_DSTCACHE_MODE 0x3428 # define R300_DC_AUTOFLUSH_ENABLE (1 << 8) # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) @@ -807,8 +807,8 @@ extern int r600_cs_init(struct drm_device *dev); #define RADEON_DST_PITCH_OFFSET_C 0x1c80 # define RADEON_DST_TILE_LINEAR (0 << 30) # define RADEON_DST_TILE_MACRO (1 << 30) -# define RADEON_DST_TILE_MICRO (2 << 30) -# define RADEON_DST_TILE_BOTH (3 << 30) +# define RADEON_DST_TILE_MICRO (2U << 30) +# define RADEON_DST_TILE_BOTH (3U << 30) #define RADEON_SCRATCH_REG0 0x15e0 #define RADEON_SCRATCH_REG1 0x15e4 @@ -902,7 +902,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); # define R300_RB2D_DC_FLUSH (3 << 0) # define R300_RB2D_DC_FREE (3 << 2) # define R300_RB2D_DC_FLUSH_ALL 0xf -# define R300_RB2D_DC_BUSY (1 << 31) +# define R300_RB2D_DC_BUSY (1U << 31) #define RADEON_RB3D_CNTL 0x1c3c # define RADEON_ALPHA_BLEND_ENABLE (1 << 0) # define RADEON_PLANE_MASK_ENABLE (1 << 1) @@ -924,16 +924,16 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); # define RADEON_RB3D_ZC_FLUSH (1 << 0) # define RADEON_RB3D_ZC_FREE (1 << 2) # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 -# define RADEON_RB3D_ZC_BUSY (1 << 31) +# define RADEON_RB3D_ZC_BUSY (1U << 31) #define R300_ZB_ZCACHE_CTLSTAT 0x4f18 # define R300_ZC_FLUSH (1 << 0) # define R300_ZC_FREE (1 << 1) -# define R300_ZC_BUSY (1 << 31) +# define R300_ZC_BUSY (1U << 31) #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c # define RADEON_RB3D_DC_FLUSH (3 << 0) # define RADEON_RB3D_DC_FREE (3 << 2) # define RADEON_RB3D_DC_FLUSH_ALL 0xf -# define RADEON_RB3D_DC_BUSY (1 << 31) +# define RADEON_RB3D_DC_BUSY (1U << 31) #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c # define R300_RB3D_DC_FLUSH (2 << 0) # define R300_RB3D_DC_FREE (2 << 2) @@ -949,7 +949,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); # define RADEON_Z_COMPRESSION_ENABLE (1 << 28) # define RADEON_FORCE_Z_DIRTY (1 << 29) # define RADEON_Z_WRITE_ENABLE (1 << 30) -# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) +# define RADEON_Z_DECOMPRESSION_ENABLE (1U << 31) #define RADEON_RBBM_SOFT_RESET 0x00f0 # define RADEON_SOFT_RESET_CP (1 << 0) # define RADEON_SOFT_RESET_HI (1 << 1) @@ -1003,7 +1003,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); # define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */ # define RADEON_GA_BUSY (1 << 26) # define RADEON_CBA2D_BUSY (1 << 27) -# define RADEON_RBBM_ACTIVE (1 << 31) +# define RADEON_RBBM_ACTIVE (1U << 31) #define RADEON_RE_LINE_PATTERN 0x1cd0 #define RADEON_RE_MISC 0x26c4 #define RADEON_RE_TOP_LEFT 0x26c0 @@ -1117,7 +1117,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); #define RADEON_CP_RB_CNTL 0x0704 # define RADEON_BUF_SWAP_32BIT (2 << 16) # define RADEON_RB_NO_UPDATE (1 << 27) -# define RADEON_RB_RPTR_WR_ENA (1 << 31) +# define RADEON_RB_RPTR_WR_ENA (1U << 31) #define RADEON_CP_RB_RPTR_ADDR 0x070c #define RADEON_CP_RB_RPTR 0x0710 #define RADEON_CP_RB_WPTR 0x0714 @@ -1193,7 +1193,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 -#define RADEON_VTX_Z_PRESENT (1 << 31) +#define RADEON_VTX_Z_PRESENT (1U << 31) #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) #define RADEON_PRIM_TYPE_NONE (0 << 0) @@ -1524,7 +1524,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); #define R600_GRBM_STATUS 0x8010 # define R600_CMDFIFO_AVAIL_MASK 0x1f # define R700_CMDFIFO_AVAIL_MASK 0xf -# define R600_GUI_ACTIVE (1 << 31) +# define R600_GUI_ACTIVE (1U << 31) #define R600_GRBM_STATUS2 0x8014 #define R600_GRBM_SOFT_RESET 0x8020 # define R600_SOFT_RESET_CP (1 << 0) @@ -1546,7 +1546,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); # define R600_RB_BUFSZ(x) ((x) << 0) # define R600_RB_BLKSZ(x) ((x) << 8) # define R600_RB_NO_UPDATE (1 << 27) -# define R600_RB_RPTR_WR_ENA (1 << 31) +# define R600_RB_RPTR_WR_ENA (1U << 31) #define R600_CP_RB_RPTR_WR 0xc108 #define R600_CP_RB_RPTR_ADDR 0xc10c #define R600_CP_RB_RPTR_ADDR_HI 0xc110 @@ -1619,7 +1619,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); #define R600_SX_MISC 0x28350 #define R600_DB_DEBUG 0x9830 -# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) +# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1U << 31) #define R600_DB_WATERMARKS 0x9838 # define R600_DEPTH_FREE(x) ((x) << 0) # define R600_DEPTH_FLUSH(x) ((x) << 5) @@ -1679,7 +1679,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); # define R600_SYNC_WALKER (1 << 25) # define R600_SYNC_ALIGNER (1 << 26) # define R600_BILINEAR_PRECISION_6_BIT (0 << 31) -# define R600_BILINEAR_PRECISION_8_BIT (1 << 31) +# define R600_BILINEAR_PRECISION_8_BIT (1U << 31) #define R700_TCP_CNTL 0x9610 @@ -1753,7 +1753,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); # define R600_PERSP_GRADIENT_ENA (1 << 28) # define R600_LINEAR_GRADIENT_ENA (1 << 29) # define R600_POSITION_SAMPLE (1 << 30) -# define R600_BARYC_AT_SAMPLE_ENA (1 << 31) +# define R600_BARYC_AT_SAMPLE_ENA (1U << 31) #define R600_SPI_PS_IN_CONTROL_1 0x286d0 # define R600_GEN_INDEX_PIX (1 << 0) # define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1) diff --git a/sys/dev/drm/via_irq.c b/sys/dev/drm/via_irq.c index 20ec77a..0ebda40 100644 --- a/sys/dev/drm/via_irq.c +++ b/sys/dev/drm/via_irq.c @@ -46,7 +46,7 @@ __FBSDID("$FreeBSD$"); #define VIA_REG_INTERRUPT 0x200 /* VIA_REG_INTERRUPT */ -#define VIA_IRQ_GLOBAL (1 << 31) +#define VIA_IRQ_GLOBAL (1U << 31) #define VIA_IRQ_VBLANK_ENABLE (1 << 19) #define VIA_IRQ_VBLANK_PENDING (1 << 3) #define VIA_IRQ_HQV0_ENABLE (1 << 11) diff --git a/sys/dev/drm2/i915/i915_reg.h b/sys/dev/drm2/i915/i915_reg.h index 754e535..8cb6fba 100644 --- a/sys/dev/drm2/i915/i915_reg.h +++ b/sys/dev/drm2/i915/i915_reg.h @@ -798,7 +798,7 @@ __FBSDID("$FreeBSD$"); #define _DPLL_A 0x06014 #define _DPLL_B 0x06018 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) -#define DPLL_VCO_ENABLE (1 << 31) +#define DPLL_VCO_ENABLE (1U << 31) #define DPLL_DVO_HIGH_SPEED (1 << 30) #define DPLL_SYNCLOCK_ENABLE (1 << 29) #define DPLL_VGA_MODE_DIS (1 << 28) @@ -1483,7 +1483,7 @@ __FBSDID("$FreeBSD$"); /* SDVO port control */ #define SDVOB 0x61140 #define SDVOC 0x61160 -#define SDVO_ENABLE (1 << 31) +#define SDVO_ENABLE (1U << 31) #define SDVO_PIPE_B_SELECT (1 << 30) #define SDVO_STALL_SELECT (1 << 29) #define SDVO_INTERRUPT_ENABLE (1 << 26) @@ -1521,7 +1521,7 @@ __FBSDID("$FreeBSD$"); #define DVOA 0x61120 #define DVOB 0x61140 #define DVOC 0x61160 -#define DVO_ENABLE (1 << 31) +#define DVO_ENABLE (1U << 31) #define DVO_PIPE_B_SELECT (1 << 30) #define DVO_PIPE_STALL_UNUSED (0 << 28) #define DVO_PIPE_STALL (1 << 28) @@ -1557,7 +1557,7 @@ __FBSDID("$FreeBSD$"); * Enables the LVDS port. This bit must be set before DPLLs are enabled, as * the DPLL semantics change when the LVDS is assigned to that pipe. */ -#define LVDS_PORT_EN (1 << 31) +#define LVDS_PORT_EN (1U << 31) /* Selects pipe B for LVDS data. Must be set on pre-965. */ #define LVDS_PIPEB_SELECT (1 << 30) #define LVDS_PIPE_MASK (1 << 30) @@ -1604,7 +1604,7 @@ __FBSDID("$FreeBSD$"); /* Video Data Island Packet control */ #define VIDEO_DIP_DATA 0x61178 #define VIDEO_DIP_CTL 0x61170 -#define VIDEO_DIP_ENABLE (1 << 31) +#define VIDEO_DIP_ENABLE (1U << 31) #define VIDEO_DIP_PORT_B (1 << 29) #define VIDEO_DIP_PORT_C (2 << 29) #define VIDEO_DIP_ENABLE_AVI (1 << 21) @@ -1620,7 +1620,7 @@ __FBSDID("$FreeBSD$"); /* Panel power sequencing */ #define PP_STATUS 0x61200 -#define PP_ON (1 << 31) +#define PP_ON (1U << 31) /* * Indicates that all dependencies of the panel are on: * @@ -1653,7 +1653,7 @@ __FBSDID("$FreeBSD$"); /* Panel fitting */ #define PFIT_CONTROL 0x61230 -#define PFIT_ENABLE (1 << 31) +#define PFIT_ENABLE (1U << 31) #define PFIT_PIPE_MASK (3 << 29) #define PFIT_PIPE_SHIFT 29 #define VERT_INTERP_DISABLE (0 << 10) @@ -1714,7 +1714,7 @@ __FBSDID("$FreeBSD$"); /* TV port control */ #define TV_CTL 0x68000 /** Enables the TV encoder */ -# define TV_ENC_ENABLE (1 << 31) +# define TV_ENC_ENABLE (1U << 31) /** Sources the TV encoder input from pipe B instead of A. */ # define TV_ENC_PIPEB_SELECT (1 << 30) /** Outputs composite video (DAC A only) */ @@ -1786,7 +1786,7 @@ __FBSDID("$FreeBSD$"); * * This gets cleared when TV_DAC_STATE_EN is cleared */ -# define TVDAC_STATE_CHG (1 << 31) +# define TVDAC_STATE_CHG (1U << 31) # define TVDAC_SENSE_MASK (7 << 28) /** Reports that DAC A voltage is above the detect threshold */ # define TVDAC_A_SENSE (1 << 30) @@ -1913,7 +1913,7 @@ __FBSDID("$FreeBSD$"); #define TV_H_CTL_2 0x68034 /** Enables the colorburst (needed for non-component color) */ -# define TV_BURST_ENA (1 << 31) +# define TV_BURST_ENA (1U << 31) /** Offset of the colorburst from the start of hsync, in pixels minus one. */ # define TV_HBURST_START_SHIFT 16 # define TV_HBURST_START_MASK 0x1fff0000 @@ -1958,7 +1958,7 @@ __FBSDID("$FreeBSD$"); #define TV_V_CTL_3 0x68044 /** Enables generation of the equalization signal */ -# define TV_EQUAL_ENA (1 << 31) +# define TV_EQUAL_ENA (1U << 31) /** Length of vsync, in half lines */ # define TV_VEQ_LEN_MASK 0x007f0000 # define TV_VEQ_LEN_SHIFT 16 @@ -2032,7 +2032,7 @@ __FBSDID("$FreeBSD$"); #define TV_SC_CTL_1 0x68060 /** Turns on the first subcarrier phase generation DDA */ -# define TV_SC_DDA1_EN (1 << 31) +# define TV_SC_DDA1_EN (1U << 31) /** Turns on the first subcarrier phase generation DDA */ # define TV_SC_DDA2_EN (1 << 30) /** Turns on the first subcarrier phase generation DDA */ @@ -2095,7 +2095,7 @@ __FBSDID("$FreeBSD$"); * If set, the rest of the registers are ignored, and the calculated values can * be read back from the register. */ -# define TV_AUTO_SCALE (1 << 31) +# define TV_AUTO_SCALE (1U << 31) /** * Disables the vertical filter. * @@ -2158,7 +2158,7 @@ __FBSDID("$FreeBSD$"); # define TV_VSCALE_IP_FRAC_SHIFT 0 #define TV_CC_CONTROL 0x68090 -# define TV_CC_ENABLE (1 << 31) +# define TV_CC_ENABLE (1U << 31) /** * Specifies which field to send the CC data in. * @@ -2174,7 +2174,7 @@ __FBSDID("$FreeBSD$"); # define TV_CC_LINE_SHIFT 0 #define TV_CC_DATA 0x68094 -# define TV_CC_RDY (1 << 31) +# define TV_CC_RDY (1U << 31) /** Second word of CC data to be transmitted. */ # define TV_CC_DATA_2_MASK 0x007f0000 # define TV_CC_DATA_2_SHIFT 16 @@ -2197,7 +2197,7 @@ __FBSDID("$FreeBSD$"); #define DP_C 0x64200 #define DP_D 0x64300 -#define DP_PORT_EN (1 << 31) +#define DP_PORT_EN (1U << 31) #define DP_PIPEB_SELECT (1 << 30) #define DP_PIPE_MASK (1 << 30) @@ -2307,7 +2307,7 @@ __FBSDID("$FreeBSD$"); #define DPD_AUX_CH_DATA4 0x64320 #define DPD_AUX_CH_DATA5 0x64324 -#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) +#define DP_AUX_CH_CTL_SEND_BUSY (1U << 31) #define DP_AUX_CH_CTL_DONE (1 << 30) #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) @@ -2903,7 +2903,7 @@ __FBSDID("$FreeBSD$"); /* VBIOS regs */ #define VGACNTRL 0x71400 -# define VGA_DISP_DISABLE (1 << 31) +# define VGA_DISP_DISABLE (1U << 31) # define VGA_2X_MODE (1 << 30) # define VGA_PIPE_B_SELECT (1 << 29) @@ -3029,7 +3029,7 @@ __FBSDID("$FreeBSD$"); #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) /* interrupts */ -#define DE_MASTER_IRQ_CONTROL (1 << 31) +#define DE_MASTER_IRQ_CONTROL (1U << 31) #define DE_SPRITEB_FLIP_DONE (1 << 29) #define DE_SPRITEA_FLIP_DONE (1 << 28) #define DE_PLANEB_FLIP_DONE (1 << 27) @@ -3553,7 +3553,7 @@ __FBSDID("$FreeBSD$"); /* or SDVOB */ #define HDMIB 0xe1140 -#define PORT_ENABLE (1 << 31) +#define PORT_ENABLE (1U << 31) #define TRANSCODER(pipe) ((pipe) << 30) #define TRANSCODER_CPT(pipe) ((pipe) << 29) #define TRANSCODER_MASK (1 << 30) @@ -3583,13 +3583,13 @@ __FBSDID("$FreeBSD$"); #define LVDS_DETECTED (1 << 1) #define BLC_PWM_CPU_CTL2 0x48250 -#define PWM_ENABLE (1 << 31) +#define PWM_ENABLE (1U << 31) #define PWM_PIPE_A (0 << 29) #define PWM_PIPE_B (1 << 29) #define BLC_PWM_CPU_CTL 0x48254 #define BLC_PWM_PCH_CTL1 0xc8250 -#define PWM_PCH_ENABLE (1 << 31) +#define PWM_PCH_ENABLE (1U << 31) #define PWM_POLARITY_ACTIVE_LOW (1 << 29) #define PWM_POLARITY_ACTIVE_HIGH (0 << 29) #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28) @@ -3611,8 +3611,8 @@ __FBSDID("$FreeBSD$"); #define PANEL_PORT_SELECT_LVDS (0 << 30) #define PANEL_PORT_SELECT_DPA (1 << 30) #define EDP_PANEL (1 << 30) -#define PANEL_PORT_SELECT_DPC (2 << 30) -#define PANEL_PORT_SELECT_DPD (3 << 30) +#define PANEL_PORT_SELECT_DPC (2U << 30) +#define PANEL_PORT_SELECT_DPD (3U << 30) #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) #define PANEL_POWER_UP_DELAY_SHIFT 16 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) diff --git a/sys/dev/drm2/radeon/evergreen_blit_kms.c b/sys/dev/drm2/radeon/evergreen_blit_kms.c index 1012f3f..f89f8b5 100644 --- a/sys/dev/drm2/radeon/evergreen_blit_kms.c +++ b/sys/dev/drm2/radeon/evergreen_blit_kms.c @@ -241,12 +241,12 @@ set_scissors(struct radeon_device *rdev, int x1, int y1, radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); - radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); + radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31)); radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); - radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); + radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31)); radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); } diff --git a/sys/dev/drm2/radeon/evergreen_cs.c b/sys/dev/drm2/radeon/evergreen_cs.c index 693c38c..1dac265 100644 --- a/sys/dev/drm2/radeon/evergreen_cs.c +++ b/sys/dev/drm2/radeon/evergreen_cs.c @@ -2949,7 +2949,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) switch (misc) { case 0: /* L2T, frame to fields */ - if (idx_value & (1 << 31)) { + if (idx_value & (1U << 31)) { DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n"); return -EINVAL; } @@ -2992,7 +2992,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) return -EINVAL; } /* detile bit */ - if (idx_value & (1 << 31)) { + if (idx_value & (1U << 31)) { /* tiled src, linear dst */ ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8); @@ -3009,7 +3009,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) break; case 3: /* L2T, broadcast */ - if (idx_value & (1 << 31)) { + if (idx_value & (1U << 31)) { DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n"); return -EINVAL; } @@ -3048,7 +3048,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) case 4: /* L2T, T2L */ /* detile bit */ - if (idx_value & (1 << 31)) { + if (idx_value & (1U << 31)) { /* tiled src, linear dst */ src_offset = radeon_get_ib_value(p, idx+1); src_offset <<= 8; @@ -3093,7 +3093,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) break; case 7: /* L2T, broadcast */ - if (idx_value & (1 << 31)) { + if (idx_value & (1U << 31)) { DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n"); return -EINVAL; } @@ -3137,7 +3137,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) switch (misc) { case 0: /* detile bit */ - if (idx_value & (1 << 31)) { + if (idx_value & (1U << 31)) { /* tiled src, linear dst */ src_offset = radeon_get_ib_value(p, idx+1); src_offset <<= 8; diff --git a/sys/dev/drm2/radeon/evergreend.h b/sys/dev/drm2/radeon/evergreend.h index 3fd74ce..044351a 100644 --- a/sys/dev/drm2/radeon/evergreend.h +++ b/sys/dev/drm2/radeon/evergreend.h @@ -61,7 +61,7 @@ __FBSDID("$FreeBSD$"); #define INSTANCE_INDEX(x) ((x) << 0) #define SE_INDEX(x) ((x) << 16) #define INSTANCE_BROADCAST_WRITES (1 << 30) -#define SE_BROADCAST_WRITES (1 << 31) +#define SE_BROADCAST_WRITES (1U << 31) #define RLC_GFX_INDEX 0x3fC4 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 #define WRITE_DIS (1 << 0) @@ -125,7 +125,7 @@ __FBSDID("$FreeBSD$"); #define RB_BUFSZ(x) ((x) << 0) #define RB_BLKSZ(x) ((x) << 8) #define RB_NO_UPDATE (1 << 27) -#define RB_RPTR_WR_ENA (1 << 31) +#define RB_RPTR_WR_ENA (1U << 31) #define BUF_SWAP_32BIT (2 << 16) #define CP_RB_RPTR 0x8700 #define CP_RB_RPTR_ADDR 0xC10C @@ -187,7 +187,7 @@ __FBSDID("$FreeBSD$"); # define HDMI_ACR_X1 1 # define HDMI_ACR_X2 2 # define HDMI_ACR_X4 4 -# define HDMI_ACR_AUDIO_PRIORITY (1 << 31) +# define HDMI_ACR_AUDIO_PRIORITY (1U << 31) #define HDMI_VBI_PACKET_CONTROL 0x7040 # define HDMI_NULL_SEND (1 << 0) # define HDMI_GC_SEND (1 << 4) @@ -322,7 +322,7 @@ __FBSDID("$FreeBSD$"); # define AFMT_AUDIO_CRC_EN (1 << 0) #define AFMT_RAMP_CONTROL0 0x7110 # define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) -# define AFMT_RAMP_DATA_SIGN (1 << 31) +# define AFMT_RAMP_DATA_SIGN (1U << 31) #define AFMT_RAMP_CONTROL1 0x7114 # define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) # define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24) @@ -406,7 +406,7 @@ __FBSDID("$FreeBSD$"); # define PIN1_AUDIO_ENABLED (1 << 25) # define PIN2_AUDIO_ENABLED (1 << 26) # define PIN3_AUDIO_ENABLED (1 << 27) -# define AUDIO_ENABLED (1 << 31) +# define AUDIO_ENABLED (1U << 31) #define GC_USER_SHADER_PIPE_CONFIG 0x8954 @@ -452,7 +452,7 @@ __FBSDID("$FreeBSD$"); #define CP_COHERENCY_BUSY (1 << 28) #define CP_BUSY (1 << 29) #define CB_BUSY (1 << 30) -#define GUI_ACTIVE (1 << 31) +#define GUI_ACTIVE (1U << 31) #define GRBM_STATUS_SE0 0x8014 #define GRBM_STATUS_SE1 0x8018 #define SE_SX_CLEAN (1 << 0) @@ -464,7 +464,7 @@ __FBSDID("$FreeBSD$"); #define SE_SH_BUSY (1 << 28) #define SE_SC_BUSY (1 << 29) #define SE_DB_BUSY (1 << 30) -#define SE_CB_BUSY (1 << 31) +#define SE_CB_BUSY (1U << 31) /* evergreen */ #define CG_THERMAL_CTRL 0x72c #define TOFFSET_MASK 0x00003FE0 @@ -771,7 +771,7 @@ __FBSDID("$FreeBSD$"); # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) -# define IH_WPTR_OVERFLOW_CLEAR (1 << 31) +# define IH_WPTR_OVERFLOW_CLEAR (1U << 31) #define IH_RB_BASE 0x3e04 #define IH_RB_RPTR 0x3e08 #define IH_RB_WPTR 0x3e0c @@ -797,13 +797,13 @@ __FBSDID("$FreeBSD$"); # define TIME_STAMP_INT_ENABLE (1 << 26) # define IB2_INT_ENABLE (1 << 29) # define IB1_INT_ENABLE (1 << 30) -# define RB_INT_ENABLE (1 << 31) +# define RB_INT_ENABLE (1U << 31) #define CP_INT_STATUS 0xc128 # define SCRATCH_INT_STAT (1 << 25) # define TIME_STAMP_INT_STAT (1 << 26) # define IB2_INT_STAT (1 << 29) # define IB1_INT_STAT (1 << 30) -# define RB_INT_STAT (1 << 31) +# define RB_INT_STAT (1U << 31) #define GRBM_INT_CNTL 0x8060 # define RDERR_INT_ENABLE (1 << 0) @@ -1062,7 +1062,7 @@ __FBSDID("$FreeBSD$"); * 1 - GDS * 2 - DATA */ -# define PACKET3_CP_DMA_CP_SYNC (1 << 31) +# define PACKET3_CP_DMA_CP_SYNC (1U << 31) /* COMMAND */ # define PACKET3_CP_DMA_DIS_WC (1 << 21) # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) diff --git a/sys/dev/drm2/radeon/nid.h b/sys/dev/drm2/radeon/nid.h index afe7a32..89c0237 100644 --- a/sys/dev/drm2/radeon/nid.h +++ b/sys/dev/drm2/radeon/nid.h @@ -219,7 +219,7 @@ __FBSDID("$FreeBSD$"); #define CP_COHERENCY_BUSY (1 << 28) #define CP_BUSY (1 << 29) #define CB_BUSY (1 << 30) -#define GUI_ACTIVE (1 << 31) +#define GUI_ACTIVE (1U << 31) #define GRBM_STATUS_SE0 0x8014 #define GRBM_STATUS_SE1 0x8018 #define SE_SX_CLEAN (1 << 0) @@ -233,7 +233,7 @@ __FBSDID("$FreeBSD$"); #define SE_SH_BUSY (1 << 28) #define SE_SC_BUSY (1 << 29) #define SE_DB_BUSY (1 << 30) -#define SE_CB_BUSY (1 << 31) +#define SE_CB_BUSY (1U << 31) #define GRBM_SOFT_RESET 0x8020 #define SOFT_RESET_CP (1 << 0) #define SOFT_RESET_CB (1 << 1) @@ -253,7 +253,7 @@ __FBSDID("$FreeBSD$"); #define INSTANCE_INDEX(x) ((x) << 0) #define SE_INDEX(x) ((x) << 16) #define INSTANCE_BROADCAST_WRITES (1 << 30) -#define SE_BROADCAST_WRITES (1 << 31) +#define SE_BROADCAST_WRITES (1U << 31) #define SCRATCH_REG0 0x8500 #define SCRATCH_REG1 0x8504 @@ -442,7 +442,7 @@ __FBSDID("$FreeBSD$"); #define RB_BUFSZ(x) ((x) << 0) #define RB_BLKSZ(x) ((x) << 8) #define RB_NO_UPDATE (1 << 27) -#define RB_RPTR_WR_ENA (1 << 31) +#define RB_RPTR_WR_ENA (1U << 31) #define BUF_SWAP_32BIT (2 << 16) #define CP_RB0_RPTR_ADDR 0xC10C #define CP_RB0_RPTR_ADDR_HI 0xC110 @@ -641,7 +641,7 @@ __FBSDID("$FreeBSD$"); #define DMA_IB_CNTL 0xd024 # define DMA_IB_ENABLE (1 << 0) # define DMA_IB_SWAP_ENABLE (1 << 4) -# define CMD_VMID_FORCE (1 << 31) +# define CMD_VMID_FORCE (1U << 31) #define DMA_IB_RPTR 0xd028 #define DMA_CNTL 0xd02c # define TRAP_ENABLE (1 << 0) diff --git a/sys/dev/drm2/radeon/r200.c b/sys/dev/drm2/radeon/r200.c index fe8b768..566645f 100644 --- a/sys/dev/drm2/radeon/r200.c +++ b/sys/dev/drm2/radeon/r200.c @@ -116,7 +116,7 @@ int r200_copy_dma(struct radeon_device *rdev, radeon_ring_write(ring, PACKET0(0x720, 2)); radeon_ring_write(ring, src_offset); radeon_ring_write(ring, dst_offset); - radeon_ring_write(ring, cur_size | (1 << 31) | (1 << 30)); + radeon_ring_write(ring, cur_size | (1U << 31) | (1 << 30)); src_offset += cur_size; dst_offset += cur_size; } diff --git a/sys/dev/drm2/radeon/r300.c b/sys/dev/drm2/radeon/r300.c index aa9073c..5681035 100644 --- a/sys/dev/drm2/radeon/r300.c +++ b/sys/dev/drm2/radeon/r300.c @@ -1041,7 +1041,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, track->textures[i].height = tmp + 1; tmp = (idx_value >> 26) & 0xF; track->textures[i].num_levels = tmp; - tmp = idx_value & (1 << 31); + tmp = idx_value & (1U << 31); track->textures[i].use_pitch = !!tmp; tmp = (idx_value >> 22) & 0xF; track->textures[i].txdepth = tmp; diff --git a/sys/dev/drm2/radeon/r300_reg.h b/sys/dev/drm2/radeon/r300_reg.h index 3478d00..3dc2b43 100644 --- a/sys/dev/drm2/radeon/r300_reg.h +++ b/sys/dev/drm2/radeon/r300_reg.h @@ -1210,7 +1210,7 @@ __FBSDID("$FreeBSD$"); # define R300_FPI0_OUTC_FRC (9 << 23) # define R300_FPI0_OUTC_REPL_ALPHA (10 << 23) # define R300_FPI0_OUTC_SAT (1 << 30) -# define R300_FPI0_INSERT_NOP (1 << 31) +# define R300_FPI0_INSERT_NOP (1U << 31) #define R300_PFS_INSTR2_0 0x49C0 # define R300_FPI2_ARGA_SRC0C_X 0 @@ -1257,7 +1257,7 @@ __FBSDID("$FreeBSD$"); # define R300_FPI2_OUTA_RCP (10 << 23) # define R300_FPI2_OUTA_RSQ (11 << 23) # define R300_FPI2_OUTA_SAT (1 << 30) -# define R300_FPI2_UNKNOWN_31 (1 << 31) +# define R300_FPI2_UNKNOWN_31 (1U << 31) /* END: Fragment program instruction set */ /* Fog state and color */ @@ -1460,7 +1460,7 @@ __FBSDID("$FreeBSD$"); # define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1) # define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1) # define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31) -# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31) +# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1U << 31) #define R300_ZB_BW_CNTL 0x4f1c # define R300_HIZ_DISABLE (0 << 0) diff --git a/sys/dev/drm2/radeon/r500_reg.h b/sys/dev/drm2/radeon/r500_reg.h index c56088b..7b7130e 100644 --- a/sys/dev/drm2/radeon/r500_reg.h +++ b/sys/dev/drm2/radeon/r500_reg.h @@ -88,7 +88,7 @@ __FBSDID("$FreeBSD$"); # define R300_SUBPIXEL_1_12 (0 << 16) # define R300_SUBPIXEL_1_16 (1 << 16) #define R300_DST_PIPE_CONFIG 0x170c -# define R300_PIPE_AUTO_CONFIG (1 << 31) +# define R300_PIPE_AUTO_CONFIG (1U << 31) #define R300_RB2D_DSTCACHE_MODE 0x3428 # define R300_DC_AUTOFLUSH_ENABLE (1 << 8) # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) @@ -148,7 +148,7 @@ __FBSDID("$FreeBSD$"); # define RS480_GTW_LAC_EN (1 << 25) # define RS480_2LEVEL_GART (0 << 30) # define RS480_1LEVEL_GART (1 << 30) -# define RS480_PDC_EN (1 << 31) +# define RS480_PDC_EN (1U << 31) #define RS480_GART_BASE 0x2c #define RS480_GART_CACHE_CNTRL 0x2e # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ @@ -639,7 +639,7 @@ __FBSDID("$FreeBSD$"); # define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1U << 31) #define AVIVO_LVTMA_CNTL 0x7a80 # define AVIVO_LVTMA_CNTL_ENABLE (1 << 0) @@ -705,7 +705,7 @@ __FBSDID("$FreeBSD$"); # define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1U << 31) #define R500_LVTMA_PWRSEQ_CNTL 0x7af0 #define R600_LVTMA_PWRSEQ_CNTL 0x7af4 diff --git a/sys/dev/drm2/radeon/r600_blit.c b/sys/dev/drm2/radeon/r600_blit.c index f9658d4..f44fd79 100644 --- a/sys/dev/drm2/radeon/r600_blit.c +++ b/sys/dev/drm2/radeon/r600_blit.c @@ -196,7 +196,7 @@ set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr) sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8)); #ifdef __BIG_ENDIAN - sq_vtx_constant_word2 |= (2 << 30); + sq_vtx_constant_word2 |= (2U << 30); #endif BEGIN_RING(9); @@ -275,12 +275,12 @@ set_scissors(drm_radeon_private_t *dev_priv, int x1, int y1, int x2, int y2) OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2)); OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2); - OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31)); + OUT_RING((x1 << 0) | (y1 << 16) | (1U << 31)); OUT_RING((x2 << 0) | (y2 << 16)); OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2)); OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2); - OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31)); + OUT_RING((x1 << 0) | (y1 << 16) | (1U << 31)); OUT_RING((x2 << 0) | (y2 << 16)); ADVANCE_RING(); } diff --git a/sys/dev/drm2/radeon/r600_blit_kms.c b/sys/dev/drm2/radeon/r600_blit_kms.c index e2ace69..47af990 100644 --- a/sys/dev/drm2/radeon/r600_blit_kms.c +++ b/sys/dev/drm2/radeon/r600_blit_kms.c @@ -244,12 +244,12 @@ set_scissors(struct radeon_device *rdev, int x1, int y1, radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); - radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); + radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31)); radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); - radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); + radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31)); radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); } diff --git a/sys/dev/drm2/radeon/r600_cs.c b/sys/dev/drm2/radeon/r600_cs.c index 6ba4614..9000b3c 100644 --- a/sys/dev/drm2/radeon/r600_cs.c +++ b/sys/dev/drm2/radeon/r600_cs.c @@ -2664,7 +2664,7 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p) if (tiled) { idx_value = radeon_get_ib_value(p, idx + 2); /* detile bit */ - if (idx_value & (1 << 31)) { + if (idx_value & (1U << 31)) { /* tiled src, linear dst */ src_offset = radeon_get_ib_value(p, idx+1); src_offset <<= 8; diff --git a/sys/dev/drm2/radeon/r600d.h b/sys/dev/drm2/radeon/r600d.h index 41cc7c6..174b1fe 100644 --- a/sys/dev/drm2/radeon/r600d.h +++ b/sys/dev/drm2/radeon/r600d.h @@ -204,7 +204,7 @@ __FBSDID("$FreeBSD$"); #define RB_BUFSZ(x) ((x) << 0) #define RB_BLKSZ(x) ((x) << 8) #define RB_NO_UPDATE (1 << 27) -#define RB_RPTR_WR_ENA (1 << 31) +#define RB_RPTR_WR_ENA (1U << 31) #define BUF_SWAP_32BIT (2 << 16) #define CP_RB_RPTR 0x8700 #define CP_RB_RPTR_ADDR 0xC10C @@ -220,7 +220,7 @@ __FBSDID("$FreeBSD$"); #define CP_SEM_WAIT_TIMER 0x85BC #define DB_DEBUG 0x9830 -#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) +#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1U << 31) #define DB_DEPTH_BASE 0x2800C #define DB_HTILE_DATA_BASE 0x28014 #define DB_HTILE_SURFACE 0x28D24 @@ -507,7 +507,7 @@ __FBSDID("$FreeBSD$"); #define SYNC_WALKER (1 << 25) #define SYNC_ALIGNER (1 << 26) #define BILINEAR_PRECISION_6_BIT (0 << 31) -#define BILINEAR_PRECISION_8_BIT (1 << 31) +#define BILINEAR_PRECISION_8_BIT (1U << 31) #define TC_CNTL 0x9608 #define TC_L2_SIZE(x) ((x)<<5) @@ -650,7 +650,7 @@ __FBSDID("$FreeBSD$"); # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) -# define IH_WPTR_OVERFLOW_CLEAR (1 << 31) +# define IH_WPTR_OVERFLOW_CLEAR (1U << 31) #define IH_RB_BASE 0x3e04 #define IH_RB_RPTR 0x3e08 #define IH_RB_WPTR 0x3e0c @@ -701,13 +701,13 @@ __FBSDID("$FreeBSD$"); # define TIME_STAMP_INT_ENABLE (1 << 26) # define IB2_INT_ENABLE (1 << 29) # define IB1_INT_ENABLE (1 << 30) -# define RB_INT_ENABLE (1 << 31) +# define RB_INT_ENABLE (1U << 31) #define CP_INT_STATUS 0xc128 # define SCRATCH_INT_STAT (1 << 25) # define TIME_STAMP_INT_STAT (1 << 26) # define IB2_INT_STAT (1 << 29) # define IB1_INT_STAT (1 << 30) -# define RB_INT_STAT (1 << 31) +# define RB_INT_STAT (1U << 31) #define GRBM_INT_CNTL 0x8060 # define RDERR_INT_ENABLE (1 << 0) @@ -914,7 +914,7 @@ __FBSDID("$FreeBSD$"); #define DCCG_AUDIO_DTO0_PHASE 0x0514 #define DCCG_AUDIO_DTO0_MODULE 0x0518 #define DCCG_AUDIO_DTO0_LOAD 0x051c -# define DTO_LOAD (1 << 31) +# define DTO_LOAD (1U << 31) #define DCCG_AUDIO_DTO0_CNTL 0x0520 #define DCCG_AUDIO_DTO1_PHASE 0x0524 @@ -1197,7 +1197,7 @@ __FBSDID("$FreeBSD$"); * 5. DST_ADDR_HI [7:0] * 6. COMMAND [29:22] | BYTE_COUNT [20:0] */ -# define PACKET3_CP_DMA_CP_SYNC (1 << 31) +# define PACKET3_CP_DMA_CP_SYNC (1U << 31) /* COMMAND */ # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) /* 0 - none diff --git a/sys/dev/drm2/radeon/radeon_cp.c b/sys/dev/drm2/radeon/radeon_cp.c index 4a03633..4ec2773 100644 --- a/sys/dev/drm2/radeon/radeon_cp.c +++ b/sys/dev/drm2/radeon/radeon_cp.c @@ -564,7 +564,7 @@ static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv) #if 0 u32 tmp; - tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); + tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1U << 31); RADEON_WRITE(RADEON_CP_RB_WPTR, tmp); #endif } diff --git a/sys/dev/drm2/radeon/radeon_drv.h b/sys/dev/drm2/radeon/radeon_drv.h index f33ea18..99c6aa4 100644 --- a/sys/dev/drm2/radeon/radeon_drv.h +++ b/sys/dev/drm2/radeon/radeon_drv.h @@ -572,7 +572,7 @@ void radeon_unregister_atpx_handler(void); # define RS480_GTW_LAC_EN (1 << 25) # define RS480_2LEVEL_GART (0 << 30) # define RS480_1LEVEL_GART (1 << 30) -# define RS480_PDC_EN (1 << 31) +# define RS480_PDC_EN (1U << 31) #define RS480_GART_BASE 0x2c #define RS480_GART_CACHE_CNTRL 0x2e # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ @@ -688,7 +688,7 @@ void radeon_unregister_atpx_handler(void); # define R300_SUBPIXEL_1_12 (0 << 16) # define R300_SUBPIXEL_1_16 (1 << 16) #define R300_DST_PIPE_CONFIG 0x170c -# define R300_PIPE_AUTO_CONFIG (1 << 31) +# define R300_PIPE_AUTO_CONFIG (1U << 31) #define R300_RB2D_DSTCACHE_MODE 0x3428 # define R300_DC_AUTOFLUSH_ENABLE (1 << 8) # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) @@ -720,8 +720,8 @@ void radeon_unregister_atpx_handler(void); #define RADEON_DST_PITCH_OFFSET_C 0x1c80 # define RADEON_DST_TILE_LINEAR (0 << 30) # define RADEON_DST_TILE_MACRO (1 << 30) -# define RADEON_DST_TILE_MICRO (2 << 30) -# define RADEON_DST_TILE_BOTH (3 << 30) +# define RADEON_DST_TILE_MICRO (2U << 30) +# define RADEON_DST_TILE_BOTH (3U << 30) #define RADEON_SCRATCH_REG0 0x15e0 #define RADEON_SCRATCH_REG1 0x15e4 @@ -815,7 +815,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); # define R300_RB2D_DC_FLUSH (3 << 0) # define R300_RB2D_DC_FREE (3 << 2) # define R300_RB2D_DC_FLUSH_ALL 0xf -# define R300_RB2D_DC_BUSY (1 << 31) +# define R300_RB2D_DC_BUSY (1U << 31) #define RADEON_RB3D_CNTL 0x1c3c # define RADEON_ALPHA_BLEND_ENABLE (1 << 0) # define RADEON_PLANE_MASK_ENABLE (1 << 1) @@ -837,16 +837,16 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); # define RADEON_RB3D_ZC_FLUSH (1 << 0) # define RADEON_RB3D_ZC_FREE (1 << 2) # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 -# define RADEON_RB3D_ZC_BUSY (1 << 31) +# define RADEON_RB3D_ZC_BUSY (1U << 31) #define R300_ZB_ZCACHE_CTLSTAT 0x4f18 # define R300_ZC_FLUSH (1 << 0) # define R300_ZC_FREE (1 << 1) -# define R300_ZC_BUSY (1 << 31) +# define R300_ZC_BUSY (1U << 31) #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c # define RADEON_RB3D_DC_FLUSH (3 << 0) # define RADEON_RB3D_DC_FREE (3 << 2) # define RADEON_RB3D_DC_FLUSH_ALL 0xf -# define RADEON_RB3D_DC_BUSY (1 << 31) +# define RADEON_RB3D_DC_BUSY (1U << 31) #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c # define R300_RB3D_DC_FLUSH (2 << 0) # define R300_RB3D_DC_FREE (2 << 2) @@ -862,7 +862,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); # define RADEON_Z_COMPRESSION_ENABLE (1 << 28) # define RADEON_FORCE_Z_DIRTY (1 << 29) # define RADEON_Z_WRITE_ENABLE (1 << 30) -# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) +# define RADEON_Z_DECOMPRESSION_ENABLE (1U << 31) #define RADEON_RBBM_SOFT_RESET 0x00f0 # define RADEON_SOFT_RESET_CP (1 << 0) # define RADEON_SOFT_RESET_HI (1 << 1) @@ -916,7 +916,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); # define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */ # define RADEON_GA_BUSY (1 << 26) # define RADEON_CBA2D_BUSY (1 << 27) -# define RADEON_RBBM_ACTIVE (1 << 31) +# define RADEON_RBBM_ACTIVE (1U << 31) #define RADEON_RE_LINE_PATTERN 0x1cd0 #define RADEON_RE_MISC 0x26c4 #define RADEON_RE_TOP_LEFT 0x26c0 @@ -1030,7 +1030,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); #define RADEON_CP_RB_CNTL 0x0704 # define RADEON_BUF_SWAP_32BIT (2 << 16) # define RADEON_RB_NO_UPDATE (1 << 27) -# define RADEON_RB_RPTR_WR_ENA (1 << 31) +# define RADEON_RB_RPTR_WR_ENA (1U << 31) #define RADEON_CP_RB_RPTR_ADDR 0x070c #define RADEON_CP_RB_RPTR 0x0710 #define RADEON_CP_RB_WPTR 0x0714 @@ -1166,7 +1166,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 -#define RADEON_VTX_Z_PRESENT (1 << 31) +#define RADEON_VTX_Z_PRESENT (1U << 31) #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) #define RADEON_PRIM_TYPE_NONE (0 << 0) @@ -1497,7 +1497,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); #define R600_GRBM_STATUS 0x8010 # define R600_CMDFIFO_AVAIL_MASK 0x1f # define R700_CMDFIFO_AVAIL_MASK 0xf -# define R600_GUI_ACTIVE (1 << 31) +# define R600_GUI_ACTIVE (1U << 31) #define R600_GRBM_STATUS2 0x8014 #define R600_GRBM_SOFT_RESET 0x8020 # define R600_SOFT_RESET_CP (1 << 0) @@ -1520,7 +1520,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); # define R600_RB_BLKSZ(x) ((x) << 8) # define R600_BUF_SWAP_32BIT (2 << 16) # define R600_RB_NO_UPDATE (1 << 27) -# define R600_RB_RPTR_WR_ENA (1 << 31) +# define R600_RB_RPTR_WR_ENA (1U << 31) #define R600_CP_RB_RPTR_WR 0xc108 #define R600_CP_RB_RPTR_ADDR 0xc10c #define R600_CP_RB_RPTR_ADDR_HI 0xc110 @@ -1593,7 +1593,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); #define R600_SX_MISC 0x28350 #define R600_DB_DEBUG 0x9830 -# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) +# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1U << 31) #define R600_DB_WATERMARKS 0x9838 # define R600_DEPTH_FREE(x) ((x) << 0) # define R600_DEPTH_FLUSH(x) ((x) << 5) @@ -1699,7 +1699,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); # define R600_SYNC_WALKER (1 << 25) # define R600_SYNC_ALIGNER (1 << 26) # define R600_BILINEAR_PRECISION_6_BIT (0 << 31) -# define R600_BILINEAR_PRECISION_8_BIT (1 << 31) +# define R600_BILINEAR_PRECISION_8_BIT (1U << 31) #define R700_TCP_CNTL 0x9610 @@ -1773,7 +1773,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); # define R600_PERSP_GRADIENT_ENA (1 << 28) # define R600_LINEAR_GRADIENT_ENA (1 << 29) # define R600_POSITION_SAMPLE (1 << 30) -# define R600_BARYC_AT_SAMPLE_ENA (1 << 31) +# define R600_BARYC_AT_SAMPLE_ENA (1U << 31) #define R600_SPI_PS_IN_CONTROL_1 0x286d0 # define R600_GEN_INDEX_PIX (1 << 0) # define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1) diff --git a/sys/dev/drm2/radeon/radeon_reg.h b/sys/dev/drm2/radeon/radeon_reg.h index 8697e0f..22ab717 100644 --- a/sys/dev/drm2/radeon/radeon_reg.h +++ b/sys/dev/drm2/radeon/radeon_reg.h @@ -361,7 +361,7 @@ __FBSDID("$FreeBSD$"); # define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24) # define RADEON_DYN_STOP_MODE_MASK (7 << 21) # define RADEON_TVPLL_PWRMGT_OFF (1 << 30) -# define RADEON_TVCLK_TURNOFF (1 << 31) +# define RADEON_TVCLK_TURNOFF (1U << 31) #define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */ # define RADEON_PM_MODE_SEL (1 << 13) # define RADEON_TCL_BYPASS_DISABLE (1 << 20) @@ -585,13 +585,13 @@ __FBSDID("$FreeBSD$"); #define RADEON_CUR_HORZ_VERT_OFF 0x0268 #define RADEON_CUR_HORZ_VERT_POSN 0x0264 #define RADEON_CUR_OFFSET 0x0260 -# define RADEON_CUR_LOCK (1 << 31) +# define RADEON_CUR_LOCK (1U << 31) #define RADEON_CUR2_CLR0 0x036c #define RADEON_CUR2_CLR1 0x0370 #define RADEON_CUR2_HORZ_VERT_OFF 0x0368 #define RADEON_CUR2_HORZ_VERT_POSN 0x0364 #define RADEON_CUR2_OFFSET 0x0360 -# define RADEON_CUR2_LOCK (1 << 31) +# define RADEON_CUR2_LOCK (1U << 31) #define RADEON_DAC_CNTL 0x0058 # define RADEON_DAC_RANGE_CNTL (3 << 0) @@ -670,7 +670,7 @@ __FBSDID("$FreeBSD$"); # define RADEON_TV_DAC_BDACPD (1 << 26) # define RADEON_TV_DAC_RDACDET (1 << 29) # define RADEON_TV_DAC_GDACDET (1 << 30) -# define RADEON_TV_DAC_BDACDET (1 << 31) +# define RADEON_TV_DAC_BDACDET (1U << 31) # define R420_TV_DAC_DACADJ_MASK (0x1f << 20) # define R420_TV_DAC_RDACPD (1 << 25) # define R420_TV_DAC_GDACPD (1 << 26) @@ -745,7 +745,7 @@ __FBSDID("$FreeBSD$"); #define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 # define RADEON_DST_Y_MAJOR (1 << 2) # define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) -# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) +# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1U << 31) #define RADEON_DP_DATATYPE 0x16c4 # define RADEON_HOST_BIG_ENDIAN_EN (1 << 29) #define RADEON_DP_GUI_MASTER_CNTL 0x146c @@ -854,8 +854,8 @@ __FBSDID("$FreeBSD$"); # define RADEON_PITCH_SHIFT 21 # define RADEON_DST_TILE_LINEAR (0 << 30) # define RADEON_DST_TILE_MACRO (1 << 30) -# define RADEON_DST_TILE_MICRO (2 << 30) -# define RADEON_DST_TILE_BOTH (3 << 30) +# define RADEON_DST_TILE_MICRO (2U << 30) +# define RADEON_DST_TILE_BOTH (3U << 30) #define RADEON_DST_WIDTH 0x140c #define RADEON_DST_WIDTH_HEIGHT 0x1598 #define RADEON_DST_WIDTH_X 0x1588 @@ -1230,7 +1230,7 @@ __FBSDID("$FreeBSD$"); #define RADEON_MIN_GRANT 0x0f3e /* PCI */ #define RADEON_MM_DATA 0x0004 #define RADEON_MM_INDEX 0x0000 -# define RADEON_MM_APER (1 << 31) +# define RADEON_MM_APER (1U << 31) #define RADEON_MPLL_CNTL 0x000e /* PLL */ #define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ #define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ @@ -1600,12 +1600,12 @@ __FBSDID("$FreeBSD$"); # define RADEON_SOFT_RESET_HDP (1 << 7) #define RADEON_RBBM_STATUS 0x0e40 # define RADEON_RBBM_FIFOCNT_MASK 0x007f -# define RADEON_RBBM_ACTIVE (1 << 31) +# define RADEON_RBBM_ACTIVE (1U << 31) #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c # define RADEON_RB2D_DC_FLUSH (3 << 0) # define RADEON_RB2D_DC_FREE (3 << 2) # define RADEON_RB2D_DC_FLUSH_ALL 0xf -# define RADEON_RB2D_DC_BUSY (1 << 31) +# define RADEON_RB2D_DC_BUSY (1U << 31) #define RADEON_RB2D_DSTCACHE_MODE 0x3428 #define RADEON_DSTCACHE_CTLSTAT 0x1714 @@ -1631,7 +1631,7 @@ __FBSDID("$FreeBSD$"); # define RADEON_RB3D_DC_FLUSH (3 << 0) # define RADEON_RB3D_DC_FREE (3 << 2) # define RADEON_RB3D_DC_FLUSH_ALL 0xf -# define RADEON_RB3D_DC_BUSY (1 << 31) +# define RADEON_RB3D_DC_BUSY (1U << 31) #define RADEON_REG_BASE 0x0f18 /* PCI */ #define RADEON_REGPROG_INF 0x0f09 /* PCI */ @@ -1854,7 +1854,7 @@ __FBSDID("$FreeBSD$"); # define RADEON_WAIT_VAP_IDLE (1 << 28) # define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30) # define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31) -# define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31) +# define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1U << 31) #define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */ #define RADEON_XCLK_CNTL 0x000d /* PLL */ @@ -1896,7 +1896,7 @@ __FBSDID("$FreeBSD$"); # define RADEON_BUMPED_MAP_T2 (2 << 27) # define RADEON_TEX_3D_ENABLE_0 (1 << 29) # define RADEON_TEX_3D_ENABLE_1 (1 << 30) -# define RADEON_MC_ENABLE (1 << 31) +# define RADEON_MC_ENABLE (1U << 31) #define RADEON_PP_FOG_COLOR 0x1c18 # define RADEON_FOG_COLOR_MASK 0x00ffffff # define RADEON_FOG_VERTEX (0 << 24) @@ -2091,7 +2091,7 @@ __FBSDID("$FreeBSD$"); # define RADEON_TEX_VSIZE_SHIFT 16 # define RADEON_SIGNED_RGB_MASK (1 << 30) # define RADEON_SIGNED_RGB_SHIFT 30 -# define RADEON_SIGNED_ALPHA_MASK (1 << 31) +# define RADEON_SIGNED_ALPHA_MASK (1U << 31) # define RADEON_SIGNED_ALPHA_SHIFT 31 #define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */ #define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */ @@ -2558,7 +2558,7 @@ __FBSDID("$FreeBSD$"); # define RADEON_TCL_VTX_Z1 (1 << 28) # define RADEON_TCL_VTX_W1 (1 << 29) # define RADEON_TCL_VTX_NORM1 (1 << 30) -# define RADEON_TCL_VTX_Z0 (1 << 31) +# define RADEON_TCL_VTX_Z0 (1U << 31) #define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258 # define RADEON_TCL_COMPUTE_XYZW (1 << 0) @@ -2667,7 +2667,7 @@ __FBSDID("$FreeBSD$"); # define RADEON_CULL_FRONT_IS_CCW (1 << 28) # define RADEON_CULL_FRONT (1 << 29) # define RADEON_CULL_BACK (1 << 30) -# define RADEON_FORCE_W_TO_ONE (1 << 31) +# define RADEON_FORCE_W_TO_ONE (1U << 31) #define RADEON_SE_VPORT_XSCALE 0x1d98 #define RADEON_SE_VPORT_XOFFSET 0x1d9c @@ -3306,7 +3306,7 @@ __FBSDID("$FreeBSD$"); # define RADEON_MAX_FETCH_SHIFT 18 # define RADEON_MAX_FETCH_MASK (0x3 << 18) # define RADEON_RB_NO_UPDATE (1 << 27) -# define RADEON_RB_RPTR_WR_ENA (1 << 31) +# define RADEON_RB_RPTR_WR_ENA (1U << 31) #define RADEON_CP_RB_RPTR_ADDR 0x070c #define RADEON_CP_RB_RPTR 0x0710 #define RADEON_CP_RB_WPTR 0x0714 @@ -3320,7 +3320,7 @@ __FBSDID("$FreeBSD$"); # define R600_RB_BUFSZ(x) ((x) << 0) # define R600_RB_BLKSZ(x) ((x) << 8) # define R600_RB_NO_UPDATE (1 << 27) -# define R600_RB_RPTR_WR_ENA (1 << 31) +# define R600_RB_RPTR_WR_ENA (1U << 31) #define R600_CP_RB_RPTR_WR 0xc108 #define R600_CP_RB_RPTR_ADDR 0xc10c #define R600_CP_RB_RPTR_ADDR_HI 0xc110 @@ -3519,7 +3519,7 @@ __FBSDID("$FreeBSD$"); # define RADEON_TV_FIFO_CE_EN (1 << 10) # define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14) # define RADEON_TVCLK_ALWAYS_ONb (1 << 30) -# define RADEON_TV_ON (1 << 31) +# define RADEON_TV_ON (1U << 31) #define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888 # define RADEON_Y_RED_EN (1 << 0) # define RADEON_C_GRN_EN (1 << 1) @@ -3651,7 +3651,7 @@ __FBSDID("$FreeBSD$"); # define RADEON_TVPVG_MASK (7 << 11) # define RADEON_TVPDC_SHIFT 14 # define RADEON_TVPDC_MASK (3 << 14) -# define RADEON_TVPLL_TEST_DIS (1 << 31) +# define RADEON_TVPLL_TEST_DIS (1U << 31) # define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30) #define RS400_DISP2_REQ_CNTL1 0xe30 diff --git a/sys/dev/drm2/radeon/rv770d.h b/sys/dev/drm2/radeon/rv770d.h index 1f2c23c..e281444 100644 --- a/sys/dev/drm2/radeon/rv770d.h +++ b/sys/dev/drm2/radeon/rv770d.h @@ -82,7 +82,7 @@ __FBSDID("$FreeBSD$"); #define RB_BUFSZ(x) ((x) << 0) #define RB_BLKSZ(x) ((x) << 8) #define RB_NO_UPDATE (1 << 27) -#define RB_RPTR_WR_ENA (1 << 31) +#define RB_RPTR_WR_ENA (1U << 31) #define BUF_SWAP_32BIT (2 << 16) #define CP_RB_RPTR 0x8700 #define CP_RB_RPTR_ADDR 0xC10C @@ -312,7 +312,7 @@ __FBSDID("$FreeBSD$"); #define SYNC_WALKER (1 << 25) #define SYNC_ALIGNER (1 << 26) #define BILINEAR_PRECISION_6_BIT (0 << 31) -#define BILINEAR_PRECISION_8_BIT (1 << 31) +#define BILINEAR_PRECISION_8_BIT (1U << 31) #define TCP_CNTL 0x9610 #define TCP_CHAN_STEER 0x9614 @@ -537,7 +537,7 @@ __FBSDID("$FreeBSD$"); # define AFMT_AUDIO_CRC_EN (1 << 0) #define AFMT_RAMP_CONTROL0 0x74e0 # define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) -# define AFMT_RAMP_DATA_SIGN (1 << 31) +# define AFMT_RAMP_DATA_SIGN (1U << 31) #define AFMT_RAMP_CONTROL1 0x74e4 # define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) # define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24) @@ -622,7 +622,7 @@ __FBSDID("$FreeBSD$"); # define PIN1_AUDIO_ENABLED (1 << 25) # define PIN2_AUDIO_ENABLED (1 << 26) # define PIN3_AUDIO_ENABLED (1 << 27) -# define AUDIO_ENABLED (1 << 31) +# define AUDIO_ENABLED (1U << 31) #define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 diff --git a/sys/dev/drm2/radeon/sid.h b/sys/dev/drm2/radeon/sid.h index 028916f..7aa21c1 100644 --- a/sys/dev/drm2/radeon/sid.h +++ b/sys/dev/drm2/radeon/sid.h @@ -199,7 +199,7 @@ __FBSDID("$FreeBSD$"); #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808 #define TRAIN_DONE_D0 (1 << 30) -#define TRAIN_DONE_D1 (1 << 31) +#define TRAIN_DONE_D1 (1U << 31) #define MC_SEQ_SUP_CNTL 0x28c8 #define RUN_MASK (1 << 0) @@ -227,7 +227,7 @@ __FBSDID("$FreeBSD$"); # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) -# define IH_WPTR_OVERFLOW_CLEAR (1 << 31) +# define IH_WPTR_OVERFLOW_CLEAR (1U << 31) #define IH_RB_BASE 0x3e04 #define IH_RB_RPTR 0x3e08 #define IH_RB_WPTR 0x3e0c @@ -414,7 +414,7 @@ __FBSDID("$FreeBSD$"); #define CP_COHERENCY_BUSY (1 << 28) #define CP_BUSY (1 << 29) #define CB_BUSY (1 << 30) -#define GUI_ACTIVE (1 << 31) +#define GUI_ACTIVE (1U << 31) #define GRBM_STATUS_SE0 0x8014 #define GRBM_STATUS_SE1 0x8018 #define SE_DB_CLEAN (1 << 1) @@ -427,7 +427,7 @@ __FBSDID("$FreeBSD$"); #define SE_SPI_BUSY (1 << 27) #define SE_SC_BUSY (1 << 29) #define SE_DB_BUSY (1 << 30) -#define SE_CB_BUSY (1 << 31) +#define SE_CB_BUSY (1U << 31) #define GRBM_SOFT_RESET 0x8020 #define SOFT_RESET_CP (1 << 0) @@ -451,7 +451,7 @@ __FBSDID("$FreeBSD$"); #define SE_INDEX(x) ((x) << 16) #define SH_BROADCAST_WRITES (1 << 29) #define INSTANCE_BROADCAST_WRITES (1 << 30) -#define SE_BROADCAST_WRITES (1 << 31) +#define SE_BROADCAST_WRITES (1U << 31) #define GRBM_INT_CNTL 0x8060 # define RDERR_INT_ENABLE (1 << 0) @@ -672,7 +672,7 @@ __FBSDID("$FreeBSD$"); #define RB_BLKSZ(x) ((x) << 8) #define BUF_SWAP_32BIT (2 << 16) #define RB_NO_UPDATE (1 << 27) -#define RB_RPTR_WR_ENA (1 << 31) +#define RB_RPTR_WR_ENA (1U << 31) #define CP_RB0_RPTR_ADDR 0xC10C #define CP_RB0_RPTR_ADDR_HI 0xC110 @@ -706,7 +706,7 @@ __FBSDID("$FreeBSD$"); # define TIME_STAMP_INT_ENABLE (1 << 26) # define CP_RINGID2_INT_ENABLE (1 << 29) # define CP_RINGID1_INT_ENABLE (1 << 30) -# define CP_RINGID0_INT_ENABLE (1 << 31) +# define CP_RINGID0_INT_ENABLE (1U << 31) #define CP_INT_STATUS_RING0 0xC1B4 #define CP_INT_STATUS_RING1 0xC1B8 #define CP_INT_STATUS_RING2 0xC1BC @@ -714,7 +714,7 @@ __FBSDID("$FreeBSD$"); # define TIME_STAMP_INT_STAT (1 << 26) # define CP_RINGID2_INT_STAT (1 << 29) # define CP_RINGID1_INT_STAT (1 << 30) -# define CP_RINGID0_INT_STAT (1 << 31) +# define CP_RINGID0_INT_STAT (1U << 31) #define CP_DEBUG 0xC1FC @@ -890,7 +890,7 @@ __FBSDID("$FreeBSD$"); * 1 - GDS * 2 - DATA */ -# define PACKET3_CP_DMA_CP_SYNC (1 << 31) +# define PACKET3_CP_DMA_CP_SYNC (1U << 31) /* COMMAND */ # define PACKET3_CP_DMA_DIS_WC (1 << 21) # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) diff --git a/sys/dev/drm2/ttm/ttm_bo.c b/sys/dev/drm2/ttm/ttm_bo.c index 88f374e..d87940c 100644 --- a/sys/dev/drm2/ttm/ttm_bo.c +++ b/sys/dev/drm2/ttm/ttm_bo.c @@ -218,7 +218,7 @@ int ttm_bo_reserve_nolru(struct ttm_buffer_object *bo, * Already reserved by a thread that will not back * off for us. We need to back off. */ - if (unlikely(sequence - bo->val_seq < (1 << 31))) + if (unlikely(sequence - bo->val_seq < (1U << 31))) return -EAGAIN; } @@ -237,7 +237,7 @@ int ttm_bo_reserve_nolru(struct ttm_buffer_object *bo, * Wake up waiters that may need to recheck for deadlock, * if we decreased the sequence number. */ - if (unlikely((bo->val_seq - sequence < (1 << 31)) + if (unlikely((bo->val_seq - sequence < (1U << 31)) || !bo->seq_valid)) wake_up = true; @@ -315,7 +315,7 @@ int ttm_bo_reserve_slowpath_nolru(struct ttm_buffer_object *bo, return ret; } - if ((bo->val_seq - sequence < (1 << 31)) || !bo->seq_valid) + if ((bo->val_seq - sequence < (1U << 31)) || !bo->seq_valid) wake_up = true; /** diff --git a/sys/dev/e1000/e1000_82575.h b/sys/dev/e1000/e1000_82575.h index e7039d8..9d8d3fc 100644 --- a/sys/dev/e1000/e1000_82575.h +++ b/sys/dev/e1000/e1000_82575.h @@ -384,7 +384,7 @@ struct e1000_adv_tx_context_desc { #define E1000_ETQF_FILTER_ENABLE (1 << 26) #define E1000_ETQF_IMM_INT (1 << 29) #define E1000_ETQF_1588 (1 << 30) -#define E1000_ETQF_QUEUE_ENABLE (1 << 31) +#define E1000_ETQF_QUEUE_ENABLE (1U << 31) /* * ETQF filter list: one static filter per filter consumer. This is * to avoid filter collisions later. Add new filters @@ -411,7 +411,7 @@ struct e1000_adv_tx_context_desc { #define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */ #define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8 #define E1000_DTXSWC_LLE_SHIFT 16 -#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */ +#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1U << 31) /* global VF LB enable */ /* Easy defines for setting default pool, would normally be left a zero */ #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7 diff --git a/sys/dev/e1000/e1000_ich8lan.c b/sys/dev/e1000/e1000_ich8lan.c index 82ffceb..8177226 100644 --- a/sys/dev/e1000/e1000_ich8lan.c +++ b/sys/dev/e1000/e1000_ich8lan.c @@ -4149,7 +4149,7 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) /* Device Status */ if (hw->mac.type == e1000_ich8lan) { reg = E1000_READ_REG(hw, E1000_STATUS); - reg &= ~(1 << 31); + reg &= ~(1U << 31); E1000_WRITE_REG(hw, E1000_STATUS, reg); } diff --git a/sys/dev/e1000/e1000_regs.h b/sys/dev/e1000/e1000_regs.h index f2b37db..a88220f 100644 --- a/sys/dev/e1000/e1000_regs.h +++ b/sys/dev/e1000/e1000_regs.h @@ -207,7 +207,7 @@ /* QAV Tx mode control register bitfields masks */ #define E1000_TQAVCC_IDLE_SLOPE 0xFFFF /* Idle slope */ #define E1000_TQAVCC_KEEP_CREDITS (1 << 30) /* Keep credits opt enable */ -#define E1000_TQAVCC_QUEUE_MODE (1 << 31) /* SP vs. SR Tx mode */ +#define E1000_TQAVCC_QUEUE_MODE (1U << 31) /* SP vs. SR Tx mode */ /* Good transmitted packets counter registers */ #define E1000_PQGPTC(_n) (0x010014 + (0x100 * (_n))) diff --git a/sys/dev/etherswitch/arswitch/arswitchreg.h b/sys/dev/etherswitch/arswitch/arswitchreg.h index 38be689..f221014 100644 --- a/sys/dev/etherswitch/arswitch/arswitchreg.h +++ b/sys/dev/etherswitch/arswitch/arswitchreg.h @@ -46,7 +46,7 @@ #define AR8X16_MASK_CTRL_REV_MASK 0x000000ff #define AR8X16_MASK_CTRL_VER_MASK 0x0000ff00 #define AR8X16_MASK_CTRL_VER_SHIFT 8 -#define AR8X16_MASK_CTRL_SOFT_RESET (1 << 31) +#define AR8X16_MASK_CTRL_SOFT_RESET (1U << 31) #define AR8X16_REG_MODE 0x0008 /* DIR-615 E4 U-Boot */ @@ -111,7 +111,7 @@ #define AR8X16_VLAN_VID_SHIFT 16 #define AR8X16_VLAN_PRIO 0x70000000 #define AR8X16_VLAN_PRIO_SHIFT 28 -#define AR8X16_VLAN_PRIO_EN (1 << 31) +#define AR8X16_VLAN_PRIO_EN (1U << 31) #define AR8X16_REG_VLAN_DATA 0x0044 #define AR8X16_VLAN_MEMBER 0x0000003f @@ -151,6 +151,8 @@ #define AR8X16_MIB_FUNC_CAPTURE 0x3 #define AR8X16_MIB_FUNC_XXX (1 << 30) /* 0x40000000 */ +#define AR934X_MIB_ENABLE (1 << 30) + #define AR8X16_REG_MDIO_HIGH_ADDR 0x0094 #define AR8X16_REG_MDIO_CTRL 0x0098 @@ -160,7 +162,7 @@ #define AR8X16_MDIO_CTRL_CMD_WRITE 0 #define AR8X16_MDIO_CTRL_CMD_READ (1 << 27) #define AR8X16_MDIO_CTRL_MASTER_EN (1 << 30) -#define AR8X16_MDIO_CTRL_BUSY (1 << 31) +#define AR8X16_MDIO_CTRL_BUSY (1U << 31) #define AR8X16_REG_PORT_BASE(_p) (0x0100 + (_p) * 0x0100) @@ -287,5 +289,218 @@ #define AR8X16_MAX_VLANS 16 -#endif /* __AR8X16_SWITCHREG_H__ */ +/* + * AR9340 switch specific definitions. + */ + +/* XXX Linux define compatibility stuff */ +#define BITM(_count) ((1 << _count) - 1) +#define BITS(_shift, _count) (BITM(_count) << _shift) + +#define AR934X_REG_OPER_MODE0 0x04 +#define AR934X_OPER_MODE0_MAC_GMII_EN (1 << 6) +#define AR934X_OPER_MODE0_PHY_MII_EN (1 << 10) + +#define AR934X_REG_OPER_MODE1 0x08 +#define AR934X_REG_OPER_MODE1_PHY4_MII_EN (1 << 28) + +#define AR934X_REG_FLOOD_MASK 0x2c +#define AR934X_FLOOD_MASK_MC_DP(_p) (1 << (16 + (_p))) +#define AR934X_FLOOD_MASK_BC_DP(_p) (1 << (25 + (_p))) + +#define AR934X_REG_QM_CTRL 0x3c +#define AR934X_QM_CTRL_ARP_EN (1 << 15) + +#define AR934X_REG_AT_CTRL 0x5c +#define AR934X_AT_CTRL_AGE_TIME BITS(0, 15) +#define AR934X_AT_CTRL_AGE_EN (1 << 17) +#define AR934X_AT_CTRL_LEARN_CHANGE (1 << 18) + +#define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100) + +#define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08) +#define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0 +#define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN (1 << 12) +#define AR934X_PORT_VLAN1_PORT_TLS_MODE (1 << 13) +#define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN (1 << 14) +#define AR934X_PORT_VLAN1_PORT_CLONE_EN (1 << 15) +#define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16 +#define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN (1 << 28) +#define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29 + +#define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c) +#define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16 +#define AR934X_PORT_VLAN2_8021Q_MODE_S 30 +#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0 +#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1 +#define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2 +#define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3 +/* + * AR8327 specific registers + */ +#define AR8327_NUM_PORTS 7 +#define AR8327_NUM_PHYS 5 +#define AR8327_PORTS_ALL 0x7f + +#define AR8327_REG_MASK 0x000 + +#define AR8327_REG_PAD0_MODE 0x004 +#define AR8327_REG_PAD5_MODE 0x008 +#define AR8327_REG_PAD6_MODE 0x00c + +#define AR8327_PAD_MAC_MII_RXCLK_SEL (1 << 0) +#define AR8327_PAD_MAC_MII_TXCLK_SEL (1 << 1) +#define AR8327_PAD_MAC_MII_EN (1 << 2) +#define AR8327_PAD_MAC_GMII_RXCLK_SEL (1 << 4) +#define AR8327_PAD_MAC_GMII_TXCLK_SEL (1 << 5) +#define AR8327_PAD_MAC_GMII_EN (1 << 6) +#define AR8327_PAD_SGMII_EN (1 << 7) +#define AR8327_PAD_PHY_MII_RXCLK_SEL (1 << 8) +#define AR8327_PAD_PHY_MII_TXCLK_SEL (1 << 9) +#define AR8327_PAD_PHY_MII_EN (1 << 10) +#define AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL (1 << 11) +#define AR8327_PAD_PHY_GMII_RXCLK_SEL (1 << 12) +#define AR8327_PAD_PHY_GMII_TXCLK_SEL (1 << 13) +#define AR8327_PAD_PHY_GMII_EN (1 << 14) +#define AR8327_PAD_PHYX_GMII_EN (1 << 16) +#define AR8327_PAD_PHYX_RGMII_EN (1 << 17) +#define AR8327_PAD_PHYX_MII_EN (1 << 18) +#define AR8327_PAD_SGMII_DELAY_EN (1 << 19) +#define AR8327_PAD_RGMII_RXCLK_DELAY_SEL BITS(20, 2) +#define AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S 20 +#define AR8327_PAD_RGMII_TXCLK_DELAY_SEL BITS(22, 2) +#define AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S 22 +#define AR8327_PAD_RGMII_RXCLK_DELAY_EN (1 << 24) +#define AR8327_PAD_RGMII_TXCLK_DELAY_EN (1 << 25) +#define AR8327_PAD_RGMII_EN (1 << 26) + +#define AR8327_REG_POWER_ON_STRIP 0x010 +#define AR8327_POWER_ON_STRIP_POWER_ON_SEL (1U << 31) +#define AR8327_POWER_ON_STRIP_LED_OPEN_EN (1 << 24) +#define AR8327_POWER_ON_STRIP_SERDES_AEN (1 << 7) + +#define AR8327_REG_INT_STATUS0 0x020 +#define AR8327_INT0_VT_DONE (1 << 20) + +#define AR8327_REG_INT_STATUS1 0x024 +#define AR8327_REG_INT_MASK0 0x028 +#define AR8327_REG_INT_MASK1 0x02c + +#define AR8327_REG_MODULE_EN 0x030 +#define AR8327_MODULE_EN_MIB (1 << 0) + +#define AR8327_REG_MIB_FUNC 0x034 +#define AR8327_MIB_CPU_KEEP (1 << 20) + +#define AR8327_REG_SERVICE_TAG 0x048 +#define AR8327_REG_LED_CTRL0 0x050 +#define AR8327_REG_LED_CTRL1 0x054 +#define AR8327_REG_LED_CTRL2 0x058 +#define AR8327_REG_LED_CTRL3 0x05c +#define AR8327_REG_MAC_ADDR0 0x060 +#define AR8327_REG_MAC_ADDR1 0x064 + +#define AR8327_REG_MAX_FRAME_SIZE 0x078 +#define AR8327_MAX_FRAME_SIZE_MTU BITS(0, 14) + +#define AR8327_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) + +#define AR8327_REG_HEADER_CTRL 0x098 +#define AR8327_REG_PORT_HEADER(_i) (0x09c + (_i) * 4) + +#define AR8327_REG_SGMII_CTRL 0x0e0 +#define AR8327_SGMII_CTRL_EN_PLL (1 << 1) +#define AR8327_SGMII_CTRL_EN_RX (1 << 2) +#define AR8327_SGMII_CTRL_EN_TX (1 << 3) + +#define AR8327_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8) +#define AR8327_PORT_VLAN0_DEF_SVID BITS(0, 12) +#define AR8327_PORT_VLAN0_DEF_SVID_S 0 +#define AR8327_PORT_VLAN0_DEF_CVID BITS(16, 12) +#define AR8327_PORT_VLAN0_DEF_CVID_S 16 + +#define AR8327_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8) +#define AR8327_PORT_VLAN1_PORT_VLAN_PROP (1 << 6) +#define AR8327_PORT_VLAN1_OUT_MODE BITS(12, 2) +#define AR8327_PORT_VLAN1_OUT_MODE_S 12 +#define AR8327_PORT_VLAN1_OUT_MODE_UNMOD 0 +#define AR8327_PORT_VLAN1_OUT_MODE_UNTAG 1 +#define AR8327_PORT_VLAN1_OUT_MODE_TAG 2 +#define AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH 3 + +#define AR8327_REG_ATU_DATA0 0x600 +#define AR8327_REG_ATU_DATA1 0x604 +#define AR8327_REG_ATU_DATA2 0x608 + +#define AR8327_REG_ATU_FUNC 0x60c +#define AR8327_ATU_FUNC_OP BITS(0, 4) +#define AR8327_ATU_FUNC_OP_NOOP 0x0 +#define AR8327_ATU_FUNC_OP_FLUSH 0x1 +#define AR8327_ATU_FUNC_OP_LOAD 0x2 +#define AR8327_ATU_FUNC_OP_PURGE 0x3 +#define AR8327_ATU_FUNC_OP_FLUSH_LOCKED 0x4 +#define AR8327_ATU_FUNC_OP_FLUSH_UNICAST 0x5 +#define AR8327_ATU_FUNC_OP_GET_NEXT 0x6 +#define AR8327_ATU_FUNC_OP_SEARCH_MAC 0x7 +#define AR8327_ATU_FUNC_OP_CHANGE_TRUNK 0x8 +#define AR8327_ATU_FUNC_BUSY (1U << 31) + +#define AR8327_REG_VTU_FUNC0 0x0610 +#define AR8327_VTU_FUNC0_EG_MODE BITS(4, 14) +#define AR8327_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2) +#define AR8327_VTU_FUNC0_EG_MODE_KEEP 0 +#define AR8327_VTU_FUNC0_EG_MODE_UNTAG 1 +#define AR8327_VTU_FUNC0_EG_MODE_TAG 2 +#define AR8327_VTU_FUNC0_EG_MODE_NOT 3 +#define AR8327_VTU_FUNC0_IVL (1 << 19) +#define AR8327_VTU_FUNC0_VALID (1 << 20) + +#define AR8327_REG_VTU_FUNC1 0x0614 +#define AR8327_VTU_FUNC1_OP BITS(0, 3) +#define AR8327_VTU_FUNC1_OP_NOOP 0 +#define AR8327_VTU_FUNC1_OP_FLUSH 1 +#define AR8327_VTU_FUNC1_OP_LOAD 2 +#define AR8327_VTU_FUNC1_OP_PURGE 3 +#define AR8327_VTU_FUNC1_OP_REMOVE_PORT 4 +#define AR8327_VTU_FUNC1_OP_GET_NEXT 5 +#define AR8327_VTU_FUNC1_OP_GET_ONE 6 +#define AR8327_VTU_FUNC1_FULL (1 << 4) +#define AR8327_VTU_FUNC1_PORT (1 << 8, 4) +#define AR8327_VTU_FUNC1_PORT_S 8 +#define AR8327_VTU_FUNC1_VID (1 << 16, 12) +#define AR8327_VTU_FUNC1_VID_S 16 +#define AR8327_VTU_FUNC1_BUSY (1U << 31) + +#define AR8327_REG_FWD_CTRL0 0x620 +#define AR8327_FWD_CTRL0_CPU_PORT_EN (1 << 10) +#define AR8327_FWD_CTRL0_MIRROR_PORT BITS(4, 4) +#define AR8327_FWD_CTRL0_MIRROR_PORT_S 4 + +#define AR8327_REG_FWD_CTRL1 0x624 +#define AR8327_FWD_CTRL1_UC_FLOOD BITS(0, 7) +#define AR8327_FWD_CTRL1_UC_FLOOD_S 0 +#define AR8327_FWD_CTRL1_MC_FLOOD BITS(8, 7) +#define AR8327_FWD_CTRL1_MC_FLOOD_S 8 +#define AR8327_FWD_CTRL1_BC_FLOOD BITS(16, 7) +#define AR8327_FWD_CTRL1_BC_FLOOD_S 16 +#define AR8327_FWD_CTRL1_IGMP BITS(24, 7) +#define AR8327_FWD_CTRL1_IGMP_S 24 + +#define AR8327_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc) +#define AR8327_PORT_LOOKUP_MEMBER BITS(0, 7) +#define AR8327_PORT_LOOKUP_IN_MODE BITS(8, 2) +#define AR8327_PORT_LOOKUP_IN_MODE_S 8 +#define AR8327_PORT_LOOKUP_STATE BITS(16, 3) +#define AR8327_PORT_LOOKUP_STATE_S 16 +#define AR8327_PORT_LOOKUP_LEARN (1 << 20) +#define AR8327_PORT_LOOKUP_ING_MIRROR_EN (1 << 25) + +#define AR8327_REG_PORT_PRIO(_i) (0x664 + (_i) * 0xc) + +#define AR8327_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8) +#define AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN (1 << 16) + +#define AR8327_REG_PORT_STATS_BASE(_i) (0x1000 + (_i) * 0x100) + +#endif /* __AR8X16_SWITCHREG_H__ */ diff --git a/sys/dev/ffec/if_ffecreg.h b/sys/dev/ffec/if_ffecreg.h index ef2853d..2233df7 100644 --- a/sys/dev/ffec/if_ffecreg.h +++ b/sys/dev/ffec/if_ffecreg.h @@ -40,7 +40,7 @@ __FBSDID("$FreeBSD$"); */ #define FEC_IER_REG 0x0004 #define FEC_IEM_REG 0x0008 -#define FEC_IER_HBERR (1 << 31) +#define FEC_IER_HBERR (1U << 31) #define FEC_IER_BABR (1 << 30) #define FEC_IER_BABT (1 << 29) #define FEC_IER_GRA (1 << 28) @@ -98,12 +98,12 @@ __FBSDID("$FreeBSD$"); #define FEC_MSCR_MII_SPEED_MASk (0x3f << FEC_MSCR_MII_SPEED_SHIFT) #define FEC_MIBC_REG 0x0064 -#define FEC_MIBC_DIS (1 << 31) +#define FEC_MIBC_DIS (1U << 31) #define FEC_MIBC_IDLE (1 << 30) #define FEC_MIBC_CLEAR (1 << 29) /* imx6 only */ #define FEC_RCR_REG 0x0084 -#define FEC_RCR_GRS (1 << 31) +#define FEC_RCR_GRS (1U << 31) #define FEC_RCR_NLC (1 << 30) #define FEC_RCR_MAX_FL_SHIFT 16 #define FEC_RCR_MAX_FL_MASK (0x3fff << FEC_RCR_MAX_FL_SHIFT) @@ -265,7 +265,7 @@ struct ffec_hwdesc uint32_t buf_paddr; }; -#define FEC_TXDESC_READY (1 << 31) +#define FEC_TXDESC_READY (1U << 31) #define FEC_TXDESC_T01 (1 << 30) #define FEC_TXDESC_WRAP (1 << 29) #define FEC_TXDESC_T02 (1 << 28) @@ -274,7 +274,7 @@ struct ffec_hwdesc #define FEC_TXDESC_ABC (1 << 25) #define FEC_TXDESC_LEN_MASK (0xffff) -#define FEC_RXDESC_EMPTY (1 << 31) +#define FEC_RXDESC_EMPTY (1U << 31) #define FEC_RXDESC_R01 (1 << 30) #define FEC_RXDESC_WRAP (1 << 29) #define FEC_RXDESC_R02 (1 << 28) diff --git a/sys/dev/firewire/firewire.c b/sys/dev/firewire/firewire.c index f1ebb6d..0a6180a 100644 --- a/sys/dev/firewire/firewire.c +++ b/sys/dev/firewire/firewire.c @@ -649,7 +649,7 @@ fw_reset_csr(struct firewire_comm *fc) CSRARC(fc, BANDWIDTH_AV) = 4915; CSRARC(fc, CHANNELS_AV_HI) = 0xffffffff; CSRARC(fc, CHANNELS_AV_LO) = 0xffffffff; - CSRARC(fc, IP_CHANNELS) = (1 << 31); + CSRARC(fc, IP_CHANNELS) = (1U << 31); CSRARC(fc, CONF_ROM) = 0x04 << 24; CSRARC(fc, CONF_ROM + 4) = 0x31333934; /* means strings 1394 */ diff --git a/sys/dev/firewire/fwohci.c b/sys/dev/firewire/fwohci.c index 77886d3..ae753d5 100644 --- a/sys/dev/firewire/fwohci.c +++ b/sys/dev/firewire/fwohci.c @@ -179,7 +179,7 @@ static void fwohci_task_dma(void *, int); #define OHCI_ATRETRY 0x08 #define OHCI_CROMHDR 0x18 #define OHCI_BUS_OPT 0x20 -#define OHCI_BUSIRMC (1 << 31) +#define OHCI_BUSIRMC (1U << 31) #define OHCI_BUSCMC (1 << 30) #define OHCI_BUSISC (1 << 29) #define OHCI_BUSBMC (1 << 28) @@ -205,7 +205,7 @@ static void fwohci_task_dma(void *, int); #define OHCI_SID_BUF 0x64 #define OHCI_SID_CNT 0x68 -#define OHCI_SID_ERR (1 << 31) +#define OHCI_SID_ERR (1U << 31) #define OHCI_SID_CNT_MASK 0xffc #define OHCI_IT_STAT 0x90 diff --git a/sys/dev/firewire/fwohcireg.h b/sys/dev/firewire/fwohcireg.h index 64bbf4f..d8deca8 100644 --- a/sys/dev/firewire/fwohcireg.h +++ b/sys/dev/firewire/fwohcireg.h @@ -241,7 +241,7 @@ struct ohci_registers { fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */ fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */ fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */ -#define OHCI_HCC_BIBIV (1 << 31) /* BIBimage Valid */ +#define OHCI_HCC_BIBIV (1U << 31) /* BIBimage Valid */ #define OHCI_HCC_BIGEND (1 << 30) /* noByteSwapData */ #define OHCI_HCC_PRPHY (1 << 23) /* programPhyEnable */ #define OHCI_HCC_PHYEN (1 << 22) /* aPhyEnhanceEnable */ @@ -280,7 +280,7 @@ struct ohci_registers { fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/ #define FWOHCI_NODEID 0xe8 fwohcireg_t node; /* Node ID 0xe8 */ -#define OHCI_NODE_VALID (1 << 31) +#define OHCI_NODE_VALID (1U << 31) #define OHCI_NODE_ROOT (1 << 30) #define OHCI_ASYSRCBUS 1 diff --git a/sys/dev/firewire/sbp.c b/sys/dev/firewire/sbp.c index 00e780e..8c978dd 100644 --- a/sys/dev/firewire/sbp.c +++ b/sys/dev/firewire/sbp.c @@ -2469,7 +2469,7 @@ END_DEBUG ocb->sdev = sdev; ocb->ccb = ccb; ccb->ccb_h.ccb_sdev_ptr = sdev; - ocb->orb[0] = htonl(1 << 31); + ocb->orb[0] = htonl(1U << 31); ocb->orb[1] = 0; ocb->orb[2] = htonl(((sbp->fd.fc->nodeid | FWLOCALBUS )<< 16) ); ocb->orb[3] = htonl(ocb->bus_addr + IND_PTR_OFFSET); diff --git a/sys/dev/firewire/sbp.h b/sys/dev/firewire/sbp.h index fcfa514..84d522a 100644 --- a/sys/dev/firewire/sbp.h +++ b/sys/dev/firewire/sbp.h @@ -35,7 +35,7 @@ * */ -#define ORB_NOTIFY (1 << 31) +#define ORB_NOTIFY (1U << 31) #define ORB_FMT_STD (0 << 29) #define ORB_FMT_VED (2 << 29) #define ORB_FMT_NOP (3 << 29) diff --git a/sys/dev/firewire/sbp_targ.c b/sys/dev/firewire/sbp_targ.c index f3434dd..8026b79 100644 --- a/sys/dev/firewire/sbp_targ.c +++ b/sys/dev/firewire/sbp_targ.c @@ -1716,7 +1716,7 @@ sbp_targ_pointer_handler(struct fw_xfer *xfer) orb0 = ntohl(orbi->orb[0]); orb1 = ntohl(orbi->orb[1]); - if ((orb0 & (1 << 31)) != 0) { + if ((orb0 & (1U << 31)) != 0) { printf("%s: invalid pointer\n", __func__); goto done; } diff --git a/sys/dev/hatm/if_hatmreg.h b/sys/dev/hatm/if_hatmreg.h index 9085f07..4014998 100644 --- a/sys/dev/hatm/if_hatmreg.h +++ b/sys/dev/hatm/if_hatmreg.h @@ -294,7 +294,7 @@ #define HE_REGO_CON_DAT 0x807F8 #define HE_REGO_CON_CTL 0x807FC -#define HE_REGM_CON_MBOX (2 << 30) +#define HE_REGM_CON_MBOX (2U << 30) #define HE_REGM_CON_TCM (1 << 30) #define HE_REGM_CON_RCM (0 << 30) #define HE_REGM_CON_WE (1 << 29) @@ -444,7 +444,7 @@ #define HE_REGM_TSR3_CRM (0xff << 0) #define HE_REGS_TSR3_CRM 0 -#define HE_REGM_TSR4_FLUSH (1 << 31) +#define HE_REGM_TSR4_FLUSH (1U << 31) #define HE_REGM_TSR4_SESS_END (1 << 30) #define HE_REGM_TSR4_OAM_CRC10 (1 << 28) #define HE_REGM_TSR4_NULL_CRC10 (1 << 27) @@ -475,7 +475,7 @@ #define HE_REGM_TSR13_CRM 0xffff #define HE_REGS_TSR13_CRM 0 -#define HE_REGM_TSR14_CBR_DELETE (1 << 31) +#define HE_REGM_TSR14_CBR_DELETE (1U << 31) #define HE_REGM_TSR14_ABR_CLOSE (1 << 16) /* diff --git a/sys/dev/hwpmc/hwpmc_piv.h b/sys/dev/hwpmc/hwpmc_piv.h index ebde966..4faeadd 100644 --- a/sys/dev/hwpmc/hwpmc_piv.h +++ b/sys/dev/hwpmc/hwpmc_piv.h @@ -39,7 +39,7 @@ #define P4_MAX_ESCR_PER_EVENT 2 #define P4_MAX_PMC_PER_ESCR 3 -#define P4_CCCR_OVF (1 << 31) +#define P4_CCCR_OVF (1U << 31) #define P4_CCCR_CASCADE (1 << 30) #define P4_CCCR_OVF_PMI_T1 (1 << 27) #define P4_CCCR_OVF_PMI_T0 (1 << 26) diff --git a/sys/dev/iwn/if_iwnreg.h b/sys/dev/iwn/if_iwnreg.h index 911407b..1429847 100644 --- a/sys/dev/iwn/if_iwnreg.h +++ b/sys/dev/iwn/if_iwnreg.h @@ -198,7 +198,7 @@ #define IWN_RESET_SW (1 << 7) #define IWN_RESET_MASTER_DISABLED (1 << 8) #define IWN_RESET_STOP_MASTER (1 << 9) -#define IWN_RESET_LINK_PWR_MGMT_DIS (1 << 31) +#define IWN_RESET_LINK_PWR_MGMT_DIS (1U << 31) /* Possible flags for register IWN_GP_CNTRL. */ #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) @@ -262,7 +262,7 @@ static const struct { /* Possible flags for register IWN_DRAM_INT_TBL. */ #define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) -#define IWN_DRAM_INT_TBL_ENABLE (1 << 31) +#define IWN_DRAM_INT_TBL_ENABLE (1U << 31) /* Possible values for register IWN_ANA_PLL. */ #define IWN_ANA_PLL_INIT 0x00880300 @@ -272,7 +272,7 @@ static const struct { /* Possible flags for register IWN_BSM_WR_CTRL. */ #define IWN_BSM_WR_CTRL_START_EN (1 << 30) -#define IWN_BSM_WR_CTRL_START (1 << 31) +#define IWN_BSM_WR_CTRL_START (1U << 31) /* Possible flags for register IWN_INT. */ #define IWN_INT_ALIVE (1 << 0) @@ -285,7 +285,7 @@ static const struct { #define IWN_INT_FH_TX (1 << 27) #define IWN_INT_RX_PERIODIC (1 << 28) #define IWN_INT_HW_ERR (1 << 29) -#define IWN_INT_FH_RX (1 << 31) +#define IWN_INT_FH_RX (1U << 31) /* Shortcut. */ #define IWN_INT_MASK_DEF \ @@ -305,7 +305,7 @@ static const struct { /* Possible flags/values for register IWN_FH_TX_CONFIG. */ #define IWN_FH_TX_CONFIG_DMA_PAUSE 0 -#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) +#define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ @@ -320,7 +320,7 @@ static const struct { #define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) /* Possible flags for register IWN_FH_RX_CONFIG. */ -#define IWN_FH_RX_CONFIG_ENA (1 << 31) +#define IWN_FH_RX_CONFIG_ENA (1U << 31) #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) @@ -329,7 +329,7 @@ static const struct { #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) /* Possible flags for register IWN_FH_TX_CONFIG. */ -#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) +#define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) /* Possible flags for register IWN_EEPROM. */ @@ -377,7 +377,7 @@ static const struct { #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ -#define IWN_FW_UPDATED (1 << 31) +#define IWN_FW_UPDATED (1U << 31) #define IWN_SCHED_WINSZ 64 #define IWN_SCHED_LIMIT 64 diff --git a/sys/dev/mge/if_mgevar.h b/sys/dev/mge/if_mgevar.h index f884fc8..0ab28bf 100644 --- a/sys/dev/mge/if_mgevar.h +++ b/sys/dev/mge/if_mgevar.h @@ -262,7 +262,7 @@ struct mge_softc { #define MGE_PORT_INT_RXQ0 (1 << 2) #define MGE_PORT_INT_RXERR (1 << 10) #define MGE_PORT_INT_RXERRQ0 (1 << 11) -#define MGE_PORT_INT_SUM (1 << 31) +#define MGE_PORT_INT_SUM (1U << 31) #define MGE_PORT_INT_CAUSE_EXT 0x464 #define MGE_PORT_INT_MASK_EXT 0x46C @@ -273,7 +273,7 @@ struct mge_softc { #define MGE_PORT_INT_EXT_TXUR (1 << 19) #define MGE_PORT_INT_EXT_LC (1 << 20) #define MGE_PORT_INT_EXT_IAR (1 << 23) -#define MGE_PORT_INT_EXT_SUM (1 << 31) +#define MGE_PORT_INT_EXT_SUM (1U << 31) #define MGE_RX_FIFO_URGENT_TRSH 0x470 #define MGE_TX_FIFO_URGENT_TRSH 0x474 @@ -330,7 +330,7 @@ struct mge_softc { #define MGE_RX_DESC_FIRST (1 << 27) #define MGE_RX_ENABLE_INT (1 << 29) #define MGE_RX_L4_CSUM_OK (1 << 30) -#define MGE_DMA_OWNED (1 << 31) +#define MGE_DMA_OWNED (1U << 31) #define MGE_RX_IP_FRAGMENT (1 << 2) diff --git a/sys/dev/mpt/mpt_cam.c b/sys/dev/mpt/mpt_cam.c index fa68d6b..f119a09 100644 --- a/sys/dev/mpt/mpt_cam.c +++ b/sys/dev/mpt/mpt_cam.c @@ -1431,7 +1431,7 @@ bad: /* SAS1078 36GB limitation WAR */ if (mpt->is_1078 && (((uint64_t)dm_segs->ds_addr + MPI_SGE_LENGTH(se->FlagsLength)) >> 32) == 9) { - addr |= (1 << 31); + addr |= (1U << 31); tf |= MPI_SGE_FLAGS_LOCAL_ADDRESS; } se->Address.High = htole32(addr); @@ -1554,7 +1554,7 @@ bad: (((uint64_t)dm_segs->ds_addr + MPI_SGE_LENGTH(se->FlagsLength)) >> 32) == 9) { - addr |= (1 << 31); + addr |= (1U << 31); tf |= MPI_SGE_FLAGS_LOCAL_ADDRESS; } se->Address.High = htole32(addr); diff --git a/sys/dev/msk/if_mskreg.h b/sys/dev/msk/if_mskreg.h index 5465deb..41a6eb7 100644 --- a/sys/dev/msk/if_mskreg.h +++ b/sys/dev/msk/if_mskreg.h @@ -156,7 +156,7 @@ #define DEVICEID_DLINK_DGE560SX 0x4002 #define DEVICEID_DLINK_DGE560T 0x4b00 -#define BIT_31 (1 << 31) +#define BIT_31 (1U << 31) #define BIT_30 (1 << 30) #define BIT_29 (1 << 29) #define BIT_28 (1 << 28) diff --git a/sys/dev/mvs/mvs.h b/sys/dev/mvs/mvs.h index 4938fb4..69a7c96 100644 --- a/sys/dev/mvs/mvs.h +++ b/sys/dev/mvs/mvs.h @@ -141,7 +141,7 @@ #define EDMA_IE_LINKDATARXERR(x) ((x) << 17) /* Link Data Recv Err */ #define EDMA_IE_LINKCTLTXERR(x) ((x) << 21) /* Link Ctrl Tx Error */ #define EDMA_IE_LINKDATATXERR(x) ((x) << 26) /* Link Data Tx Error */ -#define EDMA_IE_TRANSPROTERR (1 << 31) /* Transport Proto E */ +#define EDMA_IE_TRANSPROTERR (1U << 31) /* Transport Proto E */ #define EDMA_IE_TRANSIENT (EDMA_IE_LINKCTLRXERR(0x0b) | \ EDMA_IE_LINKCTLTXERR(0x1f)) /* Non-fatal Errors */ diff --git a/sys/dev/mxge/mxge_mcp.h b/sys/dev/mxge/mxge_mcp.h index 5a3fa56..365357e 100644 --- a/sys/dev/mxge/mxge_mcp.h +++ b/sys/dev/mxge/mxge_mcp.h @@ -226,7 +226,7 @@ enum myri10ge_mcp_cmd_type { a power of 2 number of entries. */ MXGEFW_CMD_SET_INTRQ_SIZE = 13, /* in bytes */ -#define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1 << 31) +#define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1U << 31) /* command to bring ethernet interface up. Above parameters (plus mtu & mac address) must have been exchanged prior diff --git a/sys/dev/qlxge/qls_dump.c b/sys/dev/qlxge/qls_dump.c index 44866ac..f829a85 100644 --- a/sys/dev/qlxge/qls_dump.c +++ b/sys/dev/qlxge/qls_dump.c @@ -111,7 +111,7 @@ enum Q81_PAUSE_FRM_DEST_LO = 0x00000128, Q81_PAUSE_FRM_DEST_HI = 0x0000012c, Q81_MAC_TX_PARAMS = 0x00000134, - Q81_MAC_TX_PARAMS_JUMBO = (1 << 31), /*Control*/ + Q81_MAC_TX_PARAMS_JUMBO = (1U << 31), /*Control*/ Q81_MAC_TX_PARAMS_SIZE_SHIFT = 16, /*Control*/ Q81_MAC_RX_PARAMS = 0x00000138, Q81_MAC_SYS_INT = 0x00000144, diff --git a/sys/dev/ral/rt2560reg.h b/sys/dev/ral/rt2560reg.h index 8e501b4..6860d1e 100644 --- a/sys/dev/ral/rt2560reg.h +++ b/sys/dev/ral/rt2560reg.h @@ -268,7 +268,7 @@ struct rt2560_rx_desc { #define RT2560_BBP_BUSY (1 << 15) #define RT2560_BBP_WRITE (1 << 16) #define RT2560_RF_20BIT (20 << 24) -#define RT2560_RF_BUSY (1 << 31) +#define RT2560_RF_BUSY (1U << 31) #define RT2560_RF_2522 0x00 #define RT2560_RF_2523 0x01 diff --git a/sys/dev/ral/rt2661reg.h b/sys/dev/ral/rt2661reg.h index b4325b0..3bed3d1 100644 --- a/sys/dev/ral/rt2661reg.h +++ b/sys/dev/ral/rt2661reg.h @@ -182,7 +182,7 @@ /* possible flags for register PHY_CSR4 */ #define RT2661_RF_21BIT (21 << 24) -#define RT2661_RF_BUSY (1 << 31) +#define RT2661_RF_BUSY (1U << 31) /* possible values for register STA_CSR4 */ #define RT2661_TX_STAT_VALID (1 << 0) diff --git a/sys/dev/ral/rt2860reg.h b/sys/dev/ral/rt2860reg.h index 06c275d..fe9fb4f 100644 --- a/sys/dev/ral/rt2860reg.h +++ b/sys/dev/ral/rt2860reg.h @@ -258,7 +258,7 @@ #define RT2860_TX_DMA_EN (1 << 0) /* possible flags for register DELAY_INT_CFG */ -#define RT2860_TXDLY_INT_EN (1 << 31) +#define RT2860_TXDLY_INT_EN (1U << 31) #define RT2860_TXMAX_PINT_SHIFT 24 #define RT2860_TXMAX_PTIME_SHIFT 16 #define RT2860_RXDLY_INT_EN (1 << 15) @@ -270,7 +270,7 @@ #define RT2860_GPIO_O_SHIFT 0 /* possible flags for register USB_DMA_CFG */ -#define RT2860_USB_TX_BUSY (1 << 31) +#define RT2860_USB_TX_BUSY (1U << 31) #define RT2860_USB_RX_BUSY (1 << 30) #define RT2860_USB_EPOUT_VLD_SHIFT 24 #define RT2860_USB_TX_EN (1 << 23) @@ -370,7 +370,7 @@ #define RT2860_TX0Q_PCNT_MASK 0x000000ff /* possible flags for register CAP_CTRL */ -#define RT2860_CAP_ADC_FEQ (1 << 31) +#define RT2860_CAP_ADC_FEQ (1U << 31) #define RT2860_CAP_START (1 << 30) #define RT2860_MAN_TRIG (1 << 29) #define RT2860_TRIG_OFFSET_SHIFT 16 @@ -381,7 +381,7 @@ #define RT3070_RF_WRITE (1 << 16) /* possible flags for register EFUSE_CTRL */ -#define RT3070_SEL_EFUSE (1 << 31) +#define RT3070_SEL_EFUSE (1U << 31) #define RT3070_EFSROM_KICK (1 << 30) #define RT3070_EFSROM_AIN_MASK 0x03ff0000 #define RT3070_EFSROM_AIN_SHIFT 16 @@ -420,7 +420,7 @@ #define RT2860_BBP_DATA_SHIFT 0 /* possible flags for register RF_CSR_CFG0 */ -#define RT2860_RF_REG_CTRL (1 << 31) +#define RT2860_RF_REG_CTRL (1U << 31) #define RT2860_RF_LE_SEL1 (1 << 30) #define RT2860_RF_LE_STBY (1 << 29) #define RT2860_RF_REG_WIDTH_SHIFT 24 @@ -455,7 +455,7 @@ #define RT2860_SLOT_TIME 0 /* possible flags for register NAV_TIME_CFG */ -#define RT2860_NAV_UPD (1 << 31) +#define RT2860_NAV_UPD (1U << 31) #define RT2860_NAV_UPD_VAL_SHIFT 16 #define RT2860_NAV_CLR_EN (1 << 15) #define RT2860_NAV_TIMER_SHIFT 0 @@ -509,7 +509,7 @@ #define RT2860_WAKEUP_LEAD_TIME_SHIFT 0 /* possible flags for register TX_PIN_CFG */ -#define RT3593_LNA_PE_G2_POL (1 << 31) +#define RT3593_LNA_PE_G2_POL (1U << 31) #define RT3593_LNA_PE_A2_POL (1 << 30) #define RT3593_LNA_PE_G2_EN (1 << 29) #define RT3593_LNA_PE_A2_EN (1 << 28) diff --git a/sys/dev/sound/pci/hda/hdaa.h b/sys/dev/sound/pci/hda/hdaa.h index e24575d..a85e14f 100644 --- a/sys/dev/sound/pci/hda/hdaa.h +++ b/sys/dev/sound/pci/hda/hdaa.h @@ -56,7 +56,7 @@ #define HDAA_QUIRK_IVREF100 (1 << 28) #define HDAA_QUIRK_OVREF50 (1 << 29) #define HDAA_QUIRK_OVREF80 (1 << 30) -#define HDAA_QUIRK_OVREF100 (1 << 31) +#define HDAA_QUIRK_OVREF100 (1U << 31) #define HDAA_QUIRK_IVREF (HDAA_QUIRK_IVREF50 | HDAA_QUIRK_IVREF80 | \ HDAA_QUIRK_IVREF100) diff --git a/sys/dev/usb/controller/ehci.h b/sys/dev/usb/controller/ehci.h index 6fba4d4..808ff9f 100644 --- a/sys/dev/usb/controller/ehci.h +++ b/sys/dev/usb/controller/ehci.h @@ -90,7 +90,7 @@ struct ehci_itd { #define EHCI_ITD_GET_PG(x) (((x) >> 12) & 0x7) #define EHCI_ITD_SET_OFFS(x) (x) #define EHCI_ITD_GET_OFFS(x) (((x) >> 0) & 0xFFF) -#define EHCI_ITD_ACTIVE (1 << 31) +#define EHCI_ITD_ACTIVE (1U << 31) #define EHCI_ITD_DATABUFERR (1 << 30) #define EHCI_ITD_BABBLE (1 << 29) #define EHCI_ITD_XACTERR (1 << 28) @@ -126,7 +126,7 @@ struct ehci_sitd { volatile uint32_t sitd_next; volatile uint32_t sitd_portaddr; #define EHCI_SITD_SET_DIR_OUT (0 << 31) -#define EHCI_SITD_SET_DIR_IN (1 << 31) +#define EHCI_SITD_SET_DIR_IN (1U << 31) #define EHCI_SITD_SET_ADDR(x) (x) #define EHCI_SITD_GET_ADDR(x) ((x) & 0x7F) #define EHCI_SITD_SET_ENDPT(x) ((x) << 8) diff --git a/sys/dev/usb/wlan/if_rumreg.h b/sys/dev/usb/wlan/if_rumreg.h index 75a51bc..44e627a 100644 --- a/sys/dev/usb/wlan/if_rumreg.h +++ b/sys/dev/usb/wlan/if_rumreg.h @@ -139,7 +139,7 @@ #define RT2573_BBP_BUSY (1 << 16) /* possible flags for register PHY_CSR4 */ #define RT2573_RF_20BIT (20 << 24) -#define RT2573_RF_BUSY (1 << 31) +#define RT2573_RF_BUSY (1U << 31) /* LED values */ #define RT2573_LED_RADIO (1 << 8) diff --git a/sys/dev/usb/wlan/if_runreg.h b/sys/dev/usb/wlan/if_runreg.h index f810f4a..2fb7b8c 100644 --- a/sys/dev/usb/wlan/if_runreg.h +++ b/sys/dev/usb/wlan/if_runreg.h @@ -253,7 +253,7 @@ #define RT2860_TX_DMA_EN (1 << 0) /* possible flags for register DELAY_INT_CFG */ -#define RT2860_TXDLY_INT_EN (1 << 31) +#define RT2860_TXDLY_INT_EN (1U << 31) #define RT2860_TXMAX_PINT_SHIFT 24 #define RT2860_TXMAX_PTIME_SHIFT 16 #define RT2860_RXDLY_INT_EN (1 << 15) @@ -265,7 +265,7 @@ #define RT2860_GPIO_O_SHIFT 0 /* possible flags for register USB_DMA_CFG */ -#define RT2860_USB_TX_BUSY (1 << 31) +#define RT2860_USB_TX_BUSY (1U << 31) #define RT2860_USB_RX_BUSY (1 << 30) #define RT2860_USB_EPOUT_VLD_SHIFT 24 #define RT2860_USB_TX_EN (1 << 23) @@ -365,7 +365,7 @@ #define RT2860_TX0Q_PCNT_MASK 0x000000ff /* possible flags for register CAP_CTRL */ -#define RT2860_CAP_ADC_FEQ (1 << 31) +#define RT2860_CAP_ADC_FEQ (1U << 31) #define RT2860_CAP_START (1 << 30) #define RT2860_MAN_TRIG (1 << 29) #define RT2860_TRIG_OFFSET_SHIFT 16 @@ -376,7 +376,7 @@ #define RT3070_RF_WRITE (1 << 16) /* possible flags for register EFUSE_CTRL */ -#define RT3070_SEL_EFUSE (1 << 31) +#define RT3070_SEL_EFUSE (1U << 31) #define RT3070_EFSROM_KICK (1 << 30) #define RT3070_EFSROM_AIN_MASK 0x03ff0000 #define RT3070_EFSROM_AIN_SHIFT 16 @@ -418,7 +418,7 @@ #define RT2860_BBP_DATA_SHIFT 0 /* possible flags for register RF_CSR_CFG0 */ -#define RT2860_RF_REG_CTRL (1 << 31) +#define RT2860_RF_REG_CTRL (1U << 31) #define RT2860_RF_LE_SEL1 (1 << 30) #define RT2860_RF_LE_STBY (1 << 29) #define RT2860_RF_REG_WIDTH_SHIFT 24 @@ -453,7 +453,7 @@ #define RT2860_SLOT_TIME 0 /* possible flags for register NAV_TIME_CFG */ -#define RT2860_NAV_UPD (1 << 31) +#define RT2860_NAV_UPD (1U << 31) #define RT2860_NAV_UPD_VAL_SHIFT 16 #define RT2860_NAV_CLR_EN (1 << 15) #define RT2860_NAV_TIMER_SHIFT 0 diff --git a/sys/dev/usb/wlan/if_uralreg.h b/sys/dev/usb/wlan/if_uralreg.h index 042cf5a..3554fe6 100644 --- a/sys/dev/usb/wlan/if_uralreg.h +++ b/sys/dev/usb/wlan/if_uralreg.h @@ -197,7 +197,7 @@ struct ural_rx_desc { } __packed; #define RAL_RF_LOBUSY (1 << 15) -#define RAL_RF_BUSY (1 << 31) +#define RAL_RF_BUSY (1U << 31) #define RAL_RF_20BIT (20 << 24) #define RAL_RF1 0 diff --git a/sys/dev/usb/wlan/if_urtwreg.h b/sys/dev/usb/wlan/if_urtwreg.h index a0fe5ff..09dd597 100644 --- a/sys/dev/usb/wlan/if_urtwreg.h +++ b/sys/dev/usb/wlan/if_urtwreg.h @@ -72,7 +72,7 @@ #define URTW_TX_HWMASK (7 << 25) #define URTW_TX_DISREQQSIZE (1 << 28) #define URTW_TX_HW_SEQNUM (1 << 30) -#define URTW_TX_CWMIN (1 << 31) +#define URTW_TX_CWMIN (1U << 31) #define URTW_TX_NOICV (0x80000) #define URTW_RX 0x0044 /* 4 byte */ #define URTW_RX_9356SEL (1 << 6) @@ -106,7 +106,7 @@ #define URTW_MAX_RX_DMA_2048 (7 << URTW_MAX_RX_DMA_SHIFT) #define URTW_MAX_RX_DMA_1024 (6) #define URTW_MAX_RX_DMA_SHIFT (10) -#define URTW_RCR_ONLYERLPKT (1 << 31) +#define URTW_RCR_ONLYERLPKT (1U << 31) #define URTW_INT_TIMEOUT 0x0048 /* 4 byte */ #define URTW_INT_TBDA 0x004c /* 4 byte */ #define URTW_EPROM_CMD 0x0050 /* 1 byte */ @@ -330,7 +330,7 @@ struct urtw_8187b_rxhdr { #define URTW_RX_FLAG_LAST (1 << 28) #define URTW_RX_FLAG_FIRST (1 << 29) #define URTW_RX_FLAG_EOR (1 << 30) -#define URTW_RX_FLAG_OWN (1 << 31) +#define URTW_RX_FLAG_OWN (1U << 31) uint64_t mactime; uint8_t noise; uint8_t rssi; @@ -367,7 +367,7 @@ struct urtw_8187b_txhdr { #define URTW_TX_FLAG_LAST (1 << 28) #define URTW_TX_FLAG_FIRST (1 << 29) #define URTW_TX_FLAG_DMA (1 << 30) -#define URTW_TX_FLAG_OWN (1 << 31) +#define URTW_TX_FLAG_OWN (1U << 31) uint16_t rtsdur; uint16_t len; #define URTW_TX_LEN /* 0 ~ 14 bits */ diff --git a/sys/dev/usb/wlan/if_zydreg.h b/sys/dev/usb/wlan/if_zydreg.h index 06ba2ab..970a3e8 100644 --- a/sys/dev/usb/wlan/if_zydreg.h +++ b/sys/dev/usb/wlan/if_zydreg.h @@ -1007,7 +1007,7 @@ #define ZYD_FILTER_CTS (1 << 28) #define ZYD_FILTER_ACK (1 << 29) #define ZYD_FILTER_CFE (1 << 30) -#define ZYD_FILTER_CFE_A (1 << 31) +#define ZYD_FILTER_CFE_A (1U << 31) /* helpers for register ZYD_MAC_RXFILTER */ #define ZYD_FILTER_MONITOR 0xffffffff diff --git a/sys/dev/wpi/if_wpireg.h b/sys/dev/wpi/if_wpireg.h index 2ccc21f..df71b3d 100644 --- a/sys/dev/wpi/if_wpireg.h +++ b/sys/dev/wpi/if_wpireg.h @@ -143,7 +143,7 @@ /* possible flags for register WPI_UC_CTL */ #define WPI_UC_ENABLE (1 << 30) -#define WPI_UC_RUN (1 << 31) +#define WPI_UC_RUN (1U << 31) /* possible flags for register WPI_INTR_CSR */ #define WPI_ALIVE_INTR (1 << 0) @@ -151,7 +151,7 @@ #define WPI_SW_ERROR (1 << 25) #define WPI_TX_INTR (1 << 27) #define WPI_HW_ERROR (1 << 29) -#define WPI_RX_INTR (1 << 31) +#define WPI_RX_INTR (1U << 31) #define WPI_INTR_MASK \ (WPI_SW_ERROR | WPI_HW_ERROR | WPI_TX_INTR | WPI_RX_INTR | \ |
