- Move timerreg.h to <arch>/include and split i8253 specific defines into

  i8253reg.h, and add some defines to control a speaker.
- Move PPI related defines from i386/isa/spkr.c into ppireg.h and use them.
- Move IO_{PPI,TIMER} defines into ppireg.h and timerreg.h respectively.
- Use isa/isareg.h rather than <arch>/isa/isa.h.

Tested on: i386, pc98

2 files changed, 85 insertions, 35 deletions

diff --git a/sys/dev/ic/i8253reg.h b/sys/dev/ic/i8253reg.h
new file mode 100644
index 0000000..9401dc1
--- /dev/null
+++ b/sys/dev/ic/i8253reg.h
@@ -0,0 +1,78 @@
+/*-
+ * Copyright (c) 1993 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	from: Header: timerreg.h,v 1.2 93/02/28 15:08:58 mccanne Exp
+ * $FreeBSD$
+ */
+
+/*
+ * Register definitions for the Intel 8253 Programmable Interval Timer.
+ *
+ * This chip has three independent 16-bit down counters that can be
+ * read on the fly.  There are three mode registers and three countdown
+ * registers.  The countdown registers are addressed directly, via the
+ * first three I/O ports.  The three mode registers are accessed via
+ * the fourth I/O port, with two bits in the mode byte indicating the
+ * register.  (Why are hardware interfaces always so braindead?).
+ *
+ * To write a value into the countdown register, the mode register
+ * is first programmed with a command indicating the which byte of
+ * the two byte register is to be modified.  The three possibilities
+ * are load msb (TMR_MR_MSB), load lsb (TMR_MR_LSB), or load lsb then
+ * msb (TMR_MR_BOTH).
+ *
+ * To read the current value ("on the fly") from the countdown register,
+ * you write a "latch" command into the mode register, then read the stable
+ * value from the corresponding I/O port.  For example, you write
+ * TMR_MR_LATCH into the corresponding mode register.  Presumably,
+ * after doing this, a write operation to the I/O port would result
+ * in undefined behavior (but hopefully not fry the chip).
+ * Reading in this manner has no side effects.
+ */
+
+/*
+ * Macros for specifying values to be written into a mode register.
+ */
+#define	TIMER_REG_CNTR0	0	/* timer 0 counter port */
+#define	TIMER_REG_CNTR1	1	/* timer 1 counter port */
+#define	TIMER_REG_CNTR2	2	/* timer 2 counter port */
+#define	TIMER_REG_MODE		3	/* timer mode port */
+#define		TIMER_SEL0	0x00	/* select counter 0 */
+#define		TIMER_SEL1	0x40	/* select counter 1 */
+#define		TIMER_SEL2	0x80	/* select counter 2 */
+#define		TIMER_INTTC	0x00	/* mode 0, intr on terminal cnt */
+#define		TIMER_ONESHOT	0x02	/* mode 1, one shot */
+#define		TIMER_RATEGEN	0x04	/* mode 2, rate generator */
+#define		TIMER_SQWAVE	0x06	/* mode 3, square wave */
+#define		TIMER_SWSTROBE	0x08	/* mode 4, s/w triggered strobe */
+#define		TIMER_HWSTROBE	0x0a	/* mode 5, h/w triggered strobe */
+#define		TIMER_LATCH	0x00	/* latch counter for reading */
+#define		TIMER_LSB	0x10	/* r/w counter LSB */
+#define		TIMER_MSB	0x20	/* r/w counter MSB */
+#define		TIMER_16BIT	0x30	/* r/w counter 16 bits, LSB first */
+#define		TIMER_BCD	0x01	/* count in BCD */
diff --git a/sys/dev/speaker/spkr.c b/sys/dev/speaker/spkr.c
index 321b2cb..d265e7c 100644
--- a/sys/dev/speaker/spkr.c
+++ b/sys/dev/speaker/spkr.c
@@ -19,14 +19,10 @@ __FBSDID("$FreeBSD$");
 #include <sys/ctype.h>
 #include <sys/malloc.h>
 #include <isa/isavar.h>
-#ifdef PC98
-#include <pc98/cbus/cbus.h>
-#else
-#include <i386/isa/isa.h>
-#endif
-#include <i386/isa/timerreg.h>
 #include <machine/clock.h>
 #include <machine/speaker.h>
+#include <machine/ppireg.h>
+#include <machine/timerreg.h>
 
 static	d_open_t	spkropen;
 static	d_close_t	spkrclose;
@@ -58,34 +54,10 @@ static MALLOC_DEFINE(M_SPKR, "spkr", "Speaker buffer");
  * used to generate clicks (a square wave) of whatever frequency is desired.
  */
 
-/*
- * XXX PPI control values should be in a header and used in clock.c.
- */
 #ifdef PC98
 #define	SPKR_DESC	"PC98 speaker"
-#define	PPI_SPKR	0x08	/* turn these PPI bits on to pass sound */
-#define	PIT_COUNT	0x3fdb	/* PIT count address */
-
-#define	SPEAKER_ON	outb(IO_PPI, inb(IO_PPI) & ~PPI_SPKR)
-#define	SPEAKER_OFF	outb(IO_PPI, inb(IO_PPI) | PPI_SPKR)
-#define	TIMER_ACQUIRE	acquire_timer1(TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT)
-#define	TIMER_RELEASE	release_timer1()
-#define	SPEAKER_WRITE(val)	{ \
-					outb(PIT_COUNT, (val & 0xff)); \
-					outb(PIT_COUNT, (val >> 8)); \
-				}
 #else
 #define	SPKR_DESC	"PC speaker"
-#define PPI_SPKR	0x03	/* turn these PPI bits on to pass sound */
-
-#define	SPEAKER_ON	outb(IO_PPI, inb(IO_PPI) | PPI_SPKR)
-#define	SPEAKER_OFF	outb(IO_PPI, inb(IO_PPI) & ~PPI_SPKR)
-#define	TIMER_ACQUIRE	acquire_timer2(TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT)
-#define	TIMER_RELEASE	release_timer2()
-#define	SPEAKER_WRITE(val)	{ \
-					outb(TIMER_CNTR2, (val & 0xff)); \
-    					outb(TIMER_CNTR2, (val >> 8)); \
-				}
 #endif
 
 #define SPKRPRI PSOCK
@@ -117,18 +89,18 @@ tone(thz, ticks)
     /* set timer to generate clicks at given frequency in Hertz */
     sps = splclock();
 
-    if (TIMER_ACQUIRE) {
+    if (timer_spkr_acquire()) {
 	/* enter list of waiting procs ??? */
 	splx(sps);
 	return;
     }
     splx(sps);
     disable_intr();
-    SPEAKER_WRITE(divisor);
+    spkr_set_pitch(divisor);
     enable_intr();
 
     /* turn the speaker on */
-    SPEAKER_ON;
+    ppi_spkr_on();
 
     /*
      * Set timeout to endtone function, then give up the timeslice.
@@ -137,9 +109,9 @@ tone(thz, ticks)
      */
     if (ticks > 0)
 	tsleep(&endtone, SPKRPRI | PCATCH, "spkrtn", ticks);
-    SPEAKER_OFF;
+    ppi_spkr_off();
     sps = splclock();
-    TIMER_RELEASE;
+    timer_spkr_release();
     splx(sps);
 }