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| author | adrian <adrian@FreeBSD.org> | 2011-02-07 21:30:13 +0000 |
|---|---|---|
| committer | adrian <adrian@FreeBSD.org> | 2011-02-07 21:30:13 +0000 |
| commit | 9e9e958fff214c281cce442f5cc89eb0e51c61d2 (patch) | |
| tree | caf7039cae5ccac53d1b04a1d277459a5bbbf9e6 /sys/dev | |
| parent | 365538a229a5a42c6c4aed58dcfbc8e8228a66df (diff) | |
| download | FreeBSD-src-9e9e958fff214c281cce442f5cc89eb0e51c61d2.zip FreeBSD-src-9e9e958fff214c281cce442f5cc89eb0e51c61d2.tar.gz | |
Add a new RMW macro for analog register writes which implements the needed
wait period between operations.
Diffstat (limited to 'sys/dev')
| -rw-r--r-- | sys/dev/ath/ath_hal/ah_internal.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/sys/dev/ath/ath_hal/ah_internal.h b/sys/dev/ath/ath_hal/ah_internal.h index f8c157d..f3fd9e8 100644 --- a/sys/dev/ath/ath_hal/ah_internal.h +++ b/sys/dev/ath/ath_hal/ah_internal.h @@ -466,6 +466,10 @@ isBigEndian(void) #define OS_REG_CLR_BIT(_a, _r, _f) \ OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) +/* Analog register writes may require a delay between each one (eg Merlin?) */ +#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ + do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) + /* system-configurable parameters */ extern int ath_hal_dma_beacon_response_time; /* in TU's */ extern int ath_hal_sw_beacon_response_time; /* in TU's */ |
