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authoradrian <adrian@FreeBSD.org>2011-10-18 03:32:18 +0000
committeradrian <adrian@FreeBSD.org>2011-10-18 03:32:18 +0000
commit6876e3d9c139cd8d3dbaaaaf463d9a1ff2103a5e (patch)
treec3d7cb68ac3056601403d39ec6dec6316c172f97 /sys/dev
parente6dc2dfa1d7d11868787f5f0c8b98189ade9123c (diff)
downloadFreeBSD-src-6876e3d9c139cd8d3dbaaaaf463d9a1ff2103a5e.zip
FreeBSD-src-6876e3d9c139cd8d3dbaaaaf463d9a1ff2103a5e.tar.gz
Add in a currently-disabled WAR for PCI NICs.
Some earlier series (~AR5212?) play badly with BIOSes. In these instances, they may require a forced reset (by transitioning the NIC through D0 -> D3 -> D0) before they probe/attach correctly. This is currently disabled because: * I haven't figured out the "right" code to ensure this only happens for PCI NICs (not PCIe or Cardbus); * I haven't at all done wide scale testing for this, and I'm not yet ready for said wide-scale testing. I'm documenting this primarily so users with misbehaving NICs have something to tinker with. Obtained from: Atheros
Diffstat (limited to 'sys/dev')
-rw-r--r--sys/dev/ath/if_ath_pci.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/sys/dev/ath/if_ath_pci.c b/sys/dev/ath/if_ath_pci.c
index 531c79a..4824773 100644
--- a/sys/dev/ath/if_ath_pci.c
+++ b/sys/dev/ath/if_ath_pci.c
@@ -73,10 +73,27 @@ struct ath_pci_softc {
#define BS_BAR 0x10
#define PCIR_RETRY_TIMEOUT 0x41
+#define PCIR_CFG_PMCSR 0x48
static void
ath_pci_setup(device_t dev)
{
+ /* Override the system latency timer */
+ pci_write_config(dev, PCIR_LATTIMER, 0x80, 1);
+
+ /* If a PCI NIC, force wakeup */
+#ifdef ATH_PCI_WAKEUP_WAR
+ /* XXX TODO: don't do this for non-PCI (ie, PCIe, Cardbus!) */
+ if (1) {
+ uint16_t pmcsr;
+ pmcsr = pci_read_config(dev, PCIR_CFG_PMCSR, 2);
+ pmcsr |= 3;
+ pci_write_config(dev, PCIR_CFG_PMCSR, pmcsr, 2);
+ pmcsr &= ~3;
+ pci_write_config(dev, PCIR_CFG_PMCSR, pmcsr, 2);
+ }
+#endif
+
/*
* Disable retry timeout to keep PCI Tx retries from
* interfering with C3 CPU state.
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