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authornwhitehorn <nwhitehorn@FreeBSD.org>2010-10-25 15:51:43 +0000
committernwhitehorn <nwhitehorn@FreeBSD.org>2010-10-25 15:51:43 +0000
commit53d1ac9cef0952eb585a3ca03d8fa0c9304937af (patch)
tree3974f47cd624b0107f10f737bf825b4b9e4b50b9 /sys/dev
parentbb087fec9659d1b0ca5814b5eabcd56d1234ea5c (diff)
downloadFreeBSD-src-53d1ac9cef0952eb585a3ca03d8fa0c9304937af.zip
FreeBSD-src-53d1ac9cef0952eb585a3ca03d8fa0c9304937af.tar.gz
The EHCI_CAPLENGTH and EHCI_HCIVERSION registers are actually sub-registers
within the first 4 bytes of the EHCI memory space. For controllers that use big-endian MMIO, reading them with 1- and 2-byte reads would then return the wrong values. Instead, read the combined register with a 4-byte read and mask out the interesting quantities.
Diffstat (limited to 'sys/dev')
-rw-r--r--sys/dev/pci/pci.c2
-rw-r--r--sys/dev/usb/controller/ehci.c4
-rw-r--r--sys/dev/usb/controller/ehcireg.h10
3 files changed, 10 insertions, 6 deletions
diff --git a/sys/dev/pci/pci.c b/sys/dev/pci/pci.c
index ef80f81..6069b6d 100644
--- a/sys/dev/pci/pci.c
+++ b/sys/dev/pci/pci.c
@@ -2803,7 +2803,7 @@ ehci_early_takeover(device_t self)
"SMM does not respond\n");
}
/* Disable interrupts */
- offs = bus_read_1(res, EHCI_CAPLENGTH);
+ offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION));
bus_write_4(res, offs + EHCI_USBINTR, 0);
}
bus_release_resource(self, SYS_RES_MEMORY, rid, res);
diff --git a/sys/dev/usb/controller/ehci.c b/sys/dev/usb/controller/ehci.c
index 9111982..329c9d8 100644
--- a/sys/dev/usb/controller/ehci.c
+++ b/sys/dev/usb/controller/ehci.c
@@ -270,9 +270,9 @@ ehci_init(ehci_softc_t *sc)
}
#endif
- sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
+ sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
- version = EREAD2(sc, EHCI_HCIVERSION);
+ version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n",
version >> 8, version & 0xff);
diff --git a/sys/dev/usb/controller/ehcireg.h b/sys/dev/usb/controller/ehcireg.h
index ab81f08..1f5fc5c 100644
--- a/sys/dev/usb/controller/ehcireg.h
+++ b/sys/dev/usb/controller/ehcireg.h
@@ -54,9 +54,13 @@
#define EHCI_LEGSUP_USBLEGCTLSTS 0x04
/* EHCI capability registers */
-#define EHCI_CAPLENGTH 0x00 /* RO Capability register length field */
-#define EHCI_RESERVED 0x01 /* Reserved register */
-#define EHCI_HCIVERSION 0x02 /* RO Interface version number */
+#define EHCI_CAPLEN_HCIVERSION 0x00 /* RO Capability register length
+ * (least-significant byte) and
+ * interface version number (two
+ * most significant)
+ */
+#define EHCI_CAPLENGTH(x) ((x) & 0xff)
+#define EHCI_HCIVERSION(x) (((x) >> 16) & 0xffff)
#define EHCI_HCSPARAMS 0x04 /* RO Structural parameters */
#define EHCI_HCS_DEBUGPORT(x) (((x) >> 20) & 0xf)
#define EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000)
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