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| author | yongari <yongari@FreeBSD.org> | 2008-07-16 08:35:29 +0000 |
|---|---|---|
| committer | yongari <yongari@FreeBSD.org> | 2008-07-16 08:35:29 +0000 |
| commit | 8949e679ff0b97525d3e24994d6b9a43c9feed24 (patch) | |
| tree | a11fafd52a6f1ab3762a10ac23765bed78651888 /sys/dev/vr/if_vrreg.h | |
| parent | dc88e0e3e5bb00766977203967a6f933644147e6 (diff) | |
| download | FreeBSD-src-8949e679ff0b97525d3e24994d6b9a43c9feed24.zip FreeBSD-src-8949e679ff0b97525d3e24994d6b9a43c9feed24.tar.gz | |
Fix a multicast handling regression on VT6105M introduced in
vr(4) overhauling(r177050).
It seems that filtering multicast addresses with multicast CAM
entries require accessing 'CAM enable bit' for each CAM entry.
Subsequent accessing multicast CAM control register without
toggling the 'CAM enable bit' seem to no effects.
In order to fix that separate CAM setup from CAM mask configuration
and CAM entry modification. While I'm here add VLAN CAM filtering
feature which will be enabled in future(FreeBSD now can receive
VLAN id insertion/removal event from vlan(4) on the fly).
For VT6105M hardware, explicitly disable VLAN hardware tag
insertion/stripping and enable VLAN CAM filtering for VLAN id 0.
This shall make non-VLAN frames set VR_RXSTAT_VIDHIT bit in Rx
status word.
Added multicast/VLAN CAM address definition to header file.
PR: kern/125010, kern/125024
MFC after: 1 week
Diffstat (limited to 'sys/dev/vr/if_vrreg.h')
| -rw-r--r-- | sys/dev/vr/if_vrreg.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/sys/dev/vr/if_vrreg.h b/sys/dev/vr/if_vrreg.h index a744786..9c85962 100644 --- a/sys/dev/vr/if_vrreg.h +++ b/sys/dev/vr/if_vrreg.h @@ -47,6 +47,14 @@ #define VR_IMR 0x0E /* interrupt mask register */ #define VR_MAR0 0x10 /* multicast hash 0 */ #define VR_MAR1 0x14 /* multicast hash 1 */ +#define VR_MCAM0 0x10 +#define VR_MCAM1 0x11 +#define VR_MCAM2 0x12 +#define VR_MCAM3 0x13 +#define VR_MCAM4 0x14 +#define VR_MCAM5 0x15 +#define VR_VCAM0 0x16 +#define VR_VCAM1 0x17 #define VR_RXADDR 0x18 /* rx descriptor list start addr */ #define VR_TXADDR 0x1C /* tx descriptor list start addr */ #define VR_CURRXDESC0 0x20 @@ -368,6 +376,7 @@ #define VR_BCR1_TXTHRESH512BYTES 0x20 #define VR_BCR1_TXTHRESH1024BYTES 0x28 #define VR_BCR1_TXTHRESHSTORENFWD 0x38 +#define VR_BCR1_VLANFILT_ENB 0x80 /* VT6105M */ /* * CAMCTL register bits. (VT6105M only) @@ -751,3 +760,6 @@ struct vr_softc { #define VR_SETBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) #define VR_CLRBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) + +#define VR_MCAST_CAM 0 +#define VR_VLAN_CAM 1 |
