Preparations for adding USB HOST mode to the DWC OTG driver.

Merge register file with external one and put all register
definitions in a separate file.

Submitted by:	ray @

3 files changed, 980 insertions, 506 deletions

diff --git a/sys/dev/usb/controller/dwc_otg.c b/sys/dev/usb/controller/dwc_otg.c
index e5310f2..09bd692 100644
--- a/sys/dev/usb/controller/dwc_otg.c
+++ b/sys/dev/usb/controller/dwc_otg.c
@@ -81,6 +81,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/usb/usb_bus.h>
 
 #include <dev/usb/controller/dwc_otg.h>
+#include <dev/usb/controller/dwc_otgreg.h>
 
 #define	DWC_OTG_BUS2SC(bus) \
    ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \
@@ -90,12 +91,12 @@ __FBSDID("$FreeBSD$");
    DWC_OTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
 
 #define	DWC_OTG_MSK_GINT_ENABLED	\
-   (DWC_OTG_MSK_GINT_ENUM_DONE |	\
-   DWC_OTG_MSK_GINT_USB_RESET |		\
-   DWC_OTG_MSK_GINT_USB_SUSPEND |	\
-   DWC_OTG_MSK_GINT_INEP |		\
-   DWC_OTG_MSK_GINT_RXFLVL |		\
-   DWC_OTG_MSK_GINT_SESSREQINT)
+   (GINTSTS_ENUMDONE |	\
+   GINTSTS_USBRST |		\
+   GINTSTS_USBSUSP |	\
+   GINTSTS_IEPINT |		\
+   GINTSTS_RXFLVL |		\
+   GINTSTS_SESSREQINT)
 
 #define DWC_OTG_USE_HSIC 0
 
@@ -172,7 +173,7 @@ dwc_otg_init_fifo(struct dwc_otg_softc *sc)
 	/* split equally for IN and OUT */
 	fifo_size /= 2;
 
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GRXFSIZ, fifo_size / 4);
+	DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4);
 
 	/* align to 4-bytes */
 	fifo_size &= ~3;
@@ -185,7 +186,7 @@ dwc_otg_init_fifo(struct dwc_otg_softc *sc)
 		return (EINVAL);
 	}
 
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GNPTXFSIZ, (0x10 << 16) | (tx_start / 4));
+	DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, (0x10 << 16) | (tx_start / 4));
 	fifo_size -= 0x40;
 	tx_start += 0x40;
 
@@ -210,7 +211,7 @@ dwc_otg_init_fifo(struct dwc_otg_softc *sc)
 			    (DWC_OTG_MAX_TXN / 2);
 
 			if (fifo_size >= limit) {
-				DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPTXF(x),
+				DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x),
 				    ((limit / 4) << 16) |
 				    (tx_start / 4));
 				tx_start += limit;
@@ -220,7 +221,7 @@ dwc_otg_init_fifo(struct dwc_otg_softc *sc)
 				pf->max_buffer = limit;
 
 			} else if (fifo_size >= 0x80) {
-				DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPTXF(x),
+				DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x),
 				    ((0x80 / 4) << 16) | (tx_start / 4));
 				tx_start += 0x80;
 				fifo_size -= 0x80;
@@ -229,7 +230,7 @@ dwc_otg_init_fifo(struct dwc_otg_softc *sc)
 
 			} else {
 				pf->usb.is_simplex = 1;
-				DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPTXF(x),
+				DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x),
 				    (0x0 << 16) | (tx_start / 4));
 			}
 		} else {
@@ -242,13 +243,13 @@ dwc_otg_init_fifo(struct dwc_otg_softc *sc)
 	}
 
 	/* reset RX FIFO */
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GRSTCTL,
-	    DWC_OTG_MSK_GRSTCTL_RXFFLUSH);
+	DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL,
+	    GRSTCTL_RXFFLSH);
 
 	/* reset all TX FIFOs */
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GRSTCTL,
-	   DWC_OTG_MSK_GRSTCTL_TXFIFO(0x10) |
-	   DWC_OTG_MSK_GRSTCTL_TXFFLUSH);
+	DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL,
+	   GRSTCTL_TXFIFO(0x10) |
+	   GRSTCTL_TXFFLSH);
 
 	return (0);
 }
@@ -291,9 +292,9 @@ dwc_otg_pull_up(struct dwc_otg_softc *sc)
 	    sc->sc_flags.port_powered) {
 		sc->sc_flags.d_pulled_up = 1;
 
-		temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DCTL);
-		temp &= ~DWC_OTG_MSK_DCTL_SOFT_DISC;
-		DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCTL, temp);
+		temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
+		temp &= ~DCTL_SFTDISCON;
+		DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
 	}
 }
 
@@ -307,9 +308,9 @@ dwc_otg_pull_down(struct dwc_otg_softc *sc)
 	if (sc->sc_flags.d_pulled_up) {
 		sc->sc_flags.d_pulled_up = 0;
 
-		temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DCTL);
-		temp |= DWC_OTG_MSK_DCTL_SOFT_DISC;
-		DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCTL, temp);
+		temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
+		temp |= DCTL_SFTDISCON;
+		DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
 	}
 }
 
@@ -325,9 +326,9 @@ dwc_otg_resume_irq(struct dwc_otg_softc *sc)
 		 * Disable resume interrupt and enable suspend
 		 * interrupt:
 		 */
-		sc->sc_irq_mask &= ~DWC_OTG_MSK_GINT_WKUPINT;
-		sc->sc_irq_mask |= DWC_OTG_MSK_GINT_USB_SUSPEND;
-		DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTMSK, sc->sc_irq_mask);
+		sc->sc_irq_mask &= ~GINTSTS_WKUPINT;
+		sc->sc_irq_mask |= GINTSTS_USBSUSP;
+		DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 
 		/* complete root HUB interrupt endpoint */
 		dwc_otg_root_intr(sc);
@@ -345,15 +346,15 @@ dwc_otg_wakeup_peer(struct dwc_otg_softc *sc)
 	DPRINTFN(5, "Remote wakeup\n");
 
 	/* enable remote wakeup signalling */
-	temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DCTL);
-	temp |= DWC_OTG_MSK_DCTL_REMOTE_WAKEUP;
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCTL, temp);
+	temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
+	temp |= DCTL_RMTWKUPSIG;
+	DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
 
 	/* Wait 8ms for remote wakeup to complete. */
 	usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
 
-	temp &= ~DWC_OTG_MSK_DCTL_REMOTE_WAKEUP;
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCTL, temp);
+	temp &= ~DCTL_RMTWKUPSIG;
+	DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
 
 	/* need to fake resume IRQ */
 	dwc_otg_resume_irq(sc);
@@ -366,10 +367,10 @@ dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr)
 
 	DPRINTFN(5, "addr=%d\n", addr);
 
-	temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DCFG);
-	temp &= ~DWC_OTG_MSK_DCFG_SET_DEV_ADDR(0x7F);
-	temp |= DWC_OTG_MSK_DCFG_SET_DEV_ADDR(addr);
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCFG, temp);
+	temp = DWC_OTG_READ_4(sc, DOTG_DCFG);
+	temp &= ~DCFG_DEVADDR_SET(0x7F);
+	temp |= DCFG_DEVADDR_SET(addr);
+	DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp);
 }
 
 static void
@@ -378,8 +379,8 @@ dwc_otg_common_rx_ack(struct dwc_otg_softc *sc)
 	DPRINTFN(5, "RX status clear\n");
 
 	/* enable RX FIFO level interrupt */
-	sc->sc_irq_mask |= DWC_OTG_MSK_GINT_RXFLVL;
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTMSK, sc->sc_irq_mask);
+	sc->sc_irq_mask |= GINTSTS_RXFLVL;
+	DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 
 	/* clear cached status */
 	sc->sc_last_rx_status = 0;
@@ -401,18 +402,18 @@ dwc_otg_setup_rx(struct dwc_otg_td *td)
 	if (sc->sc_last_rx_status == 0)
 		goto not_complete;
 
-	if (DWC_OTG_MSK_GRXSTS_GET_CHANNEL(sc->sc_last_rx_status) != 0)
+	if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0)
 		goto not_complete;
 
-	if ((sc->sc_last_rx_status & DWC_OTG_MSK_GRXSTS_PID) !=
-	    DWC_OTG_MSK_GRXSTS_PID_DATA0) {
+	if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) !=
+	    GRXSTSRD_DPID_DATA0) {
 		/* release FIFO */
 		dwc_otg_common_rx_ack(sc);
 		goto not_complete;
 	}
 
-	if ((sc->sc_last_rx_status & DWC_OTG_MSK_GRXSTS_PACKET_STS) !=
-	    DWC_OTG_MSK_GRXSTS_DEV_STP_DATA) {
+	if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
+	    GRXSTSRD_STP_DATA) {
 		/* release FIFO */
 		dwc_otg_common_rx_ack(sc);
 		goto not_complete;
@@ -424,7 +425,7 @@ dwc_otg_setup_rx(struct dwc_otg_td *td)
 	td->did_stall = 0;
 
 	/* get the packet byte count */
-	count = DWC_OTG_MSK_GRXSTS_GET_BYTE_CNT(sc->sc_last_rx_status);
+	count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status);
 
 	/* verify data length */
 	if (count != td->remainder) {
@@ -459,22 +460,22 @@ dwc_otg_setup_rx(struct dwc_otg_td *td)
 	}
 
 	/* don't send any data by default */
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPTSIZ(0),
-	    DWC_OTG_MSK_DXEPTSIZ_SET_NPKT(0) | 
-	    DWC_OTG_MSK_DXEPTSIZ_SET_NBYTES(0));
+	DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0),
+	    DXEPTSIZ_SET_NPKT(0) | 
+	    DXEPTSIZ_SET_NBYTES(0));
 
 	temp = sc->sc_in_ctl[0];
 
 	/* enable IN endpoint */
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPCTL(0),
-	    temp | DWC_OTG_MSK_DIEPCTL_ENABLE);
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPCTL(0),
-	    temp | DWC_OTG_MSK_DIEPCTL_SET_NAK);
+	DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0),
+	    temp | DIEPCTL_EPENA);
+	DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0),
+	    temp | DIEPCTL_SNAK);
 
 	/* reset IN endpoint buffer */
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GRSTCTL,
-	    DWC_OTG_MSK_GRSTCTL_TXFIFO(0) |
-	    DWC_OTG_MSK_GRSTCTL_TXFFLUSH);
+	DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL,
+	    GRSTCTL_TXFIFO(0) |
+	    GRSTCTL_TXFFLSH);
 
 	/* acknowledge RX status */
 	dwc_otg_common_rx_ack(sc);
@@ -485,11 +486,11 @@ not_complete:
 
 	temp = sc->sc_out_ctl[0];
 
-	temp |= DWC_OTG_MSK_DOEPCTL_ENABLE |
-	    DWC_OTG_MSK_DOEPCTL_SET_NAK;
+	temp |= DOEPCTL_EPENA |
+	    DOEPCTL_SNAK;
 
 	/* enable OUT endpoint */
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPCTL(0), temp);
+	DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), temp);
 
 	if (!td->did_stall) {
 		td->did_stall = 1;
@@ -497,21 +498,21 @@ not_complete:
 		DPRINTFN(5, "stalling IN and OUT direction\n");
 
 		/* set stall after enabling endpoint */
-		DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPCTL(0),
-		    temp | DWC_OTG_MSK_DOEPCTL_STALL);
+		DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0),
+		    temp | DOEPCTL_STALL);
 
 		temp = sc->sc_in_ctl[0];
 
 		/* set stall assuming endpoint is enabled */
-		DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPCTL(0),
-		    temp | DWC_OTG_MSK_DIEPCTL_STALL);
+		DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0),
+		    temp | DIEPCTL_STALL);
 	}
 
 	/* setup number of buffers to receive */
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPTSIZ(0),
-	    DWC_OTG_MSK_DXEPTSIZ_SET_MULTI(3) |
-	    DWC_OTG_MSK_DXEPTSIZ_SET_NPKT(1) | 
-	    DWC_OTG_MSK_DXEPTSIZ_SET_NBYTES(sizeof(req)));
+	DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0),
+	    DXEPTSIZ_SET_MULTI(3) |
+	    DXEPTSIZ_SET_NPKT(1) | 
+	    DXEPTSIZ_SET_NBYTES(sizeof(req)));
 
 	return (1);			/* not complete */
 }
@@ -533,12 +534,12 @@ dwc_otg_data_rx(struct dwc_otg_td *td)
 	if (sc->sc_last_rx_status == 0)
 		goto not_complete;
 
-	if (DWC_OTG_MSK_GRXSTS_GET_CHANNEL(sc->sc_last_rx_status) != td->ep_no)
+	if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no)
 		goto not_complete;
 
 	/* check for SETUP packet */
-	if ((sc->sc_last_rx_status & DWC_OTG_MSK_GRXSTS_PACKET_STS) ==
-	    DWC_OTG_MSK_GRXSTS_DEV_STP_DATA) {
+	if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) ==
+	    GRXSTSRD_STP_DATA) {
 		if (td->remainder == 0) {
 			/*
 			 * We are actually complete and have
@@ -554,15 +555,15 @@ dwc_otg_data_rx(struct dwc_otg_td *td)
 		return (0);		/* complete */
 	}
 
-	if ((sc->sc_last_rx_status & DWC_OTG_MSK_GRXSTS_PACKET_STS) !=
-	    DWC_OTG_MSK_GRXSTS_DEV_OUT_DATA) {
+	if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
+	    GRXSTSRD_OUT_DATA) {
 		/* release FIFO */
 		dwc_otg_common_rx_ack(sc);
 		goto not_complete;
 	}
 
 	/* get the packet byte count */
-	count = DWC_OTG_MSK_GRXSTS_GET_BYTE_CNT(sc->sc_last_rx_status);
+	count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status);
 
 	/* verify the packet byte count */
 	if (count != td->max_packet_size) {
@@ -609,22 +610,22 @@ not_complete:
 
 	temp = sc->sc_out_ctl[td->ep_no];
 
-	temp |= DWC_OTG_MSK_DOEPCTL_ENABLE |
-	    DWC_OTG_MSK_DOEPCTL_CLR_NAK;
+	temp |= DOEPCTL_EPENA |
+	    DOEPCTL_CNAK;
 
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPCTL(td->ep_no), temp);
+	DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp);
 
 	/* enable SETUP and transfer complete interrupt */
 	if (td->ep_no == 0) {
-		DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPTSIZ(0),
-		    DWC_OTG_MSK_DXEPTSIZ_SET_NPKT(1) | 
-		    DWC_OTG_MSK_DXEPTSIZ_SET_NBYTES(td->max_packet_size));
+		DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0),
+		    DXEPTSIZ_SET_NPKT(1) | 
+		    DXEPTSIZ_SET_NBYTES(td->max_packet_size));
 	} else {
 		/* allow reception of multiple packets */
-		DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPTSIZ(td->ep_no),
-		    DWC_OTG_MSK_DXEPTSIZ_SET_MULTI(1) |
-		    DWC_OTG_MSK_DXEPTSIZ_SET_NPKT(4) | 
-		    DWC_OTG_MSK_DXEPTSIZ_SET_NBYTES(4 *
+		DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no),
+		    DXEPTSIZ_SET_MULTI(1) |
+		    DXEPTSIZ_SET_NPKT(4) | 
+		    DXEPTSIZ_SET_NBYTES(4 *
 		    ((td->max_packet_size + 3) & ~3)));
 	}
 	return (1);			/* not complete */
@@ -654,10 +655,10 @@ repeat:
 	temp = sc->sc_last_rx_status;
 
 	if ((td->ep_no == 0) && (temp != 0) &&
-	    (DWC_OTG_MSK_GRXSTS_GET_CHANNEL(temp) == 0)) {
+	    (GRXSTSRD_CHNUM_GET(temp) == 0)) {
 
-		if ((temp & DWC_OTG_MSK_GRXSTS_PACKET_STS) !=
-		    DWC_OTG_MSK_GRXSTS_DEV_STP_DATA) {
+		if ((temp & GRXSTSRD_PKTSTS_MASK) !=
+		    GRXSTSRD_STP_DATA) {
 
 			/* dump data - wrong direction */
 			dwc_otg_common_rx_ack(sc);
@@ -677,10 +678,10 @@ repeat:
 		uint16_t cpkt;
 
 		/* check if packets have been transferred */
-		temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DIEPTSIZ(td->ep_no));
+		temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
 
 		/* get current packet number */
-		cpkt = DWC_OTG_MSK_DXEPTSIZ_GET_NPKT(temp);
+		cpkt = DXEPTSIZ_GET_NPKT(temp);
 
 		if (cpkt >= td->npkt) {
 			fifo_left = 0;
@@ -711,7 +712,7 @@ repeat:
 
 			/* transfer data into FIFO */
 			bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl,
-			    DWC_OTG_REG_DFIFO(td->ep_no),
+			    DOTG_DFIFO(td->ep_no),
 			    sc->sc_tx_bounce_buffer, (count + 3) / 4);
 
 			td->tx_bytes -= count;
@@ -735,14 +736,14 @@ repeat:
 		goto not_complete;
 
 	/* check if not all packets have been transferred */
-	temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DIEPTSIZ(td->ep_no));
+	temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
 
-	if (DWC_OTG_MSK_DXEPTSIZ_GET_NPKT(temp) != 0) {
+	if (DXEPTSIZ_GET_NPKT(temp) != 0) {
 
 		DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x "
 		    "DIEPCTL=0x%08x\n", td->ep_no,
-		    DWC_OTG_MSK_DXEPTSIZ_GET_NPKT(temp),
-		    temp, DWC_OTG_READ_4(sc, DWC_OTG_REG_DIEPCTL(td->ep_no)));
+		    DXEPTSIZ_GET_NPKT(temp),
+		    temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no)));
 
 		goto not_complete;
 	}
@@ -791,10 +792,10 @@ repeat:
 		}
 		td->npkt = 1;
 	}
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPTSIZ(td->ep_no),
-	    DWC_OTG_MSK_DXEPTSIZ_SET_MULTI(1) |
-	    DWC_OTG_MSK_DXEPTSIZ_SET_NPKT(td->npkt) | 
-	    DWC_OTG_MSK_DXEPTSIZ_SET_NBYTES(count));
+	DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no),
+	    DXEPTSIZ_SET_MULTI(1) |
+	    DXEPTSIZ_SET_NPKT(td->npkt) | 
+	    DXEPTSIZ_SET_NBYTES(count));
 
 	/* make room for buffering */
 	td->npkt += mpkt;
@@ -802,9 +803,9 @@ repeat:
 	temp = sc->sc_in_ctl[td->ep_no];
 
 	/* must enable before writing data to FIFO */
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPCTL(td->ep_no), temp |
-	    DWC_OTG_MSK_DIEPCTL_ENABLE |
-	    DWC_OTG_MSK_DIEPCTL_CLR_NAK);
+	DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp |
+	    DIEPCTL_EPENA |
+	    DIEPCTL_CNAK);
 
 	td->tx_bytes = count;
 
@@ -834,10 +835,10 @@ dwc_otg_data_tx_sync(struct dwc_otg_td *td)
 	/*
 	 * If all packets are transferred we are complete:
 	 */
-	temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DIEPTSIZ(td->ep_no));
+	temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
 
 	/* check that all packets have been transferred */
-	if (DWC_OTG_MSK_DXEPTSIZ_GET_NPKT(temp) != 0) {
+	if (DXEPTSIZ_GET_NPKT(temp) != 0) {
 		DPRINTFN(5, "busy ep=%d\n", td->ep_no);
 		goto not_complete;
 	}
@@ -850,10 +851,10 @@ not_complete:
 	temp = sc->sc_last_rx_status;
 
 	if ((td->ep_no == 0) && (temp != 0) &&
-	    (DWC_OTG_MSK_GRXSTS_GET_CHANNEL(temp) == 0)) {
+	    (GRXSTSRD_CHNUM_GET(temp) == 0)) {
 
-		if ((temp & DWC_OTG_MSK_GRXSTS_PACKET_STS) ==
-		    DWC_OTG_MSK_GRXSTS_DEV_STP_DATA) {
+		if ((temp & GRXSTSRD_PKTSTS_MASK) ==
+		    GRXSTSRD_STP_DATA) {
 			DPRINTFN(5, "faking complete\n");
 			/*
 			 * Race condition: We are complete!
@@ -920,36 +921,36 @@ dwc_otg_interrupt_poll(struct dwc_otg_softc *sc)
 repeat:
 	if (sc->sc_last_rx_status == 0) {
 
-		temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GINTSTS);
-		if (temp & DWC_OTG_MSK_GINT_RXFLVL) {
+		temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
+		if (temp & GINTSTS_RXFLVL) {
 			/* pop current status */
 			sc->sc_last_rx_status =
-			    DWC_OTG_READ_4(sc, DWC_OTG_REG_GRXSTSP);
+			    DWC_OTG_READ_4(sc, DOTG_GRXSTSPD);
 		}
 
 		if (sc->sc_last_rx_status != 0) {
 
 			uint8_t ep_no;
 
-			temp = DWC_OTG_MSK_GRXSTS_GET_BYTE_CNT(
+			temp = GRXSTSRD_BCNT_GET(
 			    sc->sc_last_rx_status);
-			ep_no = DWC_OTG_MSK_GRXSTS_GET_CHANNEL(
+			ep_no = GRXSTSRD_CHNUM_GET(
 			    sc->sc_last_rx_status);
 
 			/* receive data, if any */
 			if (temp != 0) {
 				DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no);
 				bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl,
-				    DWC_OTG_REG_DFIFO(ep_no),
+				    DOTG_DFIFO(ep_no),
 				    sc->sc_rx_bounce_buffer, (temp + 3) / 4);
 			}
 
 			temp = sc->sc_last_rx_status &
-			    DWC_OTG_MSK_GRXSTS_PACKET_STS;
+			    GRXSTSRD_PKTSTS_MASK;
 
 			/* non-data messages we simply skip */
-			if (temp != DWC_OTG_MSK_GRXSTS_DEV_STP_DATA &&
-			    temp != DWC_OTG_MSK_GRXSTS_DEV_OUT_DATA) {
+			if (temp != GRXSTSRD_STP_DATA &&
+			    temp != GRXSTSRD_OUT_DATA) {
 				dwc_otg_common_rx_ack(sc);
 				goto repeat;
 			}
@@ -965,7 +966,7 @@ repeat:
 			DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n",
 			    sc->sc_last_rx_status, ep_no,
 			    (sc->sc_last_rx_status >> 15) & 3,
-			    DWC_OTG_MSK_GRXSTS_GET_BYTE_CNT(sc->sc_last_rx_status),
+			    GRXSTSRD_BCNT_GET(sc->sc_last_rx_status),
 			    (sc->sc_last_rx_status >> 17) & 15);
 		} else {
 			got_rx_status = 0;
@@ -973,7 +974,7 @@ repeat:
 	} else {
 		uint8_t ep_no;
 
-		ep_no = DWC_OTG_MSK_GRXSTS_GET_CHANNEL(
+		ep_no = GRXSTSRD_CHNUM_GET(
 		    sc->sc_last_rx_status);
 
 		/* check if we should dump the data */
@@ -997,8 +998,8 @@ repeat:
 			goto repeat;
 
 		/* disable RX FIFO level interrupt */
-		sc->sc_irq_mask &= ~DWC_OTG_MSK_GINT_RXFLVL;
-		DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTMSK, sc->sc_irq_mask);
+		sc->sc_irq_mask &= ~GINTSTS_RXFLVL;
+		DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 	}
 }
 
@@ -1038,12 +1039,12 @@ dwc_otg_interrupt(struct dwc_otg_softc *sc)
 	USB_BUS_LOCK(&sc->sc_bus);
 
 	/* read and clear interrupt status */
-	status = DWC_OTG_READ_4(sc, DWC_OTG_REG_GINTSTS);
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTSTS, status);
+	status = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
+	DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status);
 
 	DPRINTFN(14, "GINTSTS=0x%08x\n", status);
 
-	if (status & DWC_OTG_MSK_GINT_USB_RESET) {
+	if (status & GINTSTS_USBRST) {
 
 		/* set correct state */
 		sc->sc_flags.status_bus_reset = 0;
@@ -1056,7 +1057,7 @@ dwc_otg_interrupt(struct dwc_otg_softc *sc)
 	}
 
 	/* check for any bus state change interrupts */
-	if (status & DWC_OTG_MSK_GINT_ENUM_DONE) {
+	if (status & GINTSTS_ENUMDONE) {
 
 		uint32_t temp;
 
@@ -1078,18 +1079,18 @@ dwc_otg_interrupt(struct dwc_otg_softc *sc)
 		sc->sc_active_out_ep = 1;
 
 		/* figure out enumeration speed */
-		temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DSTS);
-		if (DWC_OTG_MSK_DSTS_GET_ENUM_SPEED(temp) ==
-		    DWC_OTG_MSK_DSTS_ENUM_SPEED_HI)
+		temp = DWC_OTG_READ_4(sc, DOTG_DSTS);
+		if (DSTS_ENUMSPD_GET(temp) ==
+		    DSTS_ENUMSPD_HI)
 			sc->sc_flags.status_high_speed = 1;
 		else
 			sc->sc_flags.status_high_speed = 0;
 
 		/* disable resume interrupt and enable suspend interrupt */
 		
-		sc->sc_irq_mask &= ~DWC_OTG_MSK_GINT_WKUPINT;
-		sc->sc_irq_mask |= DWC_OTG_MSK_GINT_USB_SUSPEND;
-		DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTMSK, sc->sc_irq_mask);
+		sc->sc_irq_mask &= ~GINTSTS_WKUPINT;
+		sc->sc_irq_mask |= GINTSTS_USBSUSP;
+		DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 
 		/* complete root HUB interrupt endpoint */
 		dwc_otg_root_intr(sc);
@@ -1099,13 +1100,13 @@ dwc_otg_interrupt(struct dwc_otg_softc *sc)
 	 * that like RESUME. Resume is set when there is at least 3
 	 * milliseconds of inactivity on the USB BUS.
 	 */
-	if (status & DWC_OTG_MSK_GINT_WKUPINT) {
+	if (status & GINTSTS_WKUPINT) {
 
 		DPRINTFN(5, "resume interrupt\n");
 
 		dwc_otg_resume_irq(sc);
 
-	} else if (status & DWC_OTG_MSK_GINT_USB_SUSPEND) {
+	} else if (status & GINTSTS_USBSUSP) {
 
 		DPRINTFN(5, "suspend interrupt\n");
 
@@ -1118,45 +1119,45 @@ dwc_otg_interrupt(struct dwc_otg_softc *sc)
 			 * Disable suspend interrupt and enable resume
 			 * interrupt:
 			 */
-			sc->sc_irq_mask &= ~DWC_OTG_MSK_GINT_USB_SUSPEND;
-			sc->sc_irq_mask |= DWC_OTG_MSK_GINT_WKUPINT;
-			DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTMSK, sc->sc_irq_mask);
+			sc->sc_irq_mask &= ~GINTSTS_USBSUSP;
+			sc->sc_irq_mask |= GINTSTS_WKUPINT;
+			DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 
 			/* complete root HUB interrupt endpoint */
 			dwc_otg_root_intr(sc);
 		}
 	}
 	/* check VBUS */
-	if (status & (DWC_OTG_MSK_GINT_USB_SUSPEND |
-	    DWC_OTG_MSK_GINT_USB_RESET |
-	    DWC_OTG_MSK_GINT_SESSREQINT)) {
+	if (status & (GINTSTS_USBSUSP |
+	    GINTSTS_USBRST |
+	    GINTSTS_SESSREQINT)) {
 		uint32_t temp;
 
-		temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GOTGCTL);
+		temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL);
 
 		DPRINTFN(5, "GOTGCTL=0x%08x\n", temp);
 
 		dwc_otg_vbus_interrupt(sc,
-		    (temp & DWC_OTG_MSK_GOTGCTL_BSESS_VALID) ? 1 : 0);
+		    (temp & GOTGCTL_BSESVLD) ? 1 : 0);
 	}
 
 	/* clear all IN endpoint interrupts */
-	if (status & DWC_OTG_MSK_GINT_INEP) {
+	if (status & GINTSTS_IEPINT) {
 		uint32_t temp;
 		uint8_t x;
 
 		for (x = 0; x != sc->sc_dev_in_ep_max; x++) {
-			temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DIEPINT(x));
-			if (temp & DWC_OTG_MSK_DIEP_XFER_COMPLETE) {
-				DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPINT(x),
-				    DWC_OTG_MSK_DIEP_XFER_COMPLETE);
+			temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x));
+			if (temp & DIEPMSK_XFERCOMPLMSK) {
+				DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x),
+				    DIEPMSK_XFERCOMPLMSK);
 			}
 		}
 	}
 
 #if 0
 	/* check if we should poll the FIFOs */
-	if (status & (DWC_OTG_MSK_GINT_RXFLVL | DWC_OTG_MSK_GINT_INEP))
+	if (status & (GINTSTS_RXFLVL | GINTSTS_IEPINT))
 #endif
 		/* poll FIFO(s) */
 		dwc_otg_interrupt_poll(sc);
@@ -1548,16 +1549,16 @@ dwc_otg_set_stall(struct usb_device *udev,
 	DPRINTFN(5, "endpoint=0x%x\n", ep_no);
 
 	if (ep_no & UE_DIR_IN) {
-		reg = DWC_OTG_REG_DIEPCTL(ep_no & UE_ADDR);
+		reg = DOTG_DIEPCTL(ep_no & UE_ADDR);
 		temp = sc->sc_in_ctl[ep_no & UE_ADDR];
 	} else {
-		reg = DWC_OTG_REG_DOEPCTL(ep_no & UE_ADDR);
+		reg = DOTG_DOEPCTL(ep_no & UE_ADDR);
 		temp = sc->sc_out_ctl[ep_no & UE_ADDR];
 	}
 
 	/* disable and stall endpoint */
-	DWC_OTG_WRITE_4(sc, reg, temp | DWC_OTG_MSK_DOEPCTL_DISABLE);
-	DWC_OTG_WRITE_4(sc, reg, temp | DWC_OTG_MSK_DOEPCTL_STALL);
+	DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS);
+	DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL);
 
 	/* clear active OUT ep */
 	if (!(ep_no & UE_DIR_IN)) {
@@ -1565,7 +1566,7 @@ dwc_otg_set_stall(struct usb_device *udev,
 		sc->sc_active_out_ep &= ~(1U << (ep_no & UE_ADDR));
 
 		if (sc->sc_last_rx_status != 0 &&
-		    (ep_no & UE_ADDR) == DWC_OTG_MSK_GRXSTS_GET_CHANNEL(
+		    (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET(
 		    sc->sc_last_rx_status)) {
 			/* dump data */
 			dwc_otg_common_rx_ack(sc);
@@ -1588,9 +1589,9 @@ dwc_otg_clear_stall_sub(struct dwc_otg_softc *sc, uint32_t mps,
 	}
 
 	if (ep_dir) {
-		reg = DWC_OTG_REG_DIEPCTL(ep_no);
+		reg = DOTG_DIEPCTL(ep_no);
 	} else {
-		reg = DWC_OTG_REG_DOEPCTL(ep_no);
+		reg = DOTG_DOEPCTL(ep_no);
 		sc->sc_active_out_ep |= (1U << ep_no);
 	}
 
@@ -1598,39 +1599,39 @@ dwc_otg_clear_stall_sub(struct dwc_otg_softc *sc, uint32_t mps,
 	mps = (mps + 3) & 0x7FC;
 
 	if (ep_type == UE_BULK) {
-		temp = DWC_OTG_MSK_EP_SET_TYPE(
-		    DWC_OTG_MSK_EP_TYPE_BULK) |
-		    DWC_OTG_MSK_DIEPCTL_USB_AEP;
+		temp = DIEPCTL_EPTYPE_SET(
+		    DIEPCTL_EPTYPE_BULK) |
+		    DIEPCTL_USBACTEP;
 	} else if (ep_type == UE_INTERRUPT) {
-		temp = DWC_OTG_MSK_EP_SET_TYPE(
-		    DWC_OTG_MSK_EP_TYPE_INTERRUPT) |
-		    DWC_OTG_MSK_DIEPCTL_USB_AEP;
+		temp = DIEPCTL_EPTYPE_SET(
+		    DIEPCTL_EPTYPE_INTERRUPT) |
+		    DIEPCTL_USBACTEP;
 	} else {
-		temp = DWC_OTG_MSK_EP_SET_TYPE(
-		    DWC_OTG_MSK_EP_TYPE_ISOC) |
-		    DWC_OTG_MSK_DIEPCTL_USB_AEP;
+		temp = DIEPCTL_EPTYPE_SET(
+		    DIEPCTL_EPTYPE_ISOC) |
+		    DIEPCTL_USBACTEP;
 	}
 
-	temp |= DWC_OTG_MSK_DIEPCTL_MPS(mps);
-	temp |= DWC_OTG_MSK_DIEPCTL_FNUM(ep_no);
+	temp |= DIEPCTL_MPS_SET(mps);
+	temp |= DIEPCTL_TXFNUM_SET(ep_no);
 
 	if (ep_dir)
 		sc->sc_in_ctl[ep_no] = temp;
 	else
 		sc->sc_out_ctl[ep_no] = temp;
 
-	DWC_OTG_WRITE_4(sc, reg, temp | DWC_OTG_MSK_DOEPCTL_DISABLE);
-	DWC_OTG_WRITE_4(sc, reg, temp | DWC_OTG_MSK_DOEPCTL_SET_DATA0);
-	DWC_OTG_WRITE_4(sc, reg, temp | DWC_OTG_MSK_DIEPCTL_SET_NAK);
+	DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS);
+	DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID);
+	DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK);
 
 	/* we only reset the transmit FIFO */
 	if (ep_dir) {
-		DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GRSTCTL,
-		    DWC_OTG_MSK_GRSTCTL_TXFIFO(ep_no) |
-		    DWC_OTG_MSK_GRSTCTL_TXFFLUSH);
+		DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL,
+		    GRSTCTL_TXFIFO(ep_no) |
+		    GRSTCTL_TXFFLSH);
 
 		DWC_OTG_WRITE_4(sc,
-		    DWC_OTG_REG_DIEPTSIZ(ep_no), 0);
+		    DOTG_DIEPTSIZ(ep_no), 0);
 	}
 
 	/* poll interrupt */
@@ -1684,14 +1685,14 @@ dwc_otg_device_state_change(struct usb_device *udev)
 		for (x = 1; x != sc->sc_dev_ep_max; x++) {
 
 			if (x < sc->sc_dev_in_ep_max) {
-				DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPCTL(x),
-				    DWC_OTG_MSK_DIEPCTL_DISABLE);
-				DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPCTL(x), 0);
+				DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x),
+				    DIEPCTL_EPDIS);
+				DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0);
 			}
 
-			DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPCTL(x),
-			    DWC_OTG_MSK_DOEPCTL_DISABLE);
-			DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPCTL(x), 0);
+			DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x),
+			    DOEPCTL_EPDIS);
+			DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0);
 		}
 		USB_BUS_UNLOCK(&sc->sc_bus);
 	}
@@ -1716,68 +1717,68 @@ dwc_otg_init(struct dwc_otg_softc *sc)
 	/* turn on clocks */
 	dwc_otg_clocks_on(sc);
 
-	temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GSNPSID);
+	temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID);
 	DPRINTF("Version = 0x%08x\n", temp);
 
 	/* disconnect */
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCTL,
-	    DWC_OTG_MSK_DCTL_SOFT_DISC);
+	DWC_OTG_WRITE_4(sc, DOTG_DCTL,
+	    DCTL_SFTDISCON);
 
 	/* wait for host to detect disconnect */
 	usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32);
 
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GRSTCTL,
-	    DWC_OTG_MSK_GRSTCTL_CSFTRST);
+	DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL,
+	    GRSTCTL_CSFTRST);
 
 	/* wait a little bit for block to reset */
 	usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128);
 
 	/* select HSIC or non-HSIC mode */
 	if (DWC_OTG_USE_HSIC) {
-		DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GUSBCFG,
-		    DWC_OTG_MSK_GUSBCFG_PHY_INTF |
-		    DWC_OTG_MSK_GUSBCFG_TRD_TIM(5));
-		DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GOTGCTL,
+		DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
+		    GUSBCFG_PHYIF |
+		    GUSBCFG_TRD_TIM_SET(5));
+		DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL,
 		    0x000000EC);
 
-		temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GLPMCFG);
-		DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GLPMCFG,
-		    temp & ~DWC_OTG_MSK_GLPMCFG_HSIC_CONN);
-		DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GLPMCFG,
-		    temp | DWC_OTG_MSK_GLPMCFG_HSIC_CONN);
+		temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
+		DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
+		    temp & ~GLPMCFG_HSIC_CONN);
+		DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
+		    temp | GLPMCFG_HSIC_CONN);
 	} else {
-		DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GUSBCFG,
-		    DWC_OTG_MSK_GUSBCFG_ULPI_UMTI_SEL |
-		    DWC_OTG_MSK_GUSBCFG_TRD_TIM(5));
-		DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GOTGCTL, 0);
+		DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
+		    GUSBCFG_ULPI_UTMI_SEL |
+		    GUSBCFG_TRD_TIM_SET(5));
+		DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0);
 
-		temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GLPMCFG);
-		DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GLPMCFG,
-		    temp & ~DWC_OTG_MSK_GLPMCFG_HSIC_CONN);
+		temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
+		DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
+		    temp & ~GLPMCFG_HSIC_CONN);
 	}
 
 	/* clear global nak */
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCTL,
-	    DWC_OTG_MSK_DCTL_CGOUT_NAK |
-	    DWC_OTG_MSK_DCTL_CGNPIN_NAK);
+	DWC_OTG_WRITE_4(sc, DOTG_DCTL,
+	    DCTL_CGOUTNAK |
+	    DCTL_CGNPINNAK);
 
 	/* enable USB port */
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_PCGCCTL, 0);
+	DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0);
 
 	/* pull up D+ */
 	dwc_otg_pull_up(sc);
 
-	temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GHWCFG3);
+	temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3);
 
-	sc->sc_fifo_size = 4 * DWC_OTG_MSK_GHWCFG3_GET_DFIFO(temp);
+	sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp);
 
-	temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GHWCFG2);
+	temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2);
 
-	sc->sc_dev_ep_max = DWC_OTG_MSK_GHWCFG2_NUM_DEV_EP(temp);
+	sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp);
 
-	temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GHWCFG4);
+	temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4);
 
-	sc->sc_dev_in_ep_max = DWC_OTG_MSK_GHWCFG4_NUM_IN_EPS(temp);
+	sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp);
 
 	DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d\n",
 	    sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max);
@@ -1788,43 +1789,43 @@ dwc_otg_init(struct dwc_otg_softc *sc)
 
 	/* enable interrupts */
 	sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED;
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTMSK, sc->sc_irq_mask);
+	DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 
 	/* enable all endpoint interrupts */
-	temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GHWCFG2);
-	if (temp & DWC_OTG_MSK_GHWCFG2_MPI) {
+	temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2);
+	if (temp & GHWCFG2_MPI) {
 		uint8_t x;
 
 		DPRINTF("Multi Process Interrupts\n");
 
 		for (x = 0; x != sc->sc_dev_in_ep_max; x++) {
-			DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPEACHMSK(x),
-			    DWC_OTG_MSK_DIEP_XFER_COMPLETE);
-			DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPEACHMSK(x), 0);
+			DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x),
+			    DIEPMSK_XFERCOMPLMSK);
+			DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0);
 		}
-		DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DEACHINTMSK, 0xFFFF);
+		DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0xFFFF);
 	} else {
-		DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPMSK,
-		    DWC_OTG_MSK_DIEP_XFER_COMPLETE);
-		DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPMSK, 0);
-		DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DAINTMSK, 0xFFFF);
+		DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK,
+		    DIEPMSK_XFERCOMPLMSK);
+		DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0);
+		DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF);
 	}
 
 	/* enable global IRQ */
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GAHBCFG,
-	    DWC_OTG_MSK_GAHBCFG_GLOBAL_IRQ);
+	DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG,
+	    GAHBCFG_GLBLINTRMSK);
 
 	/* turn off clocks */
 	dwc_otg_clocks_off(sc);
 
 	/* read initial VBUS state */
 
-	temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GOTGCTL);
+	temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL);
 
 	DPRINTFN(5, "GOTCTL=0x%08x\n", temp);
 
 	dwc_otg_vbus_interrupt(sc,
-	    (temp & DWC_OTG_MSK_GOTGCTL_BSESS_VALID) ? 1 : 0);
+	    (temp & GOTGCTL_BSESVLD) ? 1 : 0);
 
 	USB_BUS_UNLOCK(&sc->sc_bus);
 
@@ -1841,11 +1842,11 @@ dwc_otg_uninit(struct dwc_otg_softc *sc)
 	USB_BUS_LOCK(&sc->sc_bus);
 
 	/* set disconnect */
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCTL,
-	    DWC_OTG_MSK_DCTL_SOFT_DISC);
+	DWC_OTG_WRITE_4(sc, DOTG_DCTL,
+	    DCTL_SFTDISCON);
 
 	/* turn off global IRQ */
-	DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GAHBCFG, 0);
+	DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0);
 
 	sc->sc_flags.port_powered = 0;
 	sc->sc_flags.status_vbus = 0;
@@ -1946,11 +1947,11 @@ dwc_otg_device_isoc_fs_enter(struct usb_xfer *xfer)
 	DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
 	    xfer, xfer->endpoint->isoc_next, xfer->nframes);
 
-	temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DSTS);
+	temp = DWC_OTG_READ_4(sc, DOTG_DSTS);
 
 	/* get the current frame index */
 
-	nframes = DWC_OTG_MSK_DSTS_GET_FNUM(temp);
+	nframes = DSTS_SOFFN_GET(temp);
 
 	if (sc->sc_flags.status_high_speed)
 		nframes /= 8;
diff --git a/sys/dev/usb/controller/dwc_otg.h b/sys/dev/usb/controller/dwc_otg.h
index 15bbd18..8d8b3e4 100644
--- a/sys/dev/usb/controller/dwc_otg.h
+++ b/sys/dev/usb/controller/dwc_otg.h
@@ -32,290 +32,6 @@
 #define	DWC_OTG_MAX_TXP 4
 #define	DWC_OTG_MAX_TXN (0x200 * DWC_OTG_MAX_TXP)
 
-/* Global CSR registers */
-
-#define	DWC_OTG_REG_GOTGCTL		0x0000
-#define	DWC_OTG_MSK_GOTGCTL_CHIRP_ON		(1U << 27)
-#define	DWC_OTG_MSK_GOTGCTL_BSESS_VALID		(1U << 19)
-#define	DWC_OTG_MSK_GOTGCTL_ASESS_VALID		(1U << 18)
-#define	DWC_OTG_MSK_GOTGCTL_CONN_ID_STATUS	(1U << 16)
-#define	DWC_OTG_MSK_GOTGCTL_SESS_REQ		(1U << 1)
-#define	DWC_OTG_MSK_GOTGCTL_SESS_VALID		(1U << 0)
-
-#define	DWC_OTG_REG_GOTGINT		0x0004
-#define	DWC_OTG_REG_GAHBCFG		0x0008
-#define	DWC_OTG_MSK_GAHBCFG_GLOBAL_IRQ		(1U << 0)
-
-#define	DWC_OTG_REG_GUSBCFG		0x000C
-#define	DWC_OTG_MSK_GUSBCFG_FORCE_DEVICE	(1U << 30)
-#define	DWC_OTG_MSK_GUSBCFG_FORCE_HOST		(1U << 29)
-#define	DWC_OTG_MSK_GUSBCFG_NO_PULLUP		(1U << 27)
-#define	DWC_OTG_MSK_GUSBCFG_NO_PULLUP		(1U << 27)
-#define	DWC_OTG_MSK_GUSBCFG_IC_USB_CAP		(1U << 26)
-#define	DWC_OTG_MSK_GUSBCFG_ULPI_FS_LS		(1U << 17)
-#define	DWC_OTG_MSK_GUSBCFG_TRD_TIM(x)		(((x) & 15U) << 10)
-#define	DWC_OTG_MSK_GUSBCFG_HRP			(1U << 9)
-#define	DWC_OTG_MSK_GUSBCFG_SRP			(1U << 8)
-#define	DWC_OTG_MSK_GUSBCFG_HS_PHY		(1U << 6)
-#define	DWC_OTG_MSK_GUSBCFG_FS_INTF		(1U << 5)
-#define	DWC_OTG_MSK_GUSBCFG_ULPI_UMTI_SEL	(1U << 4)
-#define	DWC_OTG_MSK_GUSBCFG_PHY_INTF		(1U << 3)
-
-#define	DWC_OTG_REG_GRSTCTL		0x0010
-#define	DWC_OTG_MSK_GRSTCTL_TXFIFO(n)		(((n) & 31U) << 6)
-#define	DWC_OTG_MSK_GRSTCTL_TXFFLUSH		(1U << 5)
-#define	DWC_OTG_MSK_GRSTCTL_RXFFLUSH		(1U << 4)
-#define	DWC_OTG_MSK_GRSTCTL_FRMCNTRRST		(1U << 2)
-#define	DWC_OTG_MSK_GRSTCTL_CSFTRST		(1U << 0)
-
-#define	DWC_OTG_REG_GINTSTS		0x0014
-#define	DWC_OTG_REG_GINTMSK		0x0018
-#define	DWC_OTG_MSK_GINT_WKUPINT		(1U << 31)
-#define	DWC_OTG_MSK_GINT_SESSREQINT		(1U << 30)
-#define	DWC_OTG_MSK_GINT_DISCONNINT		(1U << 29)
-#define	DWC_OTG_MSK_GINT_CONNIDSTSCHNG		(1U << 28)
-#define	DWC_OTG_MSK_GINT_LPM			(1U << 27)
-#define	DWC_OTG_MSK_GINT_PTXFEMP		(1U << 26)
-#define	DWC_OTG_MSK_GINT_HCHINT			(1U << 25)
-#define	DWC_OTG_MSK_GINT_PRTINT			(1U << 24)
-#define	DWC_OTG_MSK_GINT_RESETDET		(1U << 23)
-#define	DWC_OTG_MSK_GINT_FETSUSP		(1U << 22)
-#define	DWC_OTG_MSK_GINT_INCOMPL_P		(1U << 21)
-#define	DWC_OTG_MSK_GINT_INCOMPL_ISO_IN		(1U << 20)
-#define	DWC_OTG_MSK_GINT_OUTEP			(1U << 19)
-#define	DWC_OTG_MSK_GINT_INEP			(1U << 18)
-#define	DWC_OTG_MSK_GINT_EP_MISMATCH		(1U << 17)
-#define	DWC_OTG_MSK_GINT_RESTORE_DONE		(1U << 16)
-#define	DWC_OTG_MSK_GINT_EOP_FRAME		(1U << 15)
-#define	DWC_OTG_MSK_GINT_ISO_OUT_DROP		(1U << 14)
-#define	DWC_OTG_MSK_GINT_ENUM_DONE		(1U << 13)
-#define	DWC_OTG_MSK_GINT_USB_RESET		(1U << 12)
-#define	DWC_OTG_MSK_GINT_USB_SUSPEND		(1U << 11)
-#define	DWC_OTG_MSK_GINT_EARLY_SUSPEND		(1U << 10)
-#define	DWC_OTG_MSK_GINT_I2C_INT		(1U << 9)
-#define	DWC_OTG_MSK_GINT_ULPI_CARKIT		(1U << 8)
-#define	DWC_OTG_MSK_GINT_GLOBAL_OUT_NAK		(1U << 7)
-#define	DWC_OTG_MSK_GINT_GLOBAL_IN_NAK		(1U << 6)
-#define	DWC_OTG_MSK_GINT_NPTXFEMP		(1U << 5)
-#define	DWC_OTG_MSK_GINT_RXFLVL			(1U << 4)
-#define	DWC_OTG_MSK_GINT_SOF			(1U << 3)
-#define	DWC_OTG_MSK_GINT_OTG			(1U << 2)
-#define	DWC_OTG_MSK_GINT_MODE_MISMATCH		(1U << 1)
-#define	DWC_OTG_MSK_GINT_CUR_MODE		(1U << 0)
-
-#define	DWC_OTG_REG_GRXSTSR		0x001C
-#define	DWC_OTG_REG_GRXSTSP		0x0020
-#define	DWC_OTG_MSK_GRXSTS_PACKET_STS		(15U << 17)
-#define	DWC_OTG_MSK_GRXSTS_HST_IN_DATA		(2U << 17)
-#define	DWC_OTG_MSK_GRXSTS_HST_IN_COMPLETE	(3U << 17)
-#define	DWC_OTG_MSK_GRXSTS_HST_DT_ERROR		(5U << 17)
-#define	DWC_OTG_MSK_GRXSTS_HST_HALTED		(7U << 17)
-#define	DWC_OTG_MSK_GRXSTS_DEV_GLOB_OUT_NAK	(1U << 17)
-#define	DWC_OTG_MSK_GRXSTS_DEV_OUT_DATA		(2U << 17)
-#define	DWC_OTG_MSK_GRXSTS_DEV_OUT_COMPLETE	(3U << 17)
-#define	DWC_OTG_MSK_GRXSTS_DEV_STP_COMPLETE	(4U << 17)
-#define	DWC_OTG_MSK_GRXSTS_DEV_STP_DATA		(6U << 17)
-#define	DWC_OTG_MSK_GRXSTS_PID			(3U << 15)
-#define	DWC_OTG_MSK_GRXSTS_PID_DATA0		(0U << 15)
-#define	DWC_OTG_MSK_GRXSTS_PID_DATA1		(2U << 15)
-#define	DWC_OTG_MSK_GRXSTS_PID_DATA2		(1U << 15)
-#define	DWC_OTG_MSK_GRXSTS_PID_MDATA		(3U << 15)
-#define	DWC_OTG_MSK_GRXSTS_GET_BYTE_CNT(x)	(((x) >> 4) & 0x7FFU)
-#define	DWC_OTG_MSK_GRXSTS_GET_CHANNEL(x)	((x) & 15U)
-#define	DWC_OTG_MSK_GRXSTS_GET_FRNUM	(x)	(((x) >> 21) & 15U)
-
-#define	DWC_OTG_REG_GRXFSIZ		0x0024
-#define	DWC_OTG_REG_GNPTXFSIZ		0x0028
-#define	DWC_OTG_REG_GNPTXSTS		0x002C
-#define	DWC_OTG_REG_GI2CCTL		0x0030
-#define	DWC_OTG_REG_GPVNDCTL		0x0034
-#define	DWC_OTG_REG_GGPIO		0x0038
-#define	DWC_OTG_REG_GUID		0x003C
-#define	DWC_OTG_REG_GSNPSID		0x0040
-#define	DWC_OTG_REG_GHWCFG1		0x0044
-#define	DWC_OTG_MSK_GHWCFG1_GET_DIR(x, n)	(((x) >> (2 * (n))) & 3U)
-#define	DWC_OTG_MSK_GHWCFG1_BIDIR		(0U)
-#define	DWC_OTG_MSK_GHWCFG1_IN			(1U)
-#define	DWC_OTG_MSK_GHWCFG1_OUT			(2U)
-#define	DWC_OTG_REG_GHWCFG2		0x0048
-#define	DWC_OTG_MSK_GHWCFG2_NUM_DEV_EP(x)	((((x) >> 10) & 15) + 1)
-#define	DWC_OTG_MSK_GHWCFG2_NUM_HOST_EP(x)	((((x) >> 14) & 15) + 1)
-#define	DWC_OTG_MSK_GHWCFG2_DYN_FIFO		(1U << 19)
-#define	DWC_OTG_MSK_GHWCFG2_MPI			(1U << 20)
-#define	DWC_OTG_REG_GHWCFG3		0x004C
-#define	DWC_OTG_MSK_GHWCFG3_GET_DFIFO(x)	((x) >> 16)
-#define	DWC_OTG_MSK_GHWCFG3_PKT_SIZE		(0x10U << (((x) >> 4) & 7))
-#define	DWC_OTG_MSK_GHWCFG3_XFR_SIZE		(0x400U << (((x) >> 0) & 15))
-
-#define	DWC_OTG_REG_GHWCFG4		0x0050
-#define	DWC_OTG_MSK_GHWCFG4_NUM_IN_EPS(x)	((((x) >> 26) & 15U) + 1U)
-#define	DWC_OTG_MSK_GHWCFG4_NUM_CTRL_EPS(x)	(((x) >> 16) & 15U)
-#define	DWC_OTG_MSK_GHWCFG4_NUM_IN_PERIODIC_EPS(x)	(((x) >> 0) & 15U)
-
-#define	DWC_OTG_REG_GLPMCFG		0x0054
-#define	DWC_OTG_MSK_GLPMCFG_HSIC_CONN		(1U << 30)
-#define	DWC_OTG_REG_GPWRDN		0x0058
-#define	DWC_OTG_MSK_GPWRDN_BVALID		(1U << 22)
-#define	DWC_OTG_MSK_GPWRDN_IDDIG		(1U << 21)
-#define	DWC_OTG_MSK_GPWRDN_CONNDET_INT		(1U << 14)
-#define	DWC_OTG_MSK_GPWRDN_CONNDET		(1U << 13)
-#define	DWC_OTG_MSK_GPWRDN_DISCONN_INT		(1U << 12)
-#define	DWC_OTG_MSK_GPWRDN_DISCONN		(1U << 11)
-#define	DWC_OTG_MSK_GPWRDN_RESETDET_INT		(1U << 10)
-#define	DWC_OTG_MSK_GPWRDN_RESETDET		(1U << 9)
-#define	DWC_OTG_MSK_GPWRDN_LINESTATE_INT	(1U << 8)
-#define	DWC_OTG_MSK_GPWRDN_LINESTATE		(1U << 7)
-#define	DWC_OTG_MSK_GPWRDN_DISABLE_VBUS		(1U << 6)
-#define	DWC_OTG_MSK_GPWRDN_POWER_DOWN		(1U << 5)
-#define	DWC_OTG_MSK_GPWRDN_POWER_DOWN_RST	(1U << 4)
-#define	DWC_OTG_MSK_GPWRDN_POWER_DOWN_CLAMP	(1U << 3)
-#define	DWC_OTG_MSK_GPWRDN_RESTORE		(1U << 2)
-#define	DWC_OTG_MSK_GPWRDN_PMU_ACTIVE		(1U << 1)
-#define	DWC_OTG_MSK_GPWRDN_PMU_IRQ_SEL		(1U << 0)
-
-#define	DWC_OTG_REG_GDFIFOCFG		0x005C
-#define	DWC_OTG_REG_GADPCTL		0x0060
-#define	DWC_OTG_REG_HPTXFSIZ		0x0100
-#define	DWC_OTG_REG_DPTXFSIZ(n)			(0x0100 + (4*(n)))
-#define	DWC_OTG_REG_DIEPTXF(n)			(0x0100 + (4*(n)))
-
-/* Host Mode CSR registers */
-
-#define	DWC_OTG_REG_HCFG		0x0400
-#define	DWC_OTG_REG_HFIR		0x0404
-#define	DWC_OTG_REG_HFNUM		0x0408
-#define	DWC_OTG_REG_HPTXSTS		0x0410
-#define	DWC_OTG_REG_HAINT		0x0414
-#define	DWC_OTG_REG_HAINTMSK		0x0418
-#define	DWC_OTG_REG_HPRT		0x0440
-#define	DWC_OTG_REG_HCCHAR(n)	(0x0500 + (32*(n)))
-#define	DWC_OTG_REG_HCSPLT(n)	(0x0504 + (32*(n)))
-#define	DWC_OTG_REG_HCINT(n)	(0x0508 + (32*(n)))
-#define	DWC_OTG_REG_HCINTMSK(n)	(0x050C + (32*(n)))
-#define	DWC_OTG_REG_HCTSIZ(n)	(0x0510 + (32*(n)))
-#define	DWC_OTG_REG_HCDMA(n)	(0x0514 + (32*(n)))
-#define	DWC_OTG_REG_HCDMAB(n)	(0x051C + (32*(n)))
-
-/* Device Mode CSR registers */
-
-#define	DWC_OTG_REG_DCFG		0x0800
-#define	DWC_OTG_MSK_DCFG_SET_DEV_ADDR(x) (((x) & 0x7FU) << 4)
-#define	DWC_OTG_MSK_DCFG_SET_DEV_SPEED(x) ((x) & 0x3U)
-#define	DWC_OTG_MSK_DCFG_DEV_SPEED_HI		(0U)
-#define	DWC_OTG_MSK_DCFG_DEV_SPEED_FULL20	(1U)
-#define	DWC_OTG_MSK_DCFG_DEV_SPEED_FULL10	(3U)
-
-#define	DWC_OTG_REG_DCTL		0x0804
-#define	DWC_OTG_MSK_DCTL_PWRON_PROG_DONE	(1U << 11)
-#define	DWC_OTG_MSK_DCTL_CGOUT_NAK		(1U << 10)
-#define	DWC_OTG_MSK_DCTL_CGNPIN_NAK		(1U << 8)
-#define	DWC_OTG_MSK_DCTL_SOFT_DISC		(1U << 1)
-#define	DWC_OTG_MSK_DCTL_REMOTE_WAKEUP		(1U << 0)
-
-#define	DWC_OTG_REG_DSTS		0x0808
-#define	DWC_OTG_MSK_DSTS_GET_FNUM(x)		(((x) >> 8) & 0x3FFF)
-#define	DWC_OTG_MSK_DSTS_GET_ENUM_SPEED(x)	(((x) >> 1) & 3U)
-#define	DWC_OTG_MSK_DSTS_ENUM_SPEED_HI		(0U)
-#define	DWC_OTG_MSK_DSTS_ENUM_SPEED_FULL20	(1U)
-#define	DWC_OTG_MSK_DSTS_ENUM_SPEED_LOW10	(2U)
-#define	DWC_OTG_MSK_DSTS_ENUM_SPEED_FULL10	(3U)
-#define	DWC_OTG_MSK_DSTS_SUSPEND		(1U << 0)
-
-#define	DWC_OTG_REG_DIEPMSK		0x0810
-#define	DWC_OTG_MSK_DIEP_FIFO_EMPTY		(1U << 4)
-#define	DWC_OTG_MSK_DIEP_XFER_COMPLETE		(1U << 0)
-
-#define	DWC_OTG_REG_DOEPMSK		0x0814
-#define	DWC_OTG_MSK_DOEP_FIFO_EMPTY		(1U << 4)
-#define	DWC_OTG_MSK_DOEP_XFER_COMPLETE		(1U << 0)
-
-#define	DWC_OTG_REG_DAINT		0x0818
-#define	DWC_OTG_REG_DAINTMSK		0x081C
-
-#define	DWC_OTG_MSK_ENDPOINT(x,in) \
-	((in) ? (1U << ((x) & 15U)) : \
-	 (0x10000U << ((x) & 15U)))
-
-#define	DWC_OTG_REG_DTKNQR1		0x0820
-#define	DWC_OTG_REG_DTKNQR2		0x0824
-#define	DWC_OTG_REG_DTKNQR3		0x0830
-#define	DWC_OTG_REG_DTKNQR4		0x0834
-#define	DWC_OTG_REG_DVBUSDIS		0x0828
-#define	DWC_OTG_REG_DVBUSPULSE		0x082C
-#define	DWC_OTG_REG_DTHRCTL		0x0830
-#define	DWC_OTG_REG_DIEPEMPMSK		0x0834
-#define	DWC_OTG_REG_DEACHINT		0x0838
-#define	DWC_OTG_REG_DEACHINTMSK		0x083C
-#define	DWC_OTG_REG_DIEPEACHMSK(n)	(0x0840 + (4*(n)))
-#define	DWC_OTG_REG_DOEPEACHMSK(n)	(0x0880 + (4*(n)))
-
-#define	DWC_OTG_REG_DIEPCTL(n)		(0x0900 + (32*(n)))
-#define	DWC_OTG_MSK_DIEPCTL_ENABLE		(1U << 31)
-#define	DWC_OTG_MSK_DIEPCTL_DISABLE		(1U << 30)
-#define	DWC_OTG_MSK_DIEPCTL_SET_DATA1		(1U << 29)	/* non-control */
-#define	DWC_OTG_MSK_DIEPCTL_SET_DATA0		(1U << 28)	/* non-control */
-#define	DWC_OTG_MSK_DIEPCTL_SET_NAK		(1U << 27)
-#define	DWC_OTG_MSK_DIEPCTL_CLR_NAK		(1U << 26)
-#define	DWC_OTG_MSK_DIEPCTL_FNUM(n)		(((n) & 15U) << 22)
-#define	DWC_OTG_MSK_DIEPCTL_STALL		(1U << 21)
-#define	DWC_OTG_MSK_EP_SET_TYPE(n)	(((n) & 3) << 18)
-#define	DWC_OTG_MSK_EP_TYPE_CONTROL		(0U)
-#define	DWC_OTG_MSK_EP_TYPE_ISOC		(1U)
-#define	DWC_OTG_MSK_EP_TYPE_BULK		(2U)
-#define	DWC_OTG_MSK_EP_TYPE_INTERRUPT		(3U)
-#define	DWC_OTG_MSK_DIEPCTL_USB_AEP		(1U << 15)
-#define	DWC_OTG_MSK_DIEPCTL_MPS_64		(0U << 0)	/* control-only */
-#define	DWC_OTG_MSK_DIEPCTL_MPS_32		(1U << 0)	/* control-only */
-#define	DWC_OTG_MSK_DIEPCTL_MPS_16		(2U << 0)	/* control-only */
-#define	DWC_OTG_MSK_DIEPCTL_MPS_8		(3U << 0)	/* control-only */
-#define	DWC_OTG_MSK_DIEPCTL_MPS(n)		((n) & 0x7FF)	/* non-control */
-
-#define	DWC_OTG_REG_DIEPINT(n)		(0x0908 + (32*(n)))
-#define	DWC_OTG_MSK_DXEPINT_TXFEMP		(1U << 7)
-#define	DWC_OTG_MSK_DXEPINT_SETUP		(1U << 3)
-#define	DWC_OTG_MSK_DXEPINT_XFER_COMPL		(1U << 0)
-
-#define	DWC_OTG_REG_DIEPTSIZ(n)		(0x0910 + (32*(n)))
-#define	DWC_OTG_MSK_DXEPTSIZ_SET_MULTI(n)	(((n) & 3) << 29)
-#define	DWC_OTG_MSK_DXEPTSIZ_SET_NPKT(n)	(((n) & 0x3FF) << 19)
-#define	DWC_OTG_MSK_DXEPTSIZ_GET_NPKT(n)	(((n) >> 19) & 0x3FF)
-#define	DWC_OTG_MSK_DXEPTSIZ_SET_NBYTES(n)	(((n) & 0x7FFFFF) << 0)
-#define	DWC_OTG_MSK_DXEPTSIZ_GET_NBYTES(n)	(((n) >> 0) & 0x7FFFFF)
-
-#define	DWC_OTG_REG_DIEPDMA(n)		(0x0914 + (32*(n)))
-#define	DWC_OTG_REG_DTXFSTS(n)		(0x0918 + (32*(n)))
-#define	DWC_OTG_REG_DIEPDMAB0		(0x091C + (32*(n)))
-
-#define	DWC_OTG_REG_DOEPCTL(n)		(0x0B00 + (32*(n)))
-#define	DWC_OTG_MSK_DOEPCTL_ENABLE		(1U << 31)
-#define	DWC_OTG_MSK_DOEPCTL_DISABLE		(1U << 30)
-#define	DWC_OTG_MSK_DOEPCTL_SET_DATA1		(1U << 29)	/* non-control */
-#define	DWC_OTG_MSK_DOEPCTL_SET_DATA0		(1U << 28)	/* non-control */
-#define	DWC_OTG_MSK_DOEPCTL_SET_NAK		(1U << 27)
-#define	DWC_OTG_MSK_DOEPCTL_CLR_NAK		(1U << 26)
-#define	DWC_OTG_MSK_DOEPCTL_FNUM(n)		(((n) & 15U) << 22)
-#define	DWC_OTG_MSK_DOEPCTL_STALL		(1U << 21)
-#define	DWC_OTG_MSK_DOEPCTL_EP_TYPE(n)	(((n) & 3) << 18)
-#define	DWC_OTG_MSK_DOEPCTL_USB_AEP		(1U << 15)
-#define	DWC_OTG_MSK_DOEPCTL_MPS_64		(0U << 0)	/* control-only */
-#define	DWC_OTG_MSK_DOEPCTL_MPS_32		(1U << 0)	/* control-only */
-#define	DWC_OTG_MSK_DOEPCTL_MPS_16		(2U << 0)	/* control-only */
-#define	DWC_OTG_MSK_DOEPCTL_MPS_8		(3U << 0)	/* control-only */
-#define	DWC_OTG_MSK_DOEPCTL_MPS(n)	((n) & 0x7FF)	/* non-control */
-
-#define	DWC_OTG_REG_DOEPINT(n)		(0x0B08 + (32*(n)))
-#define	DWC_OTG_REG_DOEPTSIZ(n)		(0x0B10 + (32*(n)))
-#define	DWC_OTG_REG_DOEPDMA(n)		(0x0B14 + (32*(n)))
-#define	DWC_OTG_REG_DOEPDMAB(n)		(0x0B1C + (32*(n)))
-
-/* FIFO access registers */
-
-#define	DWC_OTG_REG_DFIFO(n)		(0x1000 + (0x1000 * (n)))
-
-/* Power and clock gating CSR */
-
-#define	DWC_OTG_REG_PCGCCTL		0x0E00
-
 #define	DWC_OTG_READ_4(sc, reg) \
   bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
 
diff --git a/sys/dev/usb/controller/dwc_otgreg.h b/sys/dev/usb/controller/dwc_otgreg.h
new file mode 100644
index 0000000..2c991ac
--- /dev/null
+++ b/sys/dev/usb/controller/dwc_otgreg.h
@@ -0,0 +1,757 @@
+/* $FreeBSD$ */
+
+/*-
+ * Copyright (c) 2010,2011 Aleksandr Rybalko. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _DWC_OTGREG_H_
+#define	_DWC_OTGREG_H_
+
+#define	DOTG_GOTGCTL		0x0000
+#define	DOTG_GOTGINT		0x0004
+#define	DOTG_GAHBCFG		0x0008
+#define	DOTG_GUSBCFG		0x000C
+#define	DOTG_GRSTCTL		0x0010
+#define	DOTG_GINTSTS		0x0014
+#define	DOTG_GINTMSK		0x0018
+#define	DOTG_GRXSTSRD		0x001C
+#define	DOTG_GRXSTSRH		0x001C
+#define	DOTG_GRXSTSPD		0x0020
+#define	DOTG_GRXSTSPH		0x0020
+#define	DOTG_GRXFSIZ		0x0024
+#define	DOTG_GNPTXFSIZ		0x0028
+#define	DOTG_GNPTXSTS		0x002C
+#define	DOTG_GI2CCTL		0x0030
+#define	DOTG_GPVNDCTL		0x0034
+#define	DOTG_GGPIO		0x0038
+#define	DOTG_GUID		0x003C
+#define	DOTG_GSNPSID		0x0040
+#define	DOTG_GHWCFG1		0x0044
+#define	DOTG_GHWCFG2		0x0048
+#define	DOTG_GHWCFG3		0x004C
+#define	DOTG_GHWCFG4		0x0050
+#define	DOTG_GLPMCFG		0x0054
+#define	DOTG_GPWRDN		0x0058
+#define	DOTG_GDFIFOCFG		0x005C
+#define	DOTG_GADPCTL		0x0060
+
+#define	DOTG_HPTXFSIZ		0x0100
+/* start from 0x104, but fifo0 not exists */
+#define	DOTG_DPTXFSIZ(fifo)	(0x0100 + (4*(fifo)))
+#define	DOTG_DIEPTXF(fifo)	(0x0100 + (4*(fifo)))
+
+#define	DOTG_HCFG		0x0400
+#define	DOTG_HFIR		0x0404
+#define	DOTG_HFNUM		0x0408
+#define	DOTG_HPTXSTS		0x0410
+#define	DOTG_HAINT		0x0414
+#define	DOTG_HAINTMSK		0x0418
+#define	DOTG_HPRT		0x0440
+
+#define	DOTG_HCCHAR(ch)		(0x0500 + (32*(ch)))
+#define	DOTG_HCSPLT(ch)		(0x0504 + (32*(ch)))
+#define	DOTG_HCINT(ch)		(0x0508 + (32*(ch)))
+#define	DOTG_HCINTMSK(ch)	(0x050C + (32*(ch)))
+#define	DOTG_HCTSIZ(ch)		(0x0510 + (32*(ch)))
+#define	DOTG_HCDMA(ch)		(0x0514 + (32*(ch)))
+#define	DOTG_HCDMAI(ch)		(0x0514 + (32*(ch)))
+#define	DOTG_HCDMAO(ch)		(0x0514 + (32*(ch)))
+#define	DOTG_HCDMAB(ch)		(0x051C + (32*(ch)))
+
+/* Device Mode */
+#define	DOTG_DCFG		0x0800
+#define	DOTG_DCTL		0x0804
+#define	DOTG_DSTS		0x0808
+#define	DOTG_DIEPMSK		0x0810
+#define	DOTG_DOEPMSK		0x0814
+#define	DOTG_DAINT		0x0818
+#define	DOTG_DAINTMSK		0x081C
+#define	DOTG_DTKNQR1		0x0820
+#define	DOTG_DTKNQR2		0x0824
+#define	DOTG_DVBUSDIS		0x0828
+#define	DOTG_DVBUSPULSE		0x082C
+#define	DOTG_DTHRCTL		0x0830
+#define	DOTG_DTKNQR4		0x0834
+#define	DOTG_DIEPEMPMSK		0x0834
+#define	DOTG_DEACHINT		0x0838
+#define	DOTG_DEACHINTMSK	0x083C
+#define	DOTG_DIEPEACHINTMSK(ch)	(0x0840 + (4*(ch)))
+#define	DOTG_DOEPEACHINTMSK(ch)	(0x0880 + (4*(ch)))
+
+#define	DOTG_DIEPCTL(ep)	(0x0900 + (32*(ep)))
+#define	DOTG_DIEPINT(ep)	(0x0908 + (32*(ep)))
+#define	DOTG_DIEPTSIZ(ep)	(0x0910 + (32*(ep)))
+#define	DOTG_DIEPDMA(ep)	(0x0914 + (32*(ep)))
+#define	DOTG_DTXFSTS(ep)	(0x0918 + (32*(ep)))
+#define	DOTG_DIEPDMAB(ep)	(0x091c + (32*(ep)))
+
+#define	DOTG_DOEPCTL(ep)	(0x0B00 + (32*(ep)))
+#define	DOTG_DOEPFN(ep)		(0x0B04 + (32*(ep)))
+#define	DOTG_DOEPINT(ep)	(0x0B08 + (32*(ep)))
+#define	DOTG_DOEPTSIZ(ep)	(0x0B10 + (32*(ep)))
+#define	DOTG_DOEPDMA(ep)	(0x0B14 + (32*(ep)))
+#define	DOTG_DOEPDMAB(ep)	(0x0B1c + (32*(ep)))
+/* End Device Mode */
+
+/* Host Mode
+#define	DOTG_CTL_STATUS		0x0800
+#define	DOTG_DMA0_INB_CHN0	0x0818
+#define	DOTG_DMA0_INB_CHN1	0x0820
+#define	DOTG_DMA0_INB_CHN2	0x0828
+#define	DOTG_DVBUSDIS		0x0828
+#define	DOTG_DVBUSPULSE		0x082c
+#define	DOTG_DMA0_INB_CHN3	0x0830
+#define	DOTG_DMA0_INB_CHN4	0x0838
+#define	DOTG_DMA0_INB_CHN5	0x0840
+#define	DOTG_DMA0_INB_CHN6	0x0848
+#define	DOTG_DMA0_INB_CHN7	0x0850
+#define	DOTG_DMA0_OUTB_CHN0	0x0858
+#define	DOTG_DMA0_OUTB_CHN1	0x0860
+#define	DOTG_DMA0_OUTB_CHN2	0x0868
+#define	DOTG_DMA0_OUTB_CHN3	0x0870
+#define	DOTG_DMA0_OUTB_CHN4	0x0878
+#define	DOTG_DMA0_OUTB_CHN5	0x0880
+#define	DOTG_DMA0_OUTB_CHN6	0x0888
+#define	DOTG_DMA0_OUTB_CHN7	0x0890
+ End Host Mode */
+
+/* Power and clock gating CSR */
+
+#define	DOTG_PCGCCTL		0x0E00
+
+/* FIFO access registers (PIO-mode) */
+
+#define	DOTG_DFIFO(n)		(0x1000 + (0x1000 * (n)))
+
+#define	GOTGCTL_CHIRP_ON		(1<<27)
+#define	GOTGCTL_BSESVLD			(1<<19)
+#define	GOTGCTL_ASESVLD			(1<<18)
+#define	GOTGCTL_DBNCTIME		(1<<17)
+#define	GOTGCTL_CONIDSTS		(1<<16)
+#define	GOTGCTL_DEVHNPEN		(1<<11)
+#define	GOTGCTL_HSTSETHNPEN		(1<<10)
+#define	GOTGCTL_HNPREQ			(1<<9)
+#define	GOTGCTL_HSTNEGSCS		(1<<8)
+#define	GOTGCTL_SESREQ			(1<<1)
+#define	GOTGCTL_SESREQSCS		(1<<0)
+
+#define	GOTGCTL_DBNCEDONE		(1<<19)
+#define	GOTGCTL_ADEVTOUTCHG		(1<<18)
+#define	GOTGCTL_HSTNEGDET		(1<<17)
+#define	GOTGCTL_HSTNEGSUCSTSCHG		(1<<9)
+#define	GOTGCTL_SESREQSUCSTSCHG		(1<<8)
+#define	GOTGCTL_SESENDDET		(1<<2)
+
+#define	GAHBCFG_PTXFEMPLVL		(1<<8)
+#define	GAHBCFG_NPTXFEMPLVL		(1<<7)
+#define	GAHBCFG_DMAEN			(1<<5)
+#define	GAHBCFG_HBSTLEN_MASK		0x0000001e
+#define	GAHBCFG_HBSTLEN_SHIFT		1
+#define	GAHBCFG_GLBLINTRMSK		(1<<0)
+
+#define	GUSBCFG_CORRUPTTXPACKET		(1<<31)
+#define	GUSBCFG_FORCEDEVMODE		(1<<30)
+#define	GUSBCFG_FORCEHOSTMODE		(1<<29)
+#define	GUSBCFG_NO_PULLUP		(1<<27)
+#define	GUSBCFG_IC_USB_CAP		(1<<26)
+#define	GUSBCFG_TERMSELDLPULSE		(1<<22)
+#define	GUSBCFG_ULPIEXTVBUSINDICATOR	(1<<21)
+#define	GUSBCFG_ULPIEXTVBUSDRV		(1<<20)
+#define	GUSBCFG_ULPICLKSUSM		(1<<19)
+#define	GUSBCFG_ULPIAUTORES		(1<<18)
+#define	GUSBCFG_ULPIFSLS		(1<<17)
+#define	GUSBCFG_OTGI2CSEL		(1<<16)
+#define	GUSBCFG_PHYLPWRCLKSEL		(1<<15)
+#define	GUSBCFG_USBTRDTIM_MASK		0x00003c00
+#define	GUSBCFG_USBTRDTIM_SHIFT		10
+#define	GUSBCFG_TRD_TIM_SET(x)		(((x) & 15) << 10)
+#define	GUSBCFG_HNPCAP			(1<<9)
+#define	GUSBCFG_SRPCAP			(1<<8)
+#define	GUSBCFG_DDRSEL			(1<<7)
+#define	GUSBCFG_PHYSEL			(1<<6)
+#define	GUSBCFG_FSINTF			(1<<5)
+#define	GUSBCFG_ULPI_UTMI_SEL		(1<<4)
+#define	GUSBCFG_PHYIF			(1<<3)
+#define	GUSBCFG_TOUTCAL_MASK		0x00000007
+#define	GUSBCFG_TOUTCAL_SHIFT		0
+
+#define	GRSTCTL_AHBIDLE			(1<<31)
+#define	GRSTCTL_DMAREQ			(1<<30)
+#define	GRSTCTL_TXFNUM_MASK		0x000007c0
+#define	GRSTCTL_TXFNUM_SHIFT		6
+#define	GRSTCTL_TXFIFO(n)		(((n) & 31) << 6)
+#define	GRSTCTL_TXFFLSH			(1<<5)
+#define	GRSTCTL_RXFFLSH			(1<<4)
+#define	GRSTCTL_INTKNQFLSH		(1<<3)
+#define	GRSTCTL_FRMCNTRRST		(1<<2)
+#define	GRSTCTL_HSFTRST			(1<<1)
+#define	GRSTCTL_CSFTRST			(1<<0)
+
+#define	GINTSTS_WKUPINT			(1<<31)
+#define	GINTSTS_SESSREQINT		(1<<30)
+#define	GINTSTS_DISCONNINT		(1<<29)
+#define	GINTSTS_CONIDSTSCHNG		(1<<28)
+#define	GINTSTS_LPM			(1<<27)
+#define	GINTSTS_PTXFEMP			(1<<26)
+#define	GINTSTS_HCHINT			(1<<25)
+#define	GINTSTS_PRTINT			(1<<24)
+#define	GINTSTS_RESETDET		(1<<23)
+#define	GINTSTS_FETSUSP			(1<<22)
+#define	GINTSTS_INCOMPLP		(1<<21)
+#define	GINTSTS_INCOMPISOIN		(1<<20)
+#define	GINTSTS_OEPINT			(1<<19)
+#define	GINTSTS_IEPINT			(1<<18)
+#define	GINTSTS_EPMIS			(1<<17)
+#define	GINTSTS_RESTORE_DONE		(1<<16)
+#define	GINTSTS_EOPF			(1<<15)
+#define	GINTSTS_ISOOUTDROP		(1<<14)
+#define	GINTSTS_ENUMDONE		(1<<13)
+#define	GINTSTS_USBRST			(1<<12)
+#define	GINTSTS_USBSUSP			(1<<11)
+#define	GINTSTS_ERLYSUSP		(1<<10)
+#define	GINTSTS_I2CINT			(1<<9)
+#define	GINTSTS_ULPICKINT		(1<<8)
+#define	GINTSTS_GOUTNAKEFF		(1<<7)
+#define	GINTSTS_GINNAKEFF		(1<<6)
+#define	GINTSTS_NPTXFEMP		(1<<5)
+#define	GINTSTS_RXFLVL			(1<<4)
+#define	GINTSTS_SOF			(1<<3)
+#define	GINTSTS_OTGINT			(1<<2)
+#define	GINTSTS_MODEMIS			(1<<1)
+#define	GINTSTS_CURMOD			(1<<0)
+
+#define	GINTMSK_WKUPINTMSK		(1<<31)
+#define	GINTMSK_SESSREQINTMSK		(1<<30)
+#define	GINTMSK_DISCONNINTMSK		(1<<29)
+#define	GINTMSK_CONIDSTSCHNGMSK		(1<<28)
+#define	GINTMSK_PTXFEMPMSK		(1<<26)
+#define	GINTMSK_HCHINTMSK		(1<<25)
+#define	GINTMSK_PRTINTMSK		(1<<24)
+#define	GINTMSK_FETSUSPMSK		(1<<22)
+#define	GINTMSK_INCOMPLPMSK		(1<<21)
+#define	GINTMSK_INCOMPISOINMSK		(1<<20)
+#define	GINTMSK_OEPINTMSK		(1<<19)
+#define	GINTMSK_IEPINTMSK		(1<<18)
+#define	GINTMSK_EPMISMSK		(1<<17)
+#define	GINTMSK_EOPFMSK			(1<<15)
+#define	GINTMSK_ISOOUTDROPMSK		(1<<14)
+#define	GINTMSK_ENUMDONEMSK		(1<<13)
+#define	GINTMSK_USBRSTMSK		(1<<12)
+#define	GINTMSK_USBSUSPMSK		(1<<11)
+#define	GINTMSK_ERLYSUSPMSK		(1<<10)
+#define	GINTMSK_I2CINTMSK		(1<<9)
+#define	GINTMSK_ULPICKINTMSK		(1<<8)
+#define	GINTMSK_GOUTNAKEFFMSK		(1<<7)
+#define	GINTMSK_GINNAKEFFMSK		(1<<6)
+#define	GINTMSK_NPTXFEMPMSK		(1<<5)
+#define	GINTMSK_RXFLVLMSK		(1<<4)
+#define	GINTMSK_SOFMSK			(1<<3)
+#define	GINTMSK_OTGINTMSK		(1<<2)
+#define	GINTMSK_MODEMISMSK		(1<<1)
+#define	GINTMSK_CURMODMSK		(1<<0)
+
+#define	GRXSTSRH_PKTSTS_MASK		0x001e0000
+#define	GRXSTSRH_PKTSTS_SHIFT		17
+#define	GRXSTSRH_DPID_MASK		0x00018000
+#define	GRXSTSRH_DPID_SHIFT		15
+#define	GRXSTSRH_BCNT_MASK		0x00007ff0
+#define	GRXSTSRH_BCNT_SHIFT		4
+#define	GRXSTSRH_CHNUM_MASK		0x0000000f
+#define	GRXSTSRH_CHNUM_SHIFT		0
+
+#define	GRXSTSRD_FN_MASK		0x01e00000
+#define	GRXSTSRD_FN_GET(x)		(((x) >> 21) & 15)
+#define	GRXSTSRD_FN_SHIFT		21
+#define	GRXSTSRD_PKTSTS_MASK		0x001e0000
+#define	GRXSTSRD_PKTSTS_SHIFT		17
+#define	GRXSTSRH_IN_DATA		(2<<17)
+#define	GRXSTSRH_IN_COMPLETE		(3<<17)
+#define	GRXSTSRH_DT_ERROR		(5<<17)
+#define	GRXSTSRH_HALTED			(7<<17)
+#define	GRXSTSRD_GLOB_OUT_NAK		(1<<17)
+#define	GRXSTSRD_OUT_DATA		(2<<17)
+#define	GRXSTSRD_OUT_COMPLETE		(3<<17)
+#define	GRXSTSRD_STP_COMPLETE		(4<<17)
+#define	GRXSTSRD_STP_DATA		(6<<17)
+#define	GRXSTSRD_DPID_MASK		0x00018000
+#define	GRXSTSRD_DPID_SHIFT		15
+#define	GRXSTSRD_DPID_DATA0		(0<<15)
+#define	GRXSTSRD_DPID_DATA1		(2<<15)
+#define	GRXSTSRD_DPID_DATA2		(1<<15)
+#define	GRXSTSRD_PID_MDATA		(3<<15)
+#define	GRXSTSRD_BCNT_MASK		0x00007ff0
+#define	GRXSTSRD_BCNT_GET(x)		(((x) >> 4) & 0x7FF)
+#define	GRXSTSRD_BCNT_SHIFT		4
+#define	GRXSTSRD_CHNUM_MASK		0x0000000f
+#define	GRXSTSRD_CHNUM_GET(x)		((x) & 15)
+#define	GRXSTSRD_CHNUM_SHIFT		0
+
+#define	GRXFSIZ_RXFDEP_MASK		0x0000ffff
+#define	GRXFSIZ_RXFDEP_SHIFT		0
+
+#define	GNPTXFSIZ_NPTXFDEP_MASK		0xffff0000
+#define	GNPTXFSIZ_NPTXFDEP_SHIFT	0
+#define	GNPTXFSIZ_NPTXFSTADDR_MASK	0x0000ffff
+#define	GNPTXFSIZ_NPTXFSTADDR_SHIFT	16
+
+#define	GNPTXSTS_NPTXQTOP_SHIFT		24
+#define	GNPTXSTS_NPTXQTOP_MASK		0x7f000000
+#define	GNPTXSTS_NPTXQSPCAVAIL_SHIFT	16
+#define	GNPTXSTS_NPTXQSPCAVAIL_MASK	0x00ff0000
+#define	GNPTXSTS_NPTXFSPCAVAIL_SHIFT	0
+#define	GNPTXSTS_NPTXFSPCAVAIL_MASK	0x0000ffff
+
+#define	GI2CCTL_BSYDNE_SC		(1<<31)
+#define	GI2CCTL_RW			(1<<30)
+#define	GI2CCTL_I2CDATSE0		(1<<28)
+#define	GI2CCTL_I2CDEVADR_SHIFT		26
+#define	GI2CCTL_I2CDEVADR_MASK		0x0c000000
+#define	GI2CCTL_I2CSUSPCTL		(1<<25)
+#define	GI2CCTL_ACK			(1<<24)
+#define	GI2CCTL_I2CEN			(1<<23)
+#define	GI2CCTL_ADDR_SHIFT		16
+#define	GI2CCTL_ADDR_MASK		0x007f0000
+#define	GI2CCTL_REGADDR_SHIFT		8
+#define	GI2CCTL_REGADDR_MASK		0x0000ff00
+#define	GI2CCTL_RWDATA_SHIFT		0
+#define	GI2CCTL_RWDATA_MASK		0x000000ff
+
+#define	GPVNDCTL_DISULPIDRVR		(1<<31)
+#define	GPVNDCTL_VSTSDONE		(1<<27)
+#define	GPVNDCTL_VSTSBSY		(1<<26)
+#define	GPVNDCTL_NEWREGREQ		(1<<25)
+#define	GPVNDCTL_REGWR			(1<<22)
+#define	GPVNDCTL_REGADDR_SHIFT		16
+#define	GPVNDCTL_REGADDR_MASK		0x003f0000
+#define	GPVNDCTL_VCTRL_SHIFT		8
+#define	GPVNDCTL_VCTRL_MASK		0x0000ff00
+#define	GPVNDCTL_REGDATA_SHIFT		0
+#define	GPVNDCTL_REGDATA_MASK		0x000000ff
+
+#define	GGPIO_GPO_SHIFT			16
+#define	GGPIO_GPO_MASK			0xffff0000
+#define	GGPIO_GPI_SHIFT			0
+#define	GGPIO_GPI_MASK			0x0000ffff
+
+#define	GHWCFG1_GET_DIR(x, n)		(((x) >> (2 * (n))) & 3)
+#define	GHWCFG1_BIDIR			0
+#define	GHWCFG1_IN			1
+#define	GHWCFG1_OUT			2
+
+#define	GHWCFG2_TKNQDEPTH_SHIFT		26
+#define	GHWCFG2_TKNQDEPTH_MASK		0x7c000000
+#define	GHWCFG2_PTXQDEPTH_SHIFT		24
+#define	GHWCFG2_PTXQDEPTH_MASK		0x03000000
+#define	GHWCFG2_NPTXQDEPTH_SHIFT	22
+#define	GHWCFG2_NPTXQDEPTH_MASK		0x00c00000
+#define	GHWCFG2_MPI			(1<<20)
+#define	GHWCFG2_DYNFIFOSIZING		(1<<19)
+#define	GHWCFG2_PERIOSUPPORT		(1<<18)
+#define	GHWCFG2_NUMHSTCHNL_SHIFT	14
+#define	GHWCFG2_NUMHSTCHNL_MASK		0x0003c000
+#define	GHWCFG2_NUMHSTCHNL_GET(x)	((((x) >> 14) & 15) + 1)
+#define	GHWCFG2_NUMDEVEPS_SHIFT		10
+#define	GHWCFG2_NUMDEVEPS_MASK		0x00003c00
+#define	GHWCFG2_NUMDEVEPS_GET(x)	((((x) >> 10) & 15) + 1)
+#define	GHWCFG2_FSPHYTYPE_SHIFT		8
+#define	GHWCFG2_FSPHYTYPE_MASK		0x00000300
+#define	GHWCFG2_HSPHYTYPE_SHIFT		6
+#define	GHWCFG2_HSPHYTYPE_MASK		0x000000c0
+#define	GHWCFG2_SINGPNT			(1<<5)
+#define	GHWCFG2_OTGARCH_SHIFT		3
+#define	GHWCFG2_OTGARCH_MASK		0x00000018
+#define	GHWCFG2_OTGMODE_SHIFT		0
+#define	GHWCFG2_OTGMODE_MASK		0x00000007
+
+#define	GHWCFG3_DFIFODEPTH_SHIFT	16
+#define	GHWCFG3_DFIFODEPTH_MASK		0xffff0000
+#define	GHWCFG3_DFIFODEPTH_GET(x)	((x) >> 16)
+#define	GHWCFG3_RSTTYPE			(1<<11)
+#define	GHWCFG3_OPTFEATURE		(1<<10)
+#define	GHWCFG3_VNDCTLSUPT		(1<<9)
+#define	GHWCFG3_I2CINTSEL		(1<<8)
+#define	GHWCFG3_OTGEN			(1<<7)
+#define	GHWCFG3_PKTSIZEWIDTH_SHIFT	4
+#define	GHWCFG3_PKTSIZEWIDTH_MASK	0x00000070
+#define	GHWCFG3_PKTSIZE_GET(x)		(0x10<<(((x) >> 4) & 7))
+#define	GHWCFG3_XFERSIZEWIDTH_SHIFT	0
+#define	GHWCFG3_XFERSIZEWIDTH_MASK	0x0000000f
+#define	GHWCFG3_XFRRSIZE_GET(x)		(0x400<<(((x) >> 0) & 15))
+
+#define	GHWCFG4_NUM_IN_EP_GET(x)	((((x) >> 26) & 15) + 1)
+#define	GHWCFG4_SESSENDFLTR		(1<<24)
+#define	GHWCFG4_BVALIDFLTR		(1<<23)
+#define	GHWCFG4_AVALIDFLTR		(1<<22)
+#define	GHWCFG4_VBUSVALIDFLTR		(1<<21)
+#define	GHWCFG4_IDDGFLTR		(1<<20)
+#define	GHWCFG4_NUMCTLEPS_SHIFT		16
+#define	GHWCFG4_NUMCTLEPS_MASK		0x000f0000
+#define	GHWCFG4_NUMCTLEPS_GET(x)	(((x) >> 16) & 15)
+#define	GHWCFG4_PHYDATAWIDTH_SHIFT	14
+#define	GHWCFG4_PHYDATAWIDTH_MASK	0x0000c000
+#define	GHWCFG4_AHBFREQ			(1<<5)
+#define	GHWCFG4_ENABLEPWROPT		(1<<4)
+#define	GHWCFG4_NUMDEVPERIOEPS_SHIFT	0
+#define	GHWCFG4_NUMDEVPERIOEPS_MASK	0x0000000f
+#define	GHWCFG4_NUMDEVPERIOEPS_GET(x)	(((x) >> 0) & 15)
+
+#define	GLPMCFG_HSIC_CONN		(1<<30)
+
+#define	GPWRDN_BVALID			(1<<22)
+#define	GPWRDN_IDDIG			(1<<21)
+#define	GPWRDN_CONNDET_INT		(1<<14)
+#define	GPWRDN_CONNDET			(1<<13)
+#define	GPWRDN_DISCONN_INT		(1<<12)
+#define	GPWRDN_DISCONN			(1<<11)
+#define	GPWRDN_RESETDET_INT		(1<<10)
+#define	GPWRDN_RESETDET			(1<<9)
+#define	GPWRDN_LINESTATE_INT		(1<<8)
+#define	GPWRDN_LINESTATE		(1<<7)
+#define	GPWRDN_DISABLE_VBUS		(1<<6)
+#define	GPWRDN_POWER_DOWN		(1<<5)
+#define	GPWRDN_POWER_DOWN_RST		(1<<4)
+#define	GPWRDN_POWER_DOWN_CLAMP		(1<<3)
+#define	GPWRDN_RESTORE			(1<<2)
+#define	GPWRDN_PMU_ACTIVE		(1<<1)
+#define	GPWRDN_PMU_IRQ_SEL		(1<<0)
+
+#define	HPTXFSIZ_PTXFSIZE_SHIFT		16
+#define	HPTXFSIZ_PTXFSIZE_MASK		0xffff0000
+#define	HPTXFSIZ_PTXFSTADDR_SHIFT	0
+#define	HPTXFSIZ_PTXFSTADDR_MASK	0x0000ffff
+
+#define	DPTXFSIZN_DPTXFSIZE_SHIFT	16
+#define	DPTXFSIZN_DPTXFSIZE_MASK	0xffff0000
+#define	DPTXFSIZN_PTXFSTADDR_SHIFT	0
+#define	DPTXFSIZN_PTXFSTADDR_MASK	0x0000ffff
+
+#define	DIEPTXFN_INEPNTXFDEP_SHIFT	16
+#define	DIEPTXFN_INEPNTXFDEP_MASK	0xffff0000
+#define	DIEPTXFN_INEPNTXFSTADDR_SHIFT	0
+#define	DIEPTXFN_INEPNTXFSTADDR_MASK	0x0000ffff
+
+#define	HCFG_FSLSSUPP			(1<<2)
+#define	HCFG_FSLSPCLKSEL_SHIFT		0
+#define	HCFG_FSLSPCLKSEL_MASK		0x00000003
+
+#define	HFIR_FRINT_SHIFT		0
+#define	HFIR_FRINT_MASK			0x0000ffff
+
+#define	HFNUM_FRREM_SHIFT		16
+#define	HFNUM_FRREM_MASK		0xffff0000
+#define	HFNUM_FRNUM_SHIFT		0
+#define	HFNUM_FRNUM_MASK		0x0000ffff
+
+#define	HPTXSTS_PTXQTOP_SHIFT		24
+#define	HPTXSTS_PTXQTOP_MASK		0xff000000
+#define	HPTXSTS_PTXQSPCAVAIL_SHIFT	16
+#define	HPTXSTS_PTXQSPCAVAIL_MASK	0x00ff0000
+#define	HPTXSTS_PTXFSPCAVAIL_SHIFT	0
+#define	HPTXSTS_PTXFSPCAVAIL_MASK	0x0000ffff
+
+#define	HAINT_HAINT_SHIFT		0
+#define	HAINT_HAINT_MASK		0x0000ffff
+#define	HAINTMSK_HAINTMSK_SHIFT		0
+#define	HAINTMSK_HAINTMSK_MASK		0x0000ffff
+
+#define	HPRT_PRTSPD_SHIFT		17
+#define	HPRT_PRTSPD_MASK		0x00060000
+#define	HPRT_PRTSPD_HIGH		0
+#define	HPRT_PRTSPD_FULL		1
+#define	HPRT_PRTSPD_LOW			2
+#define	HPRT_PRTSPD_MASK		0x00060000
+#define	HPRT_PRTTSTCTL_SHIFT		13
+#define	HPRT_PRTTSTCTL_MASK		0x0001e000
+#define	HPRT_PRTPWR			(1<<12)
+#define	HPRT_PRTLNSTS_SHIFT		10
+#define	HPRT_PRTLNSTS_MASK		0x00000c00
+#define	HPRT_PRTRST			(1<<8)
+#define	HPRT_PRTSUSP			(1<<7)
+#define	HPRT_PRTRES			(1<<6)
+#define	HPRT_PRTOVRCURRCHNG		(1<<5)
+#define	HPRT_PRTOVRCURRACT		(1<<4)
+#define	HPRT_PRTENCHNG			(1<<3)
+#define	HPRT_PRTENA			(1<<2)
+#define	HPRT_PRTCONNDET			(1<<1)
+#define	HPRT_PRTCONNSTS			(1<<0)
+
+#define	HCCHAR_CHENA			(1<<31)
+#define	HCCHAR_CHDIS			(1<<30)
+#define	HCCHAR_ODDFRM			(1<<29)
+#define	HCCHAR_DEVADDR_SHIFT		22
+#define	HCCHAR_DEVADDR_MASK		0x1fc00000
+#define	HCCHAR_MC_EC_SHIFT		20
+#define	HCCHAR_MC_EC_MASK		0x00300000
+#define	HCCHAR_EC_SHIFT			20
+#define	HCCHAR_EC_MASK			0x00300000
+#define	HCCHAR_EPTYPE_SHIFT		18
+#define	HCCHAR_EPTYPE_MASK		0x000c0000
+#define	HCCHAR_LSPDDEV			(1<<17)
+#define	HCCHAR_EPDIR			(1<<15)
+#define	HCCHAR_EPDIR_IN			(1<<15)
+#define	HCCHAR_EPDIR_OUT		0
+#define	HCCHAR_EPNUM_SHIFT		11
+#define	HCCHAR_EPNUM_MASK		0x00007800
+#define	HCCHAR_MPS_SHIFT		0
+#define	HCCHAR_MPS_MASK			0x000007ff
+
+#define	HCSPLT_SPLTENA			(1<<31)
+#define	HCSPLT_COMPSPLT		(1<<16)
+#define	HCSPLT_XACTPOS_SHIFT		14
+#define	HCSPLT_XACTPOS_MASK		0x0000c000
+#define	HCSPLT_HUBADDR_SHIFT		7
+#define	HCSPLT_HUBADDR_MASK		0x00003f80
+#define	HCSPLT_PRTADDR_SHIFT		0
+#define	HCSPLT_PRTADDR_MASK		0x0000007f
+
+#define	HCINT_DATATGLERR		(1<<10)
+#define	HCINT_FRMOVRUN			(1<<9)
+#define	HCINT_BBLERR			(1<<8)
+#define	HCINT_XACTERR			(1<<7)
+#define	HCINT_NYET			(1<<6)
+#define	HCINT_ACK			(1<<5)
+#define	HCINT_NAK			(1<<4)
+#define	HCINT_STALL			(1<<3)
+#define	HCINT_AHBERR			(1<<2)
+#define	HCINT_CHHLTD			(1<<1)
+#define	HCINT_XFERCOMPL			(1<<0)
+
+#define	HCINTMSK_DATATGLERRMSK		(1<<10)
+#define	HCINTMSK_FRMOVRUNMSK		(1<<9)
+#define	HCINTMSK_BBLERRMSK		(1<<8)
+#define	HCINTMSK_XACTERRMSK		(1<<7)
+#define	HCINTMSK_NYETMSK		(1<<6)
+#define	HCINTMSK_ACKMSK			(1<<5)
+#define	HCINTMSK_NAKMSK			(1<<4)
+#define	HCINTMSK_STALLMSK		(1<<3)
+#define	HCINTMSK_AHBERRMSK		(1<<2)
+#define	HCINTMSK_CHHLTDMSK		(1<<1)
+#define	HCINTMSK_XFERCOMPLMSK		(1<<0)
+
+#define	HCTSIZ_DOPNG			(1<<31)
+#define	HCTSIZ_PID_SHIFT		29
+#define	HCTSIZ_PID_MASK			0x60000000
+#define	HCTSIZ_PID_DATA0		0
+#define	HCTSIZ_PID_DATA2		1
+#define	HCTSIZ_PID_DATA1		2
+#define	HCTSIZ_PID_MDATA		3
+#define	HCTSIZ_PID_SETUP		3
+#define	HCTSIZ_PKTCNT_SHIFT		19
+#define	HCTSIZ_PKTCNT_MASK		0x1ff80000
+#define	HCTSIZ_XFERSIZE_SHIFT		0
+#define	HCTSIZ_XFERSIZE_MASK		0x0007ffff
+
+#define	DCFG_EPMISCNT_SHIFT		18
+#define	DCFG_EPMISCNT_MASK		0x007c0000
+#define	DCFG_PERFRINT_SHIFT		11
+#define	DCFG_PERFRINT_MASK		0x00001800
+#define	DCFG_DEVADDR_SHIFT		4
+#define	DCFG_DEVADDR_MASK		0x000007f0
+#define	DCFG_DEVADDR_SET(x)		(((x) & 0x7F) << 4)
+#define	DCFG_NZSTSOUTHSHK		(1<<2)
+#define	DCFG_DEVSPD_SHIFT		0
+#define	DCFG_DEVSPD_MASK		0x00000003
+#define	DCFG_DEVSPD_SET(x)		((x) & 0x3)
+#define	DCFG_DEVSPD_HI			0
+#define	DCFG_DEVSPD_FULL20		1
+#define	DCFG_DEVSPD_FULL10		3
+
+#define	DCTL_PWRONPRGDONE		(1<<11)
+#define	DCTL_CGOUTNAK			(1<<10)
+#define	DCTL_SGOUTNAK			(1<<9)
+#define	DCTL_CGNPINNAK			(1<<8)
+#define	DCTL_SGNPINNAK			(1<<7)
+#define	DCTL_TSTCTL_SHIFT		4
+#define	DCTL_TSTCTL_MASK		0x00000070
+#define	DCTL_GOUTNAKSTS			(1<<3)
+#define	DCTL_GNPINNAKSTS		(1<<2)
+#define	DCTL_SFTDISCON			(1<<1)
+#define	DCTL_RMTWKUPSIG			(1<<0)
+
+#define	DSTS_SOFFN_SHIFT		8
+#define	DSTS_SOFFN_MASK			0x003fff00
+#define	DSTS_SOFFN_GET(x)		(((x) >> 8) & 0x3FFF)
+#define	DSTS_ERRTICERR			(1<<3)
+#define	DSTS_ENUMSPD_SHIFT		1
+#define	DSTS_ENUMSPD_MASK		0x00000006
+#define	DSTS_ENUMSPD_GET(x)		(((x) >> 1) & 3)
+#define	DSTS_ENUMSPD_HI			0
+#define	DSTS_ENUMSPD_FULL20		1
+#define	DSTS_ENUMSPD_LOW10		2
+#define	DSTS_ENUMSPD_FULL10		3
+#define	DSTS_SUSPSTS			(1<<0)
+
+#define	DIEPMSK_TXFIFOUNDRNMSK		(1<<8)
+#define	DIEPMSK_INEPNAKEFFMSK		(1<<6)
+#define	DIEPMSK_INTKNEPMISMSK		(1<<5)
+#define	DIEPMSK_INTKNTXFEMPMSK		(1<<4)
+#define	DIEPMSK_FIFOEMPTY		(1<<4)
+#define	DIEPMSK_TIMEOUTMSK		(1<<3)
+#define	DIEPMSK_AHBERRMSK		(1<<2)
+#define	DIEPMSK_EPDISBLDMSK		(1<<1)
+#define	DIEPMSK_XFERCOMPLMSK		(1<<0)
+
+#define	DOEPMSK_OUTPKTERRMSK		(1<<8)
+#define	DOEPMSK_BACK2BACKSETUP		(1<<6)
+#define	DOEPMSK_OUTTKNEPDISMSK		(1<<4)
+#define	DOEPMSK_FIFOEMPTY		(1<<4)
+#define	DOEPMSK_SETUPMSK		(1<<3)
+#define	DOEPMSK_AHBERRMSK		(1<<2)
+#define	DOEPMSK_EPDISBLDMSK		(1<<1)
+#define	DOEPMSK_XFERCOMPLMSK		(1<<0)
+
+#define	DIEPINT_TXFIFOUNDRN		(1<<8)
+#define	DIEPINT_INEPNAKEFF		(1<<6)
+#define	DIEPINT_INTKNEPMIS		(1<<5)
+#define	DIEPINT_INTKNTXFEMP		(1<<4)
+#define	DIEPINT_TIMEOUT			(1<<3)
+#define	DIEPINT_AHBERR			(1<<2)
+#define	DIEPINT_EPDISBLD		(1<<1)
+#define	DIEPINT_XFERCOMPL		(1<<0)
+
+#define	DOEPINT_OUTPKTERR		(1<<8)
+#define	DOEPINT_BACK2BACKSETUP		(1<<6)
+#define	DOEPINT_OUTTKNEPDIS		(1<<4)
+#define	DOEPINT_SETUP			(1<<3)
+#define	DOEPINT_AHBERR			(1<<2)
+#define	DOEPINT_EPDISBLD		(1<<1)
+#define	DOEPINT_XFERCOMPL		(1<<0)
+
+#define	DAINT_INEPINT_MASK		0xffff0000
+#define	DAINT_INEPINT_SHIFT		0
+#define	DAINT_OUTEPINT_MASK		0x0000ffff
+#define	DAINT_OUTEPINT_SHIFT		16
+
+#define	DAINTMSK_INEPINT_MASK		0xffff0000
+#define	DAINTMSK_INEPINT_SHIFT		0
+#define	DAINTMSK_OUTEPINT_MASK		0x0000ffff
+#define	DAINTMSK_OUTEPINT_SHIFT		16
+
+#define	DTKNQR1_EPTKN_SHIFT		8
+#define	DTKNQR1_EPTKN_MASK		0xffffff00
+#define	DTKNQR1_WRAPBIT			(1<<7)
+#define	DTKNQR1_INTKNWPTR_SHIFT		0
+#define	DTKNQR1_INTKNWPTR_MASK		0x0000001f
+
+#define	DVBUSDIS_DVBUSDIS_SHIFT		0
+#define	DVBUSDIS_DVBUSDIS_MASK		0x0000ffff
+
+#define	DVBUSPULSE_DVBUSPULSE_SHIFT	0
+#define	DVBUSPULSE_DVBUSPULSE_MASK	0x00000fff
+
+#define	DTHRCTL_ARBPRKEN		(1<<27)
+#define	DTHRCTL_RXTHRLEN_SHIFT		17
+#define	DTHRCTL_RXTHRLEN_MASK		0x03fe0000
+#define	DTHRCTL_RXTHREN			(1<<16)
+#define	DTHRCTL_TXTHRLEN_SHIFT		2
+#define	DTHRCTL_TXTHRLEN_MASK		0x000007fc
+#define	DTHRCTL_ISOTHREN		(1<<1)
+#define	DTHRCTL_NONISOTHREN		(1<<0)
+
+#define	DIEPEMPMSK_INEPTXFEMPMSK_SHIFT	0
+#define	DIEPEMPMSK_INEPTXFEMPMSK_MASK	0x0000ffff
+
+#define	DIEPCTL_EPENA			(1<<31)
+#define	DIEPCTL_EPDIS			(1<<30)
+#define	DIEPCTL_SETD1PID		(1<<29)
+#define	DIEPCTL_SETD0PID		(1<<28)
+#define	DIEPCTL_SNAK			(1<<27)
+#define	DIEPCTL_CNAK			(1<<26)
+#define	DIEPCTL_TXFNUM_SHIFT		22
+#define	DIEPCTL_TXFNUM_MASK		0x03c00000
+#define	DIEPCTL_TXFNUM_SET(n)		(((n) & 15) << 22)
+#define	DIEPCTL_STALL			(1<<21)
+#define	DIEPCTL_EPTYPE_SHIFT		18
+#define	DIEPCTL_EPTYPE_MASK		0x000c0000
+#define	DIEPCTL_EPTYPE_SET(n)		(((n) & 3) << 18)
+#define	DIEPCTL_EPTYPE_CONTROL		0
+#define	DIEPCTL_EPTYPE_ISOC		1
+#define	DIEPCTL_EPTYPE_BULK		2
+#define	DIEPCTL_EPTYPE_INTERRUPT	3
+#define	DIEPCTL_NAKSTS			(1<<17)
+#define	DIEPCTL_USBACTEP		(1<<15)
+#define	DIEPCTL_NEXTEP_SHIFT		11
+#define	DIEPCTL_NEXTEP_MASK		0x00007800
+#define	DIEPCTL_MPS_SHIFT		0
+#define	DIEPCTL_MPS_MASK		0x000007ff
+#define	DIEPCTL_MPS_SET(n)		((n) & 0x7FF)
+#define	DIEPCTL_MPS_64			(0<<0)
+#define	DIEPCTL_MPS_32			(1<<0)
+#define	DIEPCTL_MPS_16			(2<<0)
+#define	DIEPCTL_MPS_8			(3<<0)
+
+#define	DOEPCTL_EPENA			(1<<31)
+#define	DOEPCTL_EPDIS			(1<<30)
+#define	DOEPCTL_SETD1PID		(1<<29)
+#define	DOEPCTL_SETD0PID		(1<<28)
+#define	DOEPCTL_SNAK			(1<<27)
+#define	DOEPCTL_CNAK			(1<<26)
+#define	DOEPCTL_FNUM_SET(n)		(((n) & 15) << 22)
+#define	DOEPCTL_STALL			(1<<21)
+#define	DOEPCTL_EPTYPE_SHIFT		18
+#define	DOEPCTL_EPTYPE_MASK		0x000c0000
+#define	DOEPCTL_EPTYPE_SET(n)		(((n) & 3) << 18)
+#define	DOEPCTL_NAKSTS			(1<<17)
+#define	DOEPCTL_USBACTEP		(1<<15)
+#define	DOEPCTL_MPS_SHIFT		0
+#define	DOEPCTL_MPS_MASK		0x000007ff
+#define	DOEPCTL_MPS_SET(n)		((n) & 0x7FF)
+#define	DOEPCTL_MPS_64			(0<<0)
+#define	DOEPCTL_MPS_32			(1<<0)
+#define	DOEPCTL_MPS_16			(2<<0)
+#define	DOEPCTL_MPS_8			(3<<0)
+
+/* common bits */
+#define	DXEPINT_TXFEMP			(1<<7)
+#define	DXEPINT_SETUP			(1<<3)
+#define	DXEPINT_XFER_COMPL		(1<<0)
+
+#define	DIEPTSIZ_XFERSIZE_MASK		0x0007ffff
+#define	DIEPTSIZ_XFERSIZE_SHIFT		0
+#define	DIEPTSIZ_PKTCNT_MASK		0x1ff80000
+#define	DIEPTSIZ_PKTCNT_SHIFT		19
+#define	DIEPTSIZ_MC_MASK		0x60000000
+#define	DIEPTSIZ_MC_SHIFT		29
+
+#define	DOEPTSIZ_XFERSIZE_MASK		0x0007ffff
+#define	DOEPTSIZ_XFERSIZE_SHIFT		0
+#define	DOEPTSIZ_PKTCNT_MASK		0x1ff80000
+#define	DOEPTSIZ_PKTCNT_SHIFT		19
+#define	DOEPTSIZ_MC_MASK		0x60000000
+#define	DOEPTSIZ_MC_SHIFT		29
+
+/* common bits */
+#define	DXEPTSIZ_SET_MULTI(n)		(((n) & 3) << 29)
+#define	DXEPTSIZ_SET_NPKT(n)		(((n) & 0x3FF) << 19)
+#define	DXEPTSIZ_GET_NPKT(n)		(((n) >> 19) & 0x3FF)
+#define	DXEPTSIZ_SET_NBYTES(n)		(((n) & 0x7FFFFF) << 0)
+#define	DXEPTSIZ_GET_NBYTES(n)		(((n) >> 0) & 0x7FFFFF)
+
+/* generic endpoint mask */
+
+#define	ENDPOINT_MASK(x,in) \
+	((in) ? (1U << ((x) & 15U)) : \
+	 (0x10000U << ((x) & 15U)))
+
+#endif					/* _DWC_OTGREG_H_ */