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author | semenu <semenu@FreeBSD.org> | 2002-04-19 22:43:57 +0000 |
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committer | semenu <semenu@FreeBSD.org> | 2002-04-19 22:43:57 +0000 |
commit | b986d07861eecdef69a75b36aa1d84a75c44e519 (patch) | |
tree | 451e0dd2dec8d61e952b33483feffd388d23282e /sys/dev/tx/if_txvar.h | |
parent | 3e109d2cd3931ca713003306981eb9c6e33c03c6 (diff) | |
download | FreeBSD-src-b986d07861eecdef69a75b36aa1d84a75c44e519.zip FreeBSD-src-b986d07861eecdef69a75b36aa1d84a75c44e519.tar.gz |
Move tx(4) driver to sys/dev/tx. BTW split hardware structures and constants
into if_txreg.h.
MFC after: 1 week
Diffstat (limited to 'sys/dev/tx/if_txvar.h')
-rw-r--r-- | sys/dev/tx/if_txvar.h | 228 |
1 files changed, 1 insertions, 227 deletions
diff --git a/sys/dev/tx/if_txvar.h b/sys/dev/tx/if_txvar.h index 7a5c82b..c716a99 100644 --- a/sys/dev/tx/if_txvar.h +++ b/sys/dev/tx/if_txvar.h @@ -32,7 +32,7 @@ */ /*#define EPIC_DEBUG 1*/ /*#define EPIC_USEIOSPACE 1*/ -#define EARLY_RX 1 +#define EPIC_EARLY_RX 1 #ifndef ETHER_MAX_LEN #define ETHER_MAX_LEN 1518 @@ -50,214 +50,6 @@ #define RX_RING_MASK (RX_RING_SIZE - 1) #define ETHER_MAX_FRAME_LEN (ETHER_MAX_LEN + ETHER_CRC_LEN) -#define EPIC_MAX_MTU 1600 /* This is experiment-derived value */ - -/* PCI aux configuration registers */ -#if defined(__FreeBSD__) -#define PCIR_BASEIO (PCIR_MAPS + 0x0) /* Base IO Address */ -#define PCIR_BASEMEM (PCIR_MAPS + 0x4) /* Base Memory Address */ -#else /* __OpenBSD__ */ -#define PCI_BASEIO (PCI_MAPS + 0x0) /* Base IO Address */ -#define PCI_BASEMEM (PCI_MAPS + 0x4) /* Base Memory Address */ -#endif /* __FreeBSD__ */ - -/* PCI identification */ -#define SMC_VENDORID 0x10B8 -#define SMC_DEVICEID_83C170 0x0005 - -/* EPIC's registers */ -#define COMMAND 0x0000 -#define INTSTAT 0x0004 /* Interrupt status. See below */ -#define INTMASK 0x0008 /* Interrupt mask. See below */ -#define GENCTL 0x000C -#define NVCTL 0x0010 -#define EECTL 0x0014 /* EEPROM control **/ -#define TEST1 0x001C /* XXXXX */ -#define CRCCNT 0x0020 /* CRC error counter */ -#define ALICNT 0x0024 /* FrameTooLang error counter */ -#define MPCNT 0x0028 /* MissedFrames error counters */ -#define MIICTL 0x0030 -#define MIIDATA 0x0034 -#define MIICFG 0x0038 -#define IPG 0x003C -#define LAN0 0x0040 /* MAC address */ -#define LAN1 0x0044 /* MAC address */ -#define LAN2 0x0048 /* MAC address */ -#define ID_CHK 0x004C -#define MC0 0x0050 /* Multicast filter table */ -#define MC1 0x0054 /* Multicast filter table */ -#define MC2 0x0058 /* Multicast filter table */ -#define MC3 0x005C /* Multicast filter table */ -#define RXCON 0x0060 /* Rx control register */ -#define TXCON 0x0070 /* Tx control register */ -#define TXSTAT 0x0074 -#define PRCDAR 0x0084 /* RxRing bus address */ -#define PRSTAT 0x00A4 -#define PRCPTHR 0x00B0 -#define PTCDAR 0x00C4 /* TxRing bus address */ -#define ETXTHR 0x00DC - -#define COMMAND_STOP_RX 0x01 -#define COMMAND_START_RX 0x02 -#define COMMAND_TXQUEUED 0x04 -#define COMMAND_RXQUEUED 0x08 -#define COMMAND_NEXTFRAME 0x10 -#define COMMAND_STOP_TDMA 0x20 -#define COMMAND_STOP_RDMA 0x40 -#define COMMAND_TXUGO 0x80 - -/* Interrupt register bits */ -#define INTSTAT_RCC 0x00000001 -#define INTSTAT_HCC 0x00000002 -#define INTSTAT_RQE 0x00000004 -#define INTSTAT_OVW 0x00000008 -#define INTSTAT_RXE 0x00000010 -#define INTSTAT_TXC 0x00000020 -#define INTSTAT_TCC 0x00000040 -#define INTSTAT_TQE 0x00000080 -#define INTSTAT_TXU 0x00000100 -#define INTSTAT_CNT 0x00000200 -#define INTSTAT_PREI 0x00000400 -#define INTSTAT_RCT 0x00000800 -#define INTSTAT_FATAL 0x00001000 /* One of DPE,APE,PMA,PTA happend */ -#define INTSTAT_UNUSED1 0x00002000 -#define INTSTAT_UNUSED2 0x00004000 -#define INTSTAT_GP2 0x00008000 /* PHY Event */ -#define INTSTAT_INT_ACTV 0x00010000 -#define INTSTAT_RXIDLE 0x00020000 -#define INTSTAT_TXIDLE 0x00040000 -#define INTSTAT_RCIP 0x00080000 -#define INTSTAT_TCIP 0x00100000 -#define INTSTAT_RBE 0x00200000 -#define INTSTAT_RCTS 0x00400000 -#define INTSTAT_RSV 0x00800000 -#define INTSTAT_DPE 0x01000000 /* PCI Fatal error */ -#define INTSTAT_APE 0x02000000 /* PCI Fatal error */ -#define INTSTAT_PMA 0x04000000 /* PCI Fatal error */ -#define INTSTAT_PTA 0x08000000 /* PCI Fatal error */ - -#define GENCTL_SOFT_RESET 0x00000001 -#define GENCTL_ENABLE_INTERRUPT 0x00000002 -#define GENCTL_SOFTWARE_INTERRUPT 0x00000004 -#define GENCTL_POWER_DOWN 0x00000008 -#define GENCTL_ONECOPY 0x00000010 -#define GENCTL_BIG_ENDIAN 0x00000020 -#define GENCTL_RECEIVE_DMA_PRIORITY 0x00000040 -#define GENCTL_TRANSMIT_DMA_PRIORITY 0x00000080 -#define GENCTL_RECEIVE_FIFO_THRESHOLD128 0x00000300 -#define GENCTL_RECEIVE_FIFO_THRESHOLD96 0x00000200 -#define GENCTL_RECEIVE_FIFO_THRESHOLD64 0x00000100 -#define GENCTL_RECEIVE_FIFO_THRESHOLD32 0x00000000 -#define GENCTL_MEMORY_READ_LINE 0x00000400 -#define GENCTL_MEMORY_READ_MULTIPLE 0x00000800 -#define GENCTL_SOFTWARE1 0x00001000 -#define GENCTL_SOFTWARE2 0x00002000 -#define GENCTL_RESET_PHY 0x00004000 - -#define NVCTL_ENABLE_MEMORY_MAP 0x00000001 -#define NVCTL_CLOCK_RUN_SUPPORTED 0x00000002 -#define NVCTL_GP1_OUTPUT_ENABLE 0x00000004 -#define NVCTL_GP2_OUTPUT_ENABLE 0x00000008 -#define NVCTL_GP1 0x00000010 -#define NVCTL_GP2 0x00000020 -#define NVCTL_CARDBUS_MODE 0x00000040 -#define NVCTL_IPG_DELAY_MASK(x) ((x&0xF)<<7) - -#define RXCON_SAVE_ERRORED_PACKETS 0x00000001 -#define RXCON_RECEIVE_RUNT_FRAMES 0x00000002 -#define RXCON_RECEIVE_BROADCAST_FRAMES 0x00000004 -#define RXCON_RECEIVE_MULTICAST_FRAMES 0x00000008 -#define RXCON_RECEIVE_INVERSE_INDIVIDUAL_ADDRESS_FRAMES 0x00000010 -#define RXCON_PROMISCUOUS_MODE 0x00000020 -#define RXCON_MONITOR_MODE 0x00000040 -#define RXCON_EARLY_RECEIVE_ENABLE 0x00000080 -#define RXCON_EXTERNAL_BUFFER_DISABLE 0x00000000 -#define RXCON_EXTERNAL_BUFFER_16K 0x00000100 -#define RXCON_EXTERNAL_BUFFER_32K 0x00000200 -#define RXCON_EXTERNAL_BUFFER_128K 0x00000300 - -#define TXCON_EARLY_TRANSMIT_ENABLE 0x00000001 -#define TXCON_LOOPBACK_DISABLE 0x00000000 -#define TXCON_LOOPBACK_MODE_INT 0x00000002 -#define TXCON_LOOPBACK_MODE_PHY 0x00000004 -#define TXCON_LOOPBACK_MODE 0x00000006 -#define TXCON_FULL_DUPLEX 0x00000006 -#define TXCON_SLOT_TIME 0x00000078 - -#define MIICFG_SERIAL_ENABLE 0x00000001 -#define MIICFG_694_ENABLE 0x00000002 -#define MIICFG_694_STATUS 0x00000004 -#define MIICFG_PHY_PRESENT 0x00000008 -#define MIICFG_SMI_ENABLE 0x00000010 - -#define TEST1_CLOCK_TEST 0x00000008 - -/* - * Some default values - */ -#define TXCON_DEFAULT (TXCON_SLOT_TIME | TXCON_EARLY_TRANSMIT_ENABLE) -#define TRANSMIT_THRESHOLD 0x300 - -#if defined(EARLY_RX) -#define RXCON_EARLY (RXCON_EARLY_RECEIVE_ENABLE | \ - RXCON_SAVE_ERRORED_PACKETS) -#else -#define RXCON_EARLY (0) -#endif - -#define RXCON_DEFAULT (RXCON_EARLY | \ - RXCON_RECEIVE_MULTICAST_FRAMES | \ - RXCON_RECEIVE_BROADCAST_FRAMES) -/* - * EEPROM structure - * SMC9432* eeprom is organized by words and only first 8 words - * have distinctive meaning (according to datasheet) - */ -#define EEPROM_MAC0 0x0000 /* Byte 0 / Byte 1 */ -#define EEPROM_MAC1 0x0001 /* Byte 2 / Byte 3 */ -#define EEPROM_MAC2 0x0002 /* Byte 4 / Byte 5 */ -#define EEPROM_BID_CSUM 0x0003 /* Board Id / Check Sum */ -#define EEPROM_NVCTL 0x0004 /* NVCTL (bits 0-5) / nothing */ -#define EEPROM_PCI_MGD_MLD 0x0005 /* PCI MinGrant / MaxLatency. Desired */ -#define EEPROM_SSVENDID 0x0006 /* Subsystem Vendor Id */ -#define EEPROM_SSID 0x0006 /* Subsystem Id */ - -/* - * Structures definition and Functions prototypes - */ - -/* EPIC's hardware descriptors, must be aligned on dword in memory */ -/* NB: to make driver happy, this two structures MUST have thier sizes */ -/* be divisor of PAGE_SIZE */ -struct epic_tx_desc { - volatile u_int16_t status; - volatile u_int16_t txlength; - volatile u_int32_t bufaddr; - volatile u_int16_t buflength; - volatile u_int16_t control; - volatile u_int32_t next; -}; -struct epic_rx_desc { - volatile u_int16_t status; - volatile u_int16_t rxlength; - volatile u_int32_t bufaddr; - volatile u_int32_t buflength; - volatile u_int32_t next; -}; - -/* This structure defines EPIC's fragment list, maximum number of frags */ -/* is 63. Let use maximum, becouse size of struct MUST be divisor of */ -/* PAGE_SIZE, and sometimes come mbufs with more then 30 frags */ -#define EPIC_MAX_FRAGS 63 -struct epic_frag_list { - volatile u_int32_t numfrags; - struct { - volatile u_int32_t fragaddr; - volatile u_int32_t fraglen; - } frag[EPIC_MAX_FRAGS]; - volatile u_int32_t pad; /* align on 256 bytes */ -}; - /* This is driver's structure to define EPIC descriptors */ struct epic_rx_buffer { struct mbuf * mbuf; /* mbuf receiving packet */ @@ -267,11 +59,6 @@ struct epic_tx_buffer { struct mbuf * mbuf; /* mbuf contained packet */ }; -/* - * NB: ALIGN OF ABOVE STRUCTURES - * epic_rx_desc, epic_tx_desc, epic_frag_list - must be aligned on dword - */ - /* PHY, known by tx driver */ #define EPIC_UNKN_PHY 0x0000 #define EPIC_QS6612_PHY 0x0001 @@ -279,19 +66,6 @@ struct epic_tx_buffer { #define EPIC_LXT970_PHY 0x0003 #define EPIC_SERIAL 0x0004 -#define SMC9432DMT 0xA010 -#define SMC9432TX 0xA011 -#define SMC9032TXM 0xA012 -#define SMC9032TX 0xA013 -#define SMC9432TXPWR 0xA014 -#define SMC9432BTX 0xA015 -#define SMC9432FTX 0xA016 -#define SMC9432FTX_SC 0xA017 -#define SMC9432TX_XG_ADHOC 0xA020 -#define SMC9434TX_XG_ADHOC 0xA021 -#define SMC9432FTX_ADHOC 0xA022 -#define SMC9432BTX1 0xA024 - /* Driver status structure */ typedef struct { struct arpcom arpcom; |