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| author | yongari <yongari@FreeBSD.org> | 2009-12-22 19:00:18 +0000 |
|---|---|---|
| committer | yongari <yongari@FreeBSD.org> | 2009-12-22 19:00:18 +0000 |
| commit | 69eb1537ebfe9e513651b7095899759cee1b96aa (patch) | |
| tree | dbe256fac9215a25bcfe517ee0deb1daf1eebbfe /sys/dev/ste/if_ste.c | |
| parent | a9158a088f06d0cb2559e534b4a69eb52ef67a16 (diff) | |
| download | FreeBSD-src-69eb1537ebfe9e513651b7095899759cee1b96aa.zip FreeBSD-src-69eb1537ebfe9e513651b7095899759cee1b96aa.tar.gz | |
Add minimal dealy while ste(4) is waiting for the end of active DMA
cycle.
Diffstat (limited to 'sys/dev/ste/if_ste.c')
| -rw-r--r-- | sys/dev/ste/if_ste.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sys/dev/ste/if_ste.c b/sys/dev/ste/if_ste.c index 0fb8929..a6dce65 100644 --- a/sys/dev/ste/if_ste.c +++ b/sys/dev/ste/if_ste.c @@ -471,6 +471,7 @@ ste_wait(struct ste_softc *sc) for (i = 0; i < STE_TIMEOUT; i++) { if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) break; + DELAY(1); } if (i == STE_TIMEOUT) |
