- Introduce the bridge drivers for Sound Blaser, GUS and Crystal

  Semiconductor CS461x/428x.
- Add support for GUS and CS461x/428x pcm.

Bridges reviewed by:			dfr, cg
GUS non-PnP support submitted by:	Ville-Pertti Keinonen <will@iki.fi>
GUS PnP support tested by:		Michiru Saito <mich@mtci.ne.jp>

5 files changed, 7152 insertions, 0 deletions

diff --git a/sys/dev/sound/pci/csa.c b/sys/dev/sound/pci/csa.c
new file mode 100644
index 0000000..e8f7677
--- /dev/null
+++ b/sys/dev/sound/pci/csa.c
@@ -0,0 +1,789 @@
+/*-
+ * Copyright (c) 1999 Seigo Tanimura
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include "csa.h"
+#include "pci.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <machine/resource.h>
+#include <machine/bus.h>
+#include <machine/clock.h>
+#include <sys/rman.h>
+#include <sys/soundcard.h>
+#include <dev/sound/chip.h>
+#include <dev/sound/pci/csareg.h>
+#include <dev/sound/pci/csavar.h>
+
+#if NPCI > 0
+#include <pci/pcireg.h>
+#include <pci/pcivar.h>
+#endif /* NPCI > 0 */
+
+#if NCSA > 0
+
+#include <dev/sound/pci/csaimg.h>
+
+/* Here is the parameter structure per a device. */
+struct csa_softc {
+	device_t dev; /* device */
+	csa_res res; /* resources */
+
+	device_t pcm; /* pcm device */
+	driver_intr_t* pcmintr; /* pcm intr */
+	void *pcmintr_arg; /* pcm intr arg */
+	device_t midi; /* midi device */
+	driver_intr_t* midiintr; /* midi intr */
+	void *midiintr_arg; /* midi intr arg */
+	void *ih; /* cookie */
+};
+
+typedef struct csa_softc *sc_p;
+
+#if NPCI > 0
+static int csa_probe(device_t dev);
+static int csa_attach(device_t dev);
+#endif /* NPCI > 0 */
+static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
+					      u_long start, u_long end, u_long count, u_int flags);
+static int csa_release_resource(device_t bus, device_t child, int type, int rid,
+				   struct resource *r);
+static int csa_initialize(sc_p scp);
+static void csa_clearserialfifos(csa_res *resp);
+static void csa_resetdsp(csa_res *resp);
+static int csa_downloadimage(csa_res *resp);
+static int csa_transferimage(csa_res *resp, u_long *src, u_long dest, u_long len);
+
+static devclass_t csa_devclass;
+
+#if NPCI > 0
+static int
+csa_probe(device_t dev)
+{
+	char *s;
+	struct sndcard_func *func;
+
+	s = NULL;
+	switch (pci_get_devid(dev)) {
+	case CS4610_PCI_ID:
+		s = "Crystal Semiconductor CS4610/4611 Audio accelerator";
+		break;
+	case CS4614_PCI_ID:
+		s = "Crystal Semiconductor CS4614/4622/4624 Audio accelerator/4280 Audio controller";
+		break;
+	case CS4615_PCI_ID:
+		s = "Crystal Semiconductor CS4615 Audio accelerator";
+		break;
+	case CS4281_PCI_ID:
+		s = "Crystal Semiconductor CS4281 Audio controller";
+		break;
+	}
+
+	if (s != NULL) {
+		device_set_desc(dev, s);
+
+		/* PCM Audio */
+		func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT);
+		if (func == NULL)
+			return (ENOMEM);
+		bzero(func, sizeof(*func));
+		func->func = SCF_PCM;
+		device_add_child(dev, "pcm", -1, func);
+
+		/* Midi Interface */
+		func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT);
+		if (func == NULL)
+			return (ENOMEM);
+		bzero(func, sizeof(*func));
+		func->func = SCF_MIDI;
+		device_add_child(dev, "midi", -1, func);
+
+		return (0);
+	}
+
+	return (ENXIO);
+}
+
+static int
+csa_attach(device_t dev)
+{
+	u_int32_t stcmd;
+	sc_p scp;
+	csa_res *resp;
+
+	scp = device_get_softc(dev);
+
+	/* Fill in the softc. */
+	bzero(scp, sizeof(*scp));
+	scp->dev = dev;
+
+	/* Wake up the device. */
+	stcmd = pci_read_config(dev, PCIR_COMMAND, 4);
+	if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) {
+		stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
+		pci_write_config(dev, PCIR_COMMAND, 4, stcmd);
+	}
+	stcmd = pci_read_config(dev, PCIR_LATTIMER, 4);
+	if (stcmd < 32)
+		stcmd = 32;
+	pci_write_config(dev, PCIR_LATTIMER, 4, stcmd);
+
+	/* Allocate the resources. */
+	resp = &scp->res;
+	resp->io_rid = CS461x_IO_OFFSET;
+	resp->io = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->io_rid, 0, ~0, CS461x_IO_SIZE, RF_ACTIVE);
+	if (resp->io == NULL)
+		return (ENXIO);
+	resp->mem_rid = CS461x_MEM_OFFSET;
+	resp->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->mem_rid, 0, ~0, CS461x_MEM_SIZE, RF_ACTIVE);
+	if (resp->mem == NULL) {
+		bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
+		return (ENXIO);
+	}
+	resp->irq_rid = 0;
+	resp->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &resp->irq_rid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
+	if (resp->irq == NULL) {
+		bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
+		bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
+		return (ENXIO);
+	}
+
+	/* Initialize the chip. */
+	if (csa_initialize(scp)) {
+		bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
+		bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
+		bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
+		return (ENXIO);
+	}
+
+	/* Reset the Processor. */
+	csa_resetdsp(resp);
+
+	/* Download the Processor Image to the processor. */
+	if (csa_downloadimage(resp)) {
+		bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
+		bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
+		bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
+		return (ENXIO);
+	}
+
+	bus_generic_attach(dev);
+
+	return (0);
+}
+#endif /* NPCI > 0 */
+
+static struct resource *
+csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
+		      u_long start, u_long end, u_long count, u_int flags)
+{
+	sc_p scp;
+	csa_res *resp;
+	struct resource *res;
+
+	scp = device_get_softc(bus);
+	resp = &scp->res;
+	switch (type) {
+	case SYS_RES_IRQ:
+		if (*rid != 0)
+			return (NULL);
+		res = resp->irq;
+		break;
+	case SYS_RES_MEMORY:
+		switch (*rid) {
+		case CS461x_IO_OFFSET:
+			res = resp->io;
+			break;
+		case CS461x_MEM_OFFSET:
+			res = resp->mem;
+			break;
+		default:
+			return (NULL);
+		}
+		break;
+	default:
+		return (NULL);
+	}
+
+	return res;
+}
+
+static int
+csa_release_resource(device_t bus, device_t child, int type, int rid,
+			struct resource *r)
+{
+	return (0);
+}
+
+static int
+csa_initialize(sc_p scp)
+{
+	int i;
+	u_int32_t acsts, acisv;
+	csa_res *resp;
+
+	resp = &scp->res;
+
+	/*
+	 * First, blast the clock control register to zero so that the PLL starts
+	 * out in a known state, and blast the master serial port control register
+	 * to zero so that the serial ports also start out in a known state.
+	 */
+	csa_writeio(resp, BA0_CLKCR1, 0);
+	csa_writeio(resp, BA0_SERMC1, 0);
+
+	/*
+	 * If we are in AC97 mode, then we must set the part to a host controlled
+	 * AC-link.  Otherwise, we won't be able to bring up the link.
+	 */
+#if 1
+	csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */
+#else
+	csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */
+#endif /* 1 */
+
+	/*
+	 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
+	 * spec) and then drive it high.  This is done for non AC97 modes since
+	 * there might be logic external to the CS461x that uses the ARST# line
+	 * for a reset.
+	 */
+	csa_writeio(resp, BA0_ACCTL, 0);
+	DELAY(250);
+	csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN);
+
+	/*
+	 * The first thing we do here is to enable sync generation.  As soon
+	 * as we start receiving bit clock, we'll start producing the SYNC
+	 * signal.
+	 */
+	csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
+
+	/*
+	 * Now wait for a short while to allow the AC97 part to start
+	 * generating bit clock (so we don't try to start the PLL without an
+	 * input clock).
+	 */
+	DELAY(50000);
+
+	/*
+	 * Set the serial port timing configuration, so that
+	 * the clock control circuit gets its clock from the correct place.
+	 */
+	csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97);
+
+	/*
+	 * Write the selected clock control setup to the hardware.  Do not turn on
+	 * SWCE yet (if requested), so that the devices clocked by the output of
+	 * PLL are not clocked until the PLL is stable.
+	 */
+	csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
+	csa_writeio(resp, BA0_PLLM, 0x3a);
+	csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8);
+
+	/*
+	 * Power up the PLL.
+	 */
+	csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP);
+
+	/*
+	 * Wait until the PLL has stabilized.
+	 */
+	DELAY(50000);
+
+	/*
+	 * Turn on clocking of the core so that we can setup the serial ports.
+	 */
+	csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE);
+
+	/*
+	 * Fill the serial port FIFOs with silence.
+	 */
+	csa_clearserialfifos(resp);
+
+	/*
+	 * Set the serial port FIFO pointer to the first sample in the FIFO.
+	 */
+#if notdef
+	csa_writeio(resp, BA0_SERBSP, 0);
+#endif /* notdef */
+
+	/*
+	 *  Write the serial port configuration to the part.  The master
+	 *  enable bit is not set until all other values have been written.
+	 */
+	csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
+	csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
+	csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
+
+	/*
+	 * Wait for the codec ready signal from the AC97 codec.
+	 */
+	acsts = 0;
+	for (i = 0 ; i < 1000 ; i++) {
+		/*
+		 * First, lets wait a short while to let things settle out a bit,
+		 * and to prevent retrying the read too quickly.
+		 */
+		DELAY(250);
+
+		/*
+		 * Read the AC97 status register to see if we've seen a CODEC READY
+		 * signal from the AC97 codec.
+		 */
+		acsts = csa_readio(resp, BA0_ACSTS);
+		if ((acsts & ACSTS_CRDY) != 0)
+			break;
+	}
+
+	/*
+	 * Make sure we sampled CODEC READY.
+	 */
+	if ((acsts & ACSTS_CRDY) == 0)
+		return (ENXIO);
+
+	/*
+	 * Assert the vaid frame signal so that we can start sending commands
+	 * to the AC97 codec.
+	 */
+	csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
+
+	/*
+	 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
+	 * the codec is pumping ADC data across the AC-link.
+	 */
+	acisv = 0;
+	for (i = 0 ; i < 1000 ; i++) {
+		/*
+		 * First, lets wait a short while to let things settle out a bit,
+		 * and to prevent retrying the read too quickly.
+		 */
+#if notdef
+		DELAY(10000000L); /* clw */
+#else
+		DELAY(2500);
+#endif /* notdef */
+		/*
+		 * Read the input slot valid register and see if input slots 3 and
+		 * 4 are valid yet.
+		 */
+		acisv = csa_readio(resp, BA0_ACISV);
+		if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
+			break;
+	}
+	/*
+	 * Make sure we sampled valid input slots 3 and 4.  If not, then return
+	 * an error.
+	 */
+	if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4))
+		return (ENXIO);
+
+	/*
+	 * Now, assert valid frame and the slot 3 and 4 valid bits.  This will
+	 * commense the transfer of digital audio data to the AC97 codec.
+	 */
+	csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
+
+	/*
+	 * Power down the DAC and ADC.  We will power them up (if) when we need
+	 * them.
+	 */
+#if notdef
+	csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300);
+#endif /* notdef */
+
+	/*
+	 * Turn off the Processor by turning off the software clock enable flag in 
+	 * the clock control register.
+	 */
+#if notdef
+	clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE;
+	csa_writeio(resp, BA0_CLKCR1, clkcr1);
+#endif /* notdef */
+
+	/*
+	 * Enable interrupts on the part.
+	 */
+#if notdef
+	csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
+#endif /* notdef */
+
+	return (0);
+}
+
+static void
+csa_clearserialfifos(csa_res *resp)
+{
+	int i, j, pwr;
+	u_int8_t clkcr1, serbst;
+
+	/*
+	 * See if the devices are powered down.  If so, we must power them up first
+	 * or they will not respond.
+	 */
+	pwr = 1;
+	clkcr1 = csa_readio(resp, BA0_CLKCR1);
+	if ((clkcr1 & CLKCR1_SWCE) == 0) {
+		csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE);
+		pwr = 0;
+	}
+
+	/*
+	 * We want to clear out the serial port FIFOs so we don't end up playing
+	 * whatever random garbage happens to be in them.  We fill the sample FIFOs
+	 * with zero (silence).
+	 */
+	csa_writeio(resp, BA0_SERBWP, 0);
+
+	/* Fill all 256 sample FIFO locations. */
+	serbst = 0;
+	for (i = 0 ; i < 256 ; i++) {
+		/* Make sure the previous FIFO write operation has completed. */
+		for (j = 0 ; j < 5 ; j++) {
+			DELAY(250);
+			serbst = csa_readio(resp, BA0_SERBST);
+			if ((serbst & SERBST_WBSY) == 0)
+				break;
+		}
+		if ((serbst & SERBST_WBSY) != 0) {
+			if (!pwr)
+				csa_writeio(resp, BA0_CLKCR1, clkcr1);
+		}
+		/* Write the serial port FIFO index. */
+		csa_writeio(resp, BA0_SERBAD, i);
+		/* Tell the serial port to load the new value into the FIFO location. */
+		csa_writeio(resp, BA0_SERBCM, SERBCM_WRC);
+	}
+	/*
+	 *  Now, if we powered up the devices, then power them back down again.
+	 *  This is kinda ugly, but should never happen.
+	 */
+	if (!pwr)
+		csa_writeio(resp, BA0_CLKCR1, clkcr1);
+}
+
+static void
+csa_resetdsp(csa_res *resp)
+{
+	int i;
+
+	/*
+	 * Write the reset bit of the SP control register.
+	 */
+	csa_writemem(resp, BA1_SPCR, SPCR_RSTSP);
+
+	/*
+	 * Write the control register.
+	 */
+	csa_writemem(resp, BA1_SPCR, SPCR_DRQEN);
+
+	/*
+	 * Clear the trap registers.
+	 */
+	for (i = 0 ; i < 8 ; i++) {
+		csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i);
+		csa_writemem(resp, BA1_TWPR, 0xffff);
+	}
+	csa_writemem(resp, BA1_DREG, 0);
+
+	/*
+	 * Set the frame timer to reflect the number of cycles per frame.
+	 */
+	csa_writemem(resp, BA1_FRMT, 0xadf);
+}
+
+static int
+csa_downloadimage(csa_res *resp)
+{
+	int ret;
+	u_long ul, offset;
+
+	for (ul = 0, offset = 0 ; ul < INKY_MEMORY_COUNT ; ul++) {
+		/*
+		 * DMA this block from host memory to the appropriate
+		 * memory on the CSDevice.
+		 */
+		ret = csa_transferimage(
+			resp,
+			BA1Struct.BA1Array + offset,
+			BA1Struct.MemoryStat[ul].ulDestByteOffset,
+			BA1Struct.MemoryStat[ul].ulSourceByteSize);
+		if (ret)
+			return (ret);
+		offset += BA1Struct.MemoryStat[ul].ulSourceByteSize >> 2;
+	}
+
+	return (0);
+}
+
+static int
+csa_transferimage(csa_res *resp, u_long *src, u_long dest, u_long len)
+{
+	u_long ul;
+
+	/*
+	 * We do not allow DMAs from host memory to host memory (although the DMA
+	 * can do it) and we do not allow DMAs which are not a multiple of 4 bytes
+	 * in size (because that DMA can not do that).  Return an error if either
+	 * of these conditions exist.
+	 */
+	if ((len & 0x3) != 0)
+		return (EINVAL);
+
+	/* Check the destination address that it is a multiple of 4 */
+	if ((dest & 0x3) != 0)
+		return (EINVAL);
+
+	/* Write the buffer out. */
+	for (ul = 0 ; ul < len ; ul += 4)
+		csa_writemem(resp, dest + ul, src[ul >> 2]);
+
+	return (0);
+}
+
+int
+csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data)
+{
+	int i;
+	u_int32_t acsda, acctl, acsts;
+
+	/*
+	 * Make sure that there is not data sitting around from a previous
+	 * uncompleted access. ACSDA = Status Data Register = 47Ch
+	 */
+	acsda = csa_readio(resp, BA0_ACSDA);
+
+	/*
+	 * Setup the AC97 control registers on the CS461x to send the
+	 * appropriate command to the AC97 to perform the read.
+	 * ACCAD = Command Address Register = 46Ch
+	 * ACCDA = Command Data Register = 470h
+	 * ACCTL = Control Register = 460h
+	 * set DCV - will clear when process completed
+	 * set CRW - Read command
+	 * set VFRM - valid frame enabled
+	 * set ESYN - ASYNC generation enabled
+	 * set RSTN - ARST# inactive, AC97 codec not reset
+	 */
+
+	/*
+	 * Get the actual AC97 register from the offset
+	 */
+	csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
+	csa_writeio(resp, BA0_ACCDA, 0);
+	csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
+
+	/*
+	 * Wait for the read to occur.
+	 */
+	acctl = 0;
+	for (i = 0 ; i < 10 ; i++) {
+		/*
+		 * First, we want to wait for a short time.
+		 */
+		DELAY(25);
+
+		/*
+		 * Now, check to see if the read has completed.
+		 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
+		 */
+		acctl = csa_readio(resp, BA0_ACCTL);
+		if ((acctl & ACCTL_DCV) == 0)
+			break;
+	}
+
+	/*
+	 * Make sure the read completed.
+	 */
+	if ((acctl & ACCTL_DCV) != 0)
+		return (EAGAIN);
+
+	/*
+	 * Wait for the valid status bit to go active.
+	 */
+	acsts = 0;
+	for (i = 0 ; i < 10 ; i++) {
+		/*
+		 * Read the AC97 status register.
+		 * ACSTS = Status Register = 464h
+		 */
+		acsts = csa_readio(resp, BA0_ACSTS);
+		/*
+		 * See if we have valid status.
+		 * VSTS - Valid Status
+		 */
+		if ((acsts & ACSTS_VSTS) != 0)
+			break;
+		/*
+		 * Wait for a short while.
+		 */
+		 DELAY(25);
+	}
+
+	/*
+	 * Make sure we got valid status.
+	 */
+	if ((acsts & ACSTS_VSTS) == 0)
+		return (EAGAIN);
+
+	/*
+	 * Read the data returned from the AC97 register.
+	 * ACSDA = Status Data Register = 474h 
+	 */
+	*data = csa_readio(resp, BA0_ACSDA); 
+
+	return (0);
+}
+
+int
+csa_writecodec(csa_res *resp, u_long offset, u_int32_t data)
+{
+	int i;
+	u_int32_t acctl;
+
+	/*
+	 * Setup the AC97 control registers on the CS461x to send the
+	 * appropriate command to the AC97 to perform the write.
+	 * ACCAD = Command Address Register = 46Ch
+	 * ACCDA = Command Data Register = 470h
+	 * ACCTL = Control Register = 460h
+	 * set DCV - will clear when process completed
+	 * set VFRM - valid frame enabled
+	 * set ESYN - ASYNC generation enabled
+	 * set RSTN - ARST# inactive, AC97 codec not reset
+	 */
+
+	/*
+	 * Get the actual AC97 register from the offset
+	 */
+	csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
+	csa_writeio(resp, BA0_ACCDA, data);
+	csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
+
+	/*
+	 * Wait for the write to occur.
+	 */
+	acctl = 0;
+	for (i = 0 ; i < 10 ; i++) {
+		/*
+		 * First, we want to wait for a short time.
+		 */
+		DELAY(25);
+
+		/*
+		 * Now, check to see if the read has completed.
+		 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
+		 */
+		acctl = csa_readio(resp, BA0_ACCTL);
+		if ((acctl & ACCTL_DCV) == 0)
+			break;
+	}
+
+	/*
+	 * Make sure the write completed.
+	 */
+	if ((acctl & ACCTL_DCV) != 0)
+		return (EAGAIN);
+
+	return (0);
+}
+
+u_int32_t
+csa_readio(csa_res *resp, u_long offset)
+{
+	u_int32_t ul;
+
+	if (offset < BA0_AC97_RESET)
+		return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff;
+	else {
+		if (csa_readcodec(resp, offset, &ul))
+			ul = 0;
+		return (ul);
+	}
+}
+
+void
+csa_writeio(csa_res *resp, u_long offset, u_int32_t data)
+{
+	if (offset < BA0_AC97_RESET)
+		bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data);
+	else
+		csa_writecodec(resp, offset, data);
+}
+
+u_int32_t
+csa_readmem(csa_res *resp, u_long offset)
+{
+	return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset) & 0xffffffff;
+}
+
+void
+csa_writemem(csa_res *resp, u_long offset, u_int32_t data)
+{
+	bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data);
+}
+
+#if NPCI > 0
+static device_method_t csa_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		csa_probe),
+	DEVMETHOD(device_attach,	csa_attach),
+	DEVMETHOD(device_detach,	bus_generic_detach),
+	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
+	DEVMETHOD(device_suspend,	bus_generic_suspend),
+	DEVMETHOD(device_resume,	bus_generic_resume),
+
+	/* Bus interface */
+	DEVMETHOD(bus_print_child,	bus_generic_print_child),
+	DEVMETHOD(bus_alloc_resource,	csa_alloc_resource),
+	DEVMETHOD(bus_release_resource,	csa_release_resource),
+	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
+	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
+	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
+	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
+
+	{ 0, 0 }
+};
+
+static driver_t csa_driver = {
+	"csa",
+	csa_methods,
+	sizeof(struct csa_softc),
+};
+
+/*
+ * csa can be attached to a pci bus.
+ */
+DRIVER_MODULE(csa, pci, csa_driver, csa_devclass, 0, 0);
+#endif /* NPCI > 0 */
+
+#endif /* NCSA > 0 */
diff --git a/sys/dev/sound/pci/csaimg.h b/sys/dev/sound/pci/csaimg.h
new file mode 100644
index 0000000..994c8bc
--- /dev/null
+++ b/sys/dev/sound/pci/csaimg.h
@@ -0,0 +1,3493 @@
+/*-
+ * Copyright (c) 1999 Seigo Tanimura
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _CSA_IMG_H
+#define _CSA_IMG_H
+
+/* The following array is written during initialization. */
+static struct BA1struct BA1Struct = {
+{{ 0x00000000, 0x00003000 },{ 0x00010000, 0x00003800 },{ 0x00020000, 0x00007000 }},
+{0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000163,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00200040,0x00008010,0x00000000,
+0x00000000,0x80000001,0x00000001,0x00060000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00900080,0x00000173,0x00000000,
+0x00000000,0x00000010,0x00800000,0x00900000,
+0xf2c0000f,0x00000200,0x00000000,0x00010600,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000163,0x330300c2,
+0x06000000,0x00000000,0x80008000,0x80008000,
+0x3fc0000f,0x00000301,0x00010400,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00b00000,0x00d0806d,0x330480c3,
+0x04800000,0x00000001,0x00800001,0x0000ffff,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x066a0600,0x06350070,0x0000929d,0x929d929d,
+0x00000000,0x0000735a,0x00000600,0x00000000,
+0x929d735a,0x8734abfe,0x00010000,0x735a735a,
+0xa431ac75,0xa431ac75,0xa431ac75,0xa431ac75,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x0000804f,0x000000c3,
+0x05000000,0x00a00010,0x00000000,0x80008000,
+0x00000000,0x00000000,0x00000700,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000080,0x00a00000,0x0000809a,0x000000c2,
+0x07400000,0x00000000,0x80008000,0xffffffff,
+0x00c80028,0x00005555,0x00000000,0x000107a0,
+0x00c80028,0x000000c2,0x06800000,0x00000000,
+0x06e00080,0x00300000,0x000080bb,0x000000c9,
+0x07a00000,0x04000000,0x80008000,0xffffffff,
+0x00c80028,0x00005555,0x00000000,0x00000780,
+0x00c80028,0x000000c5,0xff800000,0x00000000,
+0x00640080,0x00c00000,0x00008197,0x000000c9,
+0x07800000,0x04000000,0x80008000,0xffffffff,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x0000805e,0x000000c1,
+0x00000000,0x00800000,0x80008000,0x80008000,
+0x00020000,0x0000ffff,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
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+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000}
+ };
+
+#endif /* _CSA_IMG_H */
diff --git a/sys/dev/sound/pci/csapcm.c b/sys/dev/sound/pci/csapcm.c
new file mode 100644
index 0000000..964011d
--- /dev/null
+++ b/sys/dev/sound/pci/csapcm.c
@@ -0,0 +1,851 @@
+/*-
+ * Copyright (c) 1999 Seigo Tanimura
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include "opt_devfs.h"
+#include "pci.h"
+#include "csa.h"
+#include "pcm.h"
+
+#include <sys/soundcard.h>
+#include <dev/sound/pcm/sound.h>
+#include <dev/sound/pcm/ac97.h>
+#include <dev/sound/chip.h>
+#include <dev/sound/pci/csareg.h>
+#include <dev/sound/pci/csavar.h>
+
+#include <pci/pcireg.h>
+#include <pci/pcivar.h>
+
+#if NCSA > 0
+
+/* device private data */
+struct csa_info;
+
+struct csa_chinfo {
+	struct csa_info *parent;
+	pcm_channel *channel;
+	snd_dbuf *buffer;
+	int dir;
+	u_int32_t fmt;
+};
+
+struct csa_info {
+	csa_res		res; /* resource */
+	void		*ih; /* Interrupt cookie */
+	bus_dma_tag_t	parent_dmat; /* DMA tag */
+
+	/* Contents of board's registers */
+	u_long		pfie;
+	u_long		pctl;
+	u_long		cctl;
+	struct csa_chinfo pch, rch;
+};
+
+/* -------------------------------------------------------------------- */
+
+/* prototypes */
+static int      csa_init(struct csa_info *);
+static void     csa_intr(void *);
+static void	csa_setplaysamplerate(csa_res *resp, u_long ulInRate);
+static void	csa_setcapturesamplerate(csa_res *resp, u_long ulOutRate);
+static void	csa_startplaydma(struct csa_info *csa);
+static void	csa_startcapturedma(struct csa_info *csa);
+static void	csa_stopplaydma(struct csa_info *csa);
+static void	csa_stopcapturedma(struct csa_info *csa);
+static void	csa_powerupadc(csa_res *resp);
+static void	csa_powerupdac(csa_res *resp);
+static int	csa_startdsp(csa_res *resp);
+static int	csa_allocres(struct csa_info *scp, device_t dev);
+static void	csa_releaseres(struct csa_info *scp, device_t dev);
+
+/* talk to the codec - called from ac97.c */
+static u_int32_t csa_rdcd(void *, int);
+static void  	 csa_wrcd(void *, int, u_int32_t);
+
+/* channel interface */
+static void *csachan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir);
+static int csachan_setdir(void *data, int dir);
+static int csachan_setformat(void *data, u_int32_t format);
+static int csachan_setspeed(void *data, u_int32_t speed);
+static int csachan_setblocksize(void *data, u_int32_t blocksize);
+static int csachan_trigger(void *data, int go);
+static int csachan_getptr(void *data);
+static pcmchan_caps *csachan_getcaps(void *data);
+
+static pcmchan_caps csa_playcaps = {
+	8000, 48000,
+	AFMT_STEREO | AFMT_U8 | AFMT_S8 | AFMT_S16_LE | AFMT_S16_BE,
+	AFMT_STEREO | AFMT_S16_LE
+};
+
+static pcmchan_caps csa_reccaps = {
+	11025, 48000,
+	AFMT_STEREO | AFMT_S16_LE,
+	AFMT_STEREO | AFMT_S16_LE
+};
+
+static pcm_channel csa_chantemplate = {
+	csachan_init,
+	csachan_setdir,
+	csachan_setformat,
+	csachan_setspeed,
+	csachan_setblocksize,
+	csachan_trigger,
+	csachan_getptr,
+	csachan_getcaps,
+};
+
+/* -------------------------------------------------------------------- */
+
+/* channel interface */
+static void *
+csachan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir)
+{
+	struct csa_info *csa = devinfo;
+	struct csa_chinfo *ch = (dir == PCMDIR_PLAY)? &csa->pch : &csa->rch;
+
+	ch->parent = csa;
+	ch->channel = c;
+	ch->buffer = b;
+	ch->buffer->bufsize = CS461x_BUFFSIZE;
+	if (chn_allocbuf(ch->buffer, csa->parent_dmat) == -1) return NULL;
+	return ch;
+}
+
+static int
+csachan_setdir(void *data, int dir)
+{
+	struct csa_chinfo *ch = data;
+	struct csa_info *csa = ch->parent;
+	csa_res *resp;
+
+	resp = &csa->res;
+
+	if (dir == PCMDIR_PLAY)
+		csa_writemem(resp, BA1_PBA, vtophys(ch->buffer->buf));
+	else
+		csa_writemem(resp, BA1_CBA, vtophys(ch->buffer->buf));
+	ch->dir = dir;
+	return 0;
+}
+
+static int
+csachan_setformat(void *data, u_int32_t format)
+{
+	struct csa_chinfo *ch = data;
+	struct csa_info *csa = ch->parent;
+	u_long pdtc;
+	csa_res *resp;
+
+	resp = &csa->res;
+
+	if (ch->dir == PCMDIR_REC)
+		csa_writemem(resp, BA1_CIE, (csa_readmem(resp, BA1_CIE) & ~0x0000003f) | 0x00000001);
+	else {
+		csa->pfie = csa_readmem(resp, BA1_PFIE) & ~0x0000f03f;
+		if (format & AFMT_U8 || format & AFMT_U16_LE || format & AFMT_U16_BE)
+			csa->pfie |= 0x8000;
+		if (format & AFMT_S16_BE || format & AFMT_U16_BE)
+			csa->pfie |= 0x4000;
+		if (!(format & AFMT_STEREO))
+			csa->pfie |= 0x2000;
+		if (format & AFMT_U8 || format & AFMT_S8)
+			csa->pfie |= 0x1000;
+		csa_writemem(resp, BA1_PFIE, csa->pfie);
+		pdtc = csa_readmem(resp, BA1_PDTC) & ~0x000003ff;
+		if ((format & AFMT_S16_BE || format & AFMT_U16_BE || format & AFMT_S16_LE || format & AFMT_U16_LE) && (format & AFMT_STEREO))
+			pdtc |= 0x00f;
+		else if ((format & AFMT_S16_BE || format & AFMT_U16_BE || format & AFMT_S16_LE || format & AFMT_U16_LE) || (format & AFMT_STEREO))
+			pdtc |= 0x007;
+		else
+			pdtc |= 0x003;
+		csa_writemem(resp, BA1_PDTC, pdtc);
+	}
+	ch->fmt = format;
+	return 0;
+}
+
+static int
+csachan_setspeed(void *data, u_int32_t speed)
+{
+	struct csa_chinfo *ch = data;
+	struct csa_info *csa = ch->parent;
+	csa_res *resp;
+
+	resp = &csa->res;
+
+	if (ch->dir == PCMDIR_PLAY)
+		csa_setplaysamplerate(resp, speed);
+	else if (ch->dir == PCMDIR_REC)
+		csa_setcapturesamplerate(resp, speed);
+
+	/* rec/play speeds locked together - should indicate in flags */
+#if 0
+	if (ch->direction == PCMDIR_PLAY) d->rec[0].speed = speed;
+	else d->play[0].speed = speed;
+#endif
+	return speed; /* XXX calc real speed */
+}
+
+static void
+csa_setplaysamplerate(csa_res *resp, u_long ulInRate)
+{
+	u_long ulTemp1, ulTemp2;
+	u_long ulPhiIncr;
+	u_long ulCorrectionPerGOF, ulCorrectionPerSec;
+	u_long ulOutRate;
+
+	ulOutRate = 48000;
+
+	/*
+	 * Compute the values used to drive the actual sample rate conversion.
+	 * The following formulas are being computed, using inline assembly
+	 * since we need to use 64 bit arithmetic to compute the values:
+	 *
+	 *     ulPhiIncr = floor((Fs,in * 2^26) / Fs,out)
+	 *     ulCorrectionPerGOF = floor((Fs,in * 2^26 - Fs,out * ulPhiIncr) /
+	 *                                GOF_PER_SEC)
+	 *     ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
+	 *                          GOF_PER_SEC * ulCorrectionPerGOF
+	 *
+	 * i.e.
+	 *
+	 *     ulPhiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
+	 *     ulCorrectionPerGOF:ulCorrectionPerSec =
+	 *         dividend:remainder(ulOther / GOF_PER_SEC)
+	 */
+	ulTemp1 = ulInRate << 16;
+	ulPhiIncr = ulTemp1 / ulOutRate;
+	ulTemp1 -= ulPhiIncr * ulOutRate;
+	ulTemp1 <<= 10;
+	ulPhiIncr <<= 10;
+	ulTemp2 = ulTemp1 / ulOutRate;
+	ulPhiIncr += ulTemp2;
+	ulTemp1 -= ulTemp2 * ulOutRate;
+	ulCorrectionPerGOF = ulTemp1 / GOF_PER_SEC;
+	ulTemp1 -= ulCorrectionPerGOF * GOF_PER_SEC;
+	ulCorrectionPerSec = ulTemp1;
+
+	/*
+	 * Fill in the SampleRateConverter control block.
+	 */
+	csa_writemem(resp, BA1_PSRC, ((ulCorrectionPerSec << 16) & 0xFFFF0000) | (ulCorrectionPerGOF & 0xFFFF));
+	csa_writemem(resp, BA1_PPI, ulPhiIncr);
+}
+
+static void
+csa_setcapturesamplerate(csa_res *resp, u_long ulOutRate)
+{
+	u_long ulPhiIncr, ulCoeffIncr, ulTemp1, ulTemp2;
+	u_long ulCorrectionPerGOF, ulCorrectionPerSec, ulInitialDelay;
+	u_long dwFrameGroupLength, dwCnt;
+	u_long ulInRate;
+
+	ulInRate = 48000;
+
+	/*
+	 * We can only decimate by up to a factor of 1/9th the hardware rate.
+	 * Return an error if an attempt is made to stray outside that limit.
+	 */
+	if((ulOutRate * 9) < ulInRate)
+		return;
+
+	/*
+	 * We can not capture at at rate greater than the Input Rate (48000).
+	 * Return an error if an attempt is made to stray outside that limit.
+	 */
+	if(ulOutRate > ulInRate)
+		return;
+
+	/*
+	 * Compute the values used to drive the actual sample rate conversion.
+	 * The following formulas are being computed, using inline assembly
+	 * since we need to use 64 bit arithmetic to compute the values:
+	 *
+	 *     ulCoeffIncr = -floor((Fs,out * 2^23) / Fs,in)
+	 *     ulPhiIncr = floor((Fs,in * 2^26) / Fs,out)
+	 *     ulCorrectionPerGOF = floor((Fs,in * 2^26 - Fs,out * ulPhiIncr) /
+	 *                                GOF_PER_SEC)
+	 *     ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
+	 *                          GOF_PER_SEC * ulCorrectionPerGOF
+	 *     ulInitialDelay = ceil((24 * Fs,in) / Fs,out)
+	 *
+	 * i.e.
+	 *
+	 *     ulCoeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
+	 *     ulPhiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
+	 *     ulCorrectionPerGOF:ulCorrectionPerSec =
+	 *         dividend:remainder(ulOther / GOF_PER_SEC)
+	 *     ulInitialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
+	 */
+	ulTemp1 = ulOutRate << 16;
+	ulCoeffIncr = ulTemp1 / ulInRate;
+	ulTemp1 -= ulCoeffIncr * ulInRate;
+	ulTemp1 <<= 7;
+	ulCoeffIncr <<= 7;
+	ulCoeffIncr += ulTemp1 / ulInRate;
+	ulCoeffIncr ^= 0xFFFFFFFF;
+	ulCoeffIncr++;
+	ulTemp1 = ulInRate << 16;
+	ulPhiIncr = ulTemp1 / ulOutRate;
+	ulTemp1 -= ulPhiIncr * ulOutRate;
+	ulTemp1 <<= 10;
+	ulPhiIncr <<= 10;
+	ulTemp2 = ulTemp1 / ulOutRate;
+	ulPhiIncr += ulTemp2;
+	ulTemp1 -= ulTemp2 * ulOutRate;
+	ulCorrectionPerGOF = ulTemp1 / GOF_PER_SEC;
+	ulTemp1 -= ulCorrectionPerGOF * GOF_PER_SEC;
+	ulCorrectionPerSec = ulTemp1;
+	ulInitialDelay = ((ulInRate * 24) + ulOutRate - 1) / ulOutRate;
+
+	/*
+	 * Fill in the VariDecimate control block.
+	 */
+	csa_writemem(resp, BA1_CSRC, 
+		     ((ulCorrectionPerSec << 16) & 0xFFFF0000) | (ulCorrectionPerGOF & 0xFFFF));
+	csa_writemem(resp, BA1_CCI, ulCoeffIncr);
+	csa_writemem(resp, BA1_CD, 
+	     (((BA1_VARIDEC_BUF_1 + (ulInitialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
+	csa_writemem(resp, BA1_CPI, ulPhiIncr);
+
+	/*
+	 * Figure out the frame group length for the write back task.  Basically,
+	 * this is just the factors of 24000 (2^6*3*5^3) that are not present in
+	 * the output sample rate.
+	 */
+	dwFrameGroupLength = 1;
+	for(dwCnt = 2; dwCnt <= 64; dwCnt *= 2)
+	{
+		if(((ulOutRate / dwCnt) * dwCnt) !=
+		   ulOutRate)
+		{
+			dwFrameGroupLength *= 2;
+		}
+	}
+	if(((ulOutRate / 3) * 3) !=
+	   ulOutRate)
+	{
+		dwFrameGroupLength *= 3;
+	}
+	for(dwCnt = 5; dwCnt <= 125; dwCnt *= 5)
+	{
+		if(((ulOutRate / dwCnt) * dwCnt) !=
+		   ulOutRate)
+		{
+			dwFrameGroupLength *= 5;
+		}
+	}
+
+	/*
+	 * Fill in the WriteBack control block.
+	 */
+	csa_writemem(resp, BA1_CFG1, dwFrameGroupLength);
+	csa_writemem(resp, BA1_CFG2, (0x00800000 | dwFrameGroupLength));
+	csa_writemem(resp, BA1_CCST, 0x0000FFFF);
+	csa_writemem(resp, BA1_CSPB, ((65536 * ulOutRate) / 24000));
+	csa_writemem(resp, (BA1_CSPB + 4), 0x0000FFFF);
+}
+
+static int
+csachan_setblocksize(void *data, u_int32_t blocksize)
+{
+#if notdef
+	return blocksize;
+#else
+	struct csa_chinfo *ch = data;
+	return ch->buffer->bufsize / 2;
+#endif /* notdef */
+}
+
+static int
+csachan_trigger(void *data, int go)
+{
+	struct csa_chinfo *ch = data;
+	struct csa_info *csa = ch->parent;
+
+	if (ch->dir == PCMDIR_PLAY) {
+		if (go == PCMTRIG_START)
+			csa_startplaydma(csa);
+		else
+			csa_stopplaydma(csa);
+	} else {
+		if (go == PCMTRIG_START)
+			csa_startcapturedma(csa);
+		else
+			csa_stopcapturedma(csa);
+	}
+	return 0;
+}
+
+static void
+csa_startplaydma(struct csa_info *csa)
+{
+	csa_res *resp;
+	u_long ul;
+
+	resp = &csa->res;
+	ul = csa_readmem(resp, BA1_PCTL);
+	ul &= 0x0000ffff;
+	csa_writemem(resp, BA1_PCTL, ul | csa->pctl);
+	csa_writemem(resp, BA1_PVOL, 0x80008000);
+}
+
+static void
+csa_startcapturedma(struct csa_info *csa)
+{
+	csa_res *resp;
+	u_long ul;
+
+	resp = &csa->res;
+	ul = csa_readmem(resp, BA1_CCTL);
+	ul &= 0xffff0000;
+	csa_writemem(resp, BA1_CCTL, ul | csa->cctl);
+	csa_writemem(resp, BA1_CVOL, 0x80008000);
+}
+
+static void
+csa_stopplaydma(struct csa_info *csa)
+{
+	csa_res *resp;
+	u_long ul;
+
+	resp = &csa->res;
+	ul = csa_readmem(resp, BA1_PCTL);
+	csa->pctl = ul & 0xffff0000;
+	csa_writemem(resp, BA1_PCTL, ul & 0x0000ffff);
+	csa_writemem(resp, BA1_PVOL, 0xffffffff);
+}
+
+static void
+csa_stopcapturedma(struct csa_info *csa)
+{
+	csa_res *resp;
+	u_long ul;
+
+	resp = &csa->res;
+	ul = csa_readmem(resp, BA1_CCTL);
+	csa->cctl = ul & 0x0000ffff;
+	csa_writemem(resp, BA1_CCTL, ul & 0xffff0000);
+	csa_writemem(resp, BA1_CVOL, 0xffffffff);
+}
+
+static void
+csa_powerupdac(csa_res *resp)
+{
+	int i;
+	u_long ul;
+
+	/*
+	 * Power on the DACs on the AC97 codec.  We turn off the DAC
+	 * powerdown bit and write the new value of the power control
+	 * register.
+	 */
+	ul = csa_readio(resp, BA0_AC97_POWERDOWN);
+	ul &= 0xfdff;
+	csa_writeio(resp, BA0_AC97_POWERDOWN, ul);
+
+	/*
+	 * Now, we wait until we sample a DAC ready state.
+	 */
+	for (i = 0 ; i < 32 ; i++) {
+		/*
+		 * First, lets wait a short while to let things settle out a
+		 * bit, and to prevent retrying the read too quickly.
+		 */
+		DELAY(125);
+
+		/*
+		 * Read the current state of the power control register.
+		 */
+		ul = csa_readio(resp, BA0_AC97_POWERDOWN);
+
+		/*
+		 * If the DAC ready state bit is set, then stop waiting.
+		 */
+		if ((ul & 0x2) != 0)
+			break;
+	}
+	/*
+	 * The DACs are now calibrated, so we can unmute the DAC output.
+	 */
+	csa_writeio(resp, BA0_AC97_PCM_OUT_VOLUME, 0x0808);
+}
+
+static void
+csa_powerupadc(csa_res *resp)
+{
+	int i;
+	u_long ul;
+
+	/*
+	 * Power on the ADCs on the AC97 codec.  We turn off the ADC
+	 * powerdown bit and write the new value of the power control
+	 * register.
+	 */
+	ul = csa_readio(resp, BA0_AC97_POWERDOWN);
+	ul &= 0xfeff;
+	csa_writeio(resp, BA0_AC97_POWERDOWN, ul);
+
+	/*
+	 * Now, we wait until we sample a ADC ready state.
+	 */
+	for (i = 0 ; i < 32 ; i++) {
+		/*
+		 * First, lets wait a short while to let things settle out a
+		 * bit, and to prevent retrying the read too quickly.
+		 */
+		DELAY(125);
+
+		/*
+		 * Read the current state of the power control register.
+		 */
+		ul = csa_readio(resp, BA0_AC97_POWERDOWN);
+
+		/*
+		 * If the ADC ready state bit is set, then stop waiting.
+		 */
+		if ((ul & 0x1) != 0)
+			break;
+	}
+}
+
+static int
+csa_startdsp(csa_res *resp)
+{
+	int i;
+	u_long ul;
+
+	/*
+	 * Set the frame timer to reflect the number of cycles per frame.
+	 */
+	csa_writemem(resp, BA1_FRMT, 0xadf);
+
+	/*
+	 * Turn on the run, run at frame, and DMA enable bits in the local copy of
+	 * the SP control register.
+	 */
+	csa_writemem(resp, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
+
+	/*
+	 * Wait until the run at frame bit resets itself in the SP control
+	 * register.
+	 */
+	ul = 0;
+	for (i = 0 ; i < 25 ; i++) {
+		/*
+		 * Wait a little bit, so we don't issue PCI reads too frequently.
+		 */
+#if notdef
+		DELAY(1000);
+#else
+		DELAY(125);
+#endif /* notdef */
+		/*
+		 * Fetch the current value of the SP status register.
+		 */
+		ul = csa_readmem(resp, BA1_SPCR);
+
+		/*
+		 * If the run at frame bit has reset, then stop waiting.
+		 */
+		if((ul & SPCR_RUNFR) == 0)
+			break;
+	}
+	/*
+	 * If the run at frame bit never reset, then return an error.
+	 */
+	if((ul & SPCR_RUNFR) != 0)
+		return (EAGAIN);
+
+	return (0);
+}
+
+static int
+csachan_getptr(void *data)
+{
+	struct csa_chinfo *ch = data;
+	struct csa_info *csa = ch->parent;
+	csa_res *resp;
+	int ptr;
+
+	resp = &csa->res;
+
+	if (ch->dir == PCMDIR_PLAY) {
+		ptr = csa_readmem(resp, BA1_PBA) - vtophys(ch->buffer->buf);
+		if ((ch->fmt & AFMT_U8) != 0 || (ch->fmt & AFMT_S8) != 0)
+			ptr >>= 1;
+	} else {
+		ptr = csa_readmem(resp, BA1_CBA) - vtophys(ch->buffer->buf);
+		if ((ch->fmt & AFMT_U8) != 0 || (ch->fmt & AFMT_S8) != 0)
+			ptr >>= 1;
+	}
+
+	return (ptr);
+}
+
+static pcmchan_caps *
+csachan_getcaps(void *data)
+{
+	struct csa_chinfo *ch = data;
+	return (ch->dir == PCMDIR_PLAY)? &csa_playcaps : &csa_reccaps;
+}
+
+/* The interrupt handler */
+static void
+csa_intr (void *p)
+{
+	struct csa_info *csa = p;
+	csa_res *resp;
+	u_int hisr;
+
+	resp = &csa->res;
+
+	/* Is this interrupt for us? */
+	/* XXX The parent device should handle this. */
+	hisr = csa_readio(resp, BA0_HISR);
+	if ((hisr & ~HISR_INTENA) == 0) {
+		/* Throw an eoi. */
+		csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
+		return;
+	}
+
+	if ((hisr & HISR_VC0) != 0)
+		chn_intr(csa->pch.channel);
+	if ((hisr & HISR_VC1) != 0)
+		chn_intr(csa->rch.channel);
+
+	/* Throw an eoi. */
+	csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
+}
+
+/* -------------------------------------------------------------------- */
+
+/*
+ * Probe and attach the card
+ */
+
+static int
+csa_init(struct csa_info *csa)
+{
+	csa_res *resp;
+
+	resp = &csa->res;
+
+	csa->pfie = 0;
+	csa_stopplaydma(csa);
+	csa_stopcapturedma(csa);
+
+	/* Crank up the power on the DAC and ADC. */
+	csa_powerupadc(resp);
+	csa_powerupdac(resp);
+
+	csa_setplaysamplerate(resp, 8000);
+	csa_setcapturesamplerate(resp, 8000);
+
+	if (csa_startdsp(resp))
+		return (1);
+
+	return 0;
+}
+
+/* Allocates resources. */
+static int
+csa_allocres(struct csa_info *csa, device_t dev)
+{
+	csa_res *resp;
+
+	resp = &csa->res;
+	if (resp->io == NULL) {
+		resp->io = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->io_rid, 0, ~0, CS461x_IO_SIZE, RF_ACTIVE);
+		if (resp->io == NULL)
+			return (1);
+	}
+	if (resp->mem == NULL) {
+		resp->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->mem_rid, 0, ~0, CS461x_MEM_SIZE, RF_ACTIVE);
+		if (resp->mem == NULL)
+			return (1);
+	}
+	if (resp->irq == NULL) {
+		resp->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &resp->irq_rid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
+		if (resp->irq == NULL)
+			return (1);
+	}
+	if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/CS461x_BUFFSIZE, /*boundary*/CS461x_BUFFSIZE,
+			       /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
+			       /*highaddr*/BUS_SPACE_MAXADDR,
+			       /*filter*/NULL, /*filterarg*/NULL,
+			       /*maxsize*/CS461x_BUFFSIZE, /*nsegments*/1, /*maxsegz*/0x3ffff,
+			       /*flags*/0, &csa->parent_dmat) != 0)
+		return (1);
+
+	return (0);
+}
+
+/* Releases resources. */
+static void
+csa_releaseres(struct csa_info *csa, device_t dev)
+{
+	csa_res *resp;
+
+	resp = &csa->res;
+	if (resp->irq != NULL) {
+		bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
+		resp->irq = NULL;
+	}
+	if (resp->io != NULL) {
+		bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
+		resp->io = NULL;
+	}
+	if (resp->mem != NULL) {
+		bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
+		resp->mem = NULL;
+	}
+}
+
+static int pcmcsa_probe(device_t dev);
+static int pcmcsa_attach(device_t dev);
+
+static int
+pcmcsa_probe(device_t dev)
+{
+	char *s;
+	struct sndcard_func *func;
+
+	/* The parent device has already been probed. */
+
+	func = device_get_ivars(dev);
+	if (func == NULL || func->func != SCF_PCM)
+		return (ENXIO);
+
+	s = "CS461x PCM Audio";
+
+	device_set_desc(dev, s);
+	return (0);
+}
+
+static int
+pcmcsa_attach(device_t dev)
+{
+	snddev_info *devinfo;
+	struct csa_info *csa;
+	csa_res *resp;
+	int unit;
+	char status[SND_STATUSLEN];
+	struct ac97_info *codec;
+
+	devinfo = device_get_softc(dev);
+	csa = malloc(sizeof(*csa), M_DEVBUF, M_NOWAIT);
+	if (csa == NULL)
+		return (ENOMEM);
+	bzero(csa, sizeof(*csa));
+	unit = device_get_unit(dev);
+
+	/* Allocate the resources. */
+	resp = &csa->res;
+	resp->io_rid = CS461x_IO_OFFSET;
+	resp->mem_rid = CS461x_MEM_OFFSET;
+	resp->irq_rid = 0;
+	if (csa_allocres(csa, dev)) {
+		csa_releaseres(csa, dev);
+		return (ENXIO);
+	}
+
+	if (csa_init(csa)) {
+		csa_releaseres(csa, dev);
+		return (ENXIO);
+	}
+	codec = ac97_create(csa, csa_rdcd, csa_wrcd);
+	if (codec == NULL)
+		return (ENXIO);
+	mixer_init(devinfo, &ac97_mixer, codec);
+
+	snprintf(status, SND_STATUSLEN, "at irq %ld", rman_get_start(resp->irq));
+
+	/* Enable interrupt. */
+	if (bus_setup_intr(dev, resp->irq, INTR_TYPE_TTY, csa_intr, csa, &csa->ih)) {
+		csa_releaseres(csa, dev);
+		return (ENXIO);
+	}
+	if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
+		csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
+	csa_writemem(resp, BA1_PFIE, csa_readmem(resp, BA1_PFIE) & ~0x0000f03f);
+	csa_writemem(resp, BA1_CIE, (csa_readmem(resp, BA1_CIE) & ~0x0000003f) | 0x00000001);
+
+	if (pcm_register(dev, csa, 1, 1)) {
+		csa_releaseres(csa, dev);
+		return (ENXIO);
+	}
+	pcm_addchan(dev, PCMDIR_REC, &csa_chantemplate, csa);
+	pcm_addchan(dev, PCMDIR_PLAY, &csa_chantemplate, csa);
+	pcm_setstatus(dev, status);
+
+	return (0);
+}
+
+/* ac97 codec */
+
+static u_int32_t
+csa_rdcd(void *devinfo, int regno)
+{
+	u_int32_t data;
+	struct csa_info *csa = (struct csa_info *)devinfo;
+
+	if (csa_readcodec(&csa->res, regno + BA0_AC97_RESET, &data))
+		data = 0;
+
+	return data;
+}
+
+static void
+csa_wrcd(void *devinfo, int regno, u_int32_t data)
+{
+	struct csa_info *csa = (struct csa_info *)devinfo;
+
+	csa_writecodec(&csa->res, regno + BA0_AC97_RESET, data);
+}
+
+static device_method_t pcmcsa_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe , pcmcsa_probe ),
+	DEVMETHOD(device_attach, pcmcsa_attach),
+
+	{ 0, 0 },
+};
+
+static driver_t pcmcsa_driver = {
+	"pcm",
+	pcmcsa_methods,
+	sizeof(snddev_info),
+};
+
+static devclass_t pcm_devclass;
+
+DRIVER_MODULE(pcmcsa, csa, pcmcsa_driver, pcm_devclass, 0, 0);
+
+#endif /* NCSA > 0 */
diff --git a/sys/dev/sound/pci/csareg.h b/sys/dev/sound/pci/csareg.h
new file mode 100644
index 0000000..2453287
--- /dev/null
+++ b/sys/dev/sound/pci/csareg.h
@@ -0,0 +1,1967 @@
+/*-
+ * Copyright (c) 1999 Seigo Tanimura
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _CSA_REG_H
+#define _CSA_REG_H
+
+/* This is the pci device id. */
+#define CS4610_PCI_ID 0x60011013
+#define CS4614_PCI_ID 0x60031013
+#define CS4615_PCI_ID 0x60041013
+#define CS4281_PCI_ID 0x60051013
+
+/* And the offsets in pci configuration space. */
+#define CS461x_IO_OFFSET  0x10
+#define CS461x_IO_SIZE    (4 * 1024)
+#define CS461x_MEM_OFFSET 0x14
+#define CS461x_MEM_SIZE   (1024 * 1024)
+
+/* Buffer size on dma transfer. Fixed for CS416x. */
+#define CS461x_BUFFSIZE   (4 * 1024)
+
+#define GOF_PER_SEC 200
+
+/*
+ * The following constats are orginally in the sample by Crystal Semiconductor.
+ * Copyright (c) 1996-1998 Crystal Semiconductor Corp.
+ */
+
+/*****************************************************************************
+ *
+ * The following define the offsets of the registers accessed via base address
+ * register zero on the CS461x part.
+ *
+ *****************************************************************************/
+#define BA0_HISR                                0x00000000L
+#define BA0_HSR0                                0x00000004L
+#define BA0_HICR                                0x00000008L
+#define BA0_DMSR                                0x00000100L
+#define BA0_HSAR                                0x00000110L
+#define BA0_HDAR                                0x00000114L
+#define BA0_HDMR                                0x00000118L
+#define BA0_HDCR                                0x0000011CL
+#define BA0_PFMC                                0x00000200L
+#define BA0_PFCV1                               0x00000204L
+#define BA0_PFCV2                               0x00000208L
+#define BA0_PCICFG00                            0x00000300L
+#define BA0_PCICFG04                            0x00000304L
+#define BA0_PCICFG08                            0x00000308L
+#define BA0_PCICFG0C                            0x0000030CL
+#define BA0_PCICFG10                            0x00000310L
+#define BA0_PCICFG14                            0x00000314L
+#define BA0_PCICFG18                            0x00000318L
+#define BA0_PCICFG1C                            0x0000031CL
+#define BA0_PCICFG20                            0x00000320L
+#define BA0_PCICFG24                            0x00000324L
+#define BA0_PCICFG28                            0x00000328L
+#define BA0_PCICFG2C                            0x0000032CL
+#define BA0_PCICFG30                            0x00000330L
+#define BA0_PCICFG34                            0x00000334L
+#define BA0_PCICFG38                            0x00000338L
+#define BA0_PCICFG3C                            0x0000033CL
+#define BA0_CLKCR1                              0x00000400L
+#define BA0_CLKCR2                              0x00000404L
+#define BA0_PLLM                                0x00000408L
+#define BA0_PLLCC                               0x0000040CL
+#define BA0_FRR                                 0x00000410L
+#define BA0_CFL1                                0x00000414L
+#define BA0_CFL2                                0x00000418L
+#define BA0_SERMC1                              0x00000420L
+#define BA0_SERMC2                              0x00000424L
+#define BA0_SERC1                               0x00000428L
+#define BA0_SERC2                               0x0000042CL
+#define BA0_SERC3                               0x00000430L
+#define BA0_SERC4                               0x00000434L
+#define BA0_SERC5                               0x00000438L
+#define BA0_SERBSP                              0x0000043CL
+#define BA0_SERBST                              0x00000440L
+#define BA0_SERBCM                              0x00000444L
+#define BA0_SERBAD                              0x00000448L
+#define BA0_SERBCF                              0x0000044CL
+#define BA0_SERBWP                              0x00000450L
+#define BA0_SERBRP                              0x00000454L
+#ifndef NO_CS4612
+#define BA0_ASER_FADDR                          0x00000458L
+#endif
+#define BA0_ACCTL                               0x00000460L
+#define BA0_ACSTS                               0x00000464L
+#define BA0_ACOSV                               0x00000468L
+#define BA0_ACCAD                               0x0000046CL
+#define BA0_ACCDA                               0x00000470L
+#define BA0_ACISV                               0x00000474L
+#define BA0_ACSAD                               0x00000478L
+#define BA0_ACSDA                               0x0000047CL
+#define BA0_JSPT                                0x00000480L
+#define BA0_JSCTL                               0x00000484L
+#define BA0_JSC1                                0x00000488L
+#define BA0_JSC2                                0x0000048CL
+#define BA0_MIDCR                               0x00000490L
+#define BA0_MIDSR                               0x00000494L
+#define BA0_MIDWP                               0x00000498L
+#define BA0_MIDRP                               0x0000049CL
+#define BA0_JSIO                                0x000004A0L
+#ifndef NO_CS4612
+#define BA0_ASER_MASTER                         0x000004A4L
+#endif
+#define BA0_CFGI                                0x000004B0L
+#define BA0_SSVID                               0x000004B4L
+#define BA0_GPIOR                               0x000004B8L
+#ifndef NO_CS4612
+#define BA0_EGPIODR                             0x000004BCL
+#define BA0_EGPIOPTR                            0x000004C0L
+#define BA0_EGPIOTR                             0x000004C4L
+#define BA0_EGPIOWR                             0x000004C8L
+#define BA0_EGPIOSR                             0x000004CCL
+#define BA0_SERC6                               0x000004D0L
+#define BA0_SERC7                               0x000004D4L
+#define BA0_SERACC                              0x000004D8L
+#define BA0_ACCTL2                              0x000004E0L
+#define BA0_ACSTS2                              0x000004E4L
+#define BA0_ACOSV2                              0x000004E8L
+#define BA0_ACCAD2                              0x000004ECL
+#define BA0_ACCDA2                              0x000004F0L
+#define BA0_ACISV2                              0x000004F4L
+#define BA0_ACSAD2                              0x000004F8L
+#define BA0_ACSDA2                              0x000004FCL
+#define BA0_IOTAC0                              0x00000500L
+#define BA0_IOTAC1                              0x00000504L
+#define BA0_IOTAC2                              0x00000508L
+#define BA0_IOTAC3                              0x0000050CL
+#define BA0_IOTAC4                              0x00000510L
+#define BA0_IOTAC5                              0x00000514L
+#define BA0_IOTAC6                              0x00000518L
+#define BA0_IOTAC7                              0x0000051CL
+#define BA0_IOTAC8                              0x00000520L
+#define BA0_IOTAC9                              0x00000524L
+#define BA0_IOTAC10                             0x00000528L
+#define BA0_IOTAC11                             0x0000052CL
+#define BA0_IOTFR0                              0x00000540L
+#define BA0_IOTFR1                              0x00000544L
+#define BA0_IOTFR2                              0x00000548L
+#define BA0_IOTFR3                              0x0000054CL
+#define BA0_IOTFR4                              0x00000550L
+#define BA0_IOTFR5                              0x00000554L
+#define BA0_IOTFR6                              0x00000558L
+#define BA0_IOTFR7                              0x0000055CL
+#define BA0_IOTFIFO                             0x00000580L
+#define BA0_IOTRRD                              0x00000584L
+#define BA0_IOTFP                               0x00000588L
+#define BA0_IOTCR                               0x0000058CL
+#define BA0_DPCID                               0x00000590L
+#define BA0_DPCIA                               0x00000594L
+#define BA0_DPCIC                               0x00000598L
+#define BA0_PCPCIR                              0x00000600L
+#define BA0_PCPCIG                              0x00000604L
+#define BA0_PCPCIEN                             0x00000608L
+#define BA0_EPCIPMC                             0x00000610L
+#endif
+
+/*****************************************************************************
+ *
+ * The following define the offsets of the AC97 shadow registers, which appear
+ * as a virtual extension to the base address register zero memory range.
+ *
+ *****************************************************************************/
+#define BA0_AC97_RESET                          0x00001000L
+#define BA0_AC97_MASTER_VOLUME                  0x00001002L
+#define BA0_AC97_HEADPHONE_VOLUME               0x00001004L
+#define BA0_AC97_MASTER_VOLUME_MONO             0x00001006L
+#define BA0_AC97_MASTER_TONE                    0x00001008L
+#define BA0_AC97_PC_BEEP_VOLUME                 0x0000100AL
+#define BA0_AC97_PHONE_VOLUME                   0x0000100CL
+#define BA0_AC97_MIC_VOLUME                     0x0000100EL
+#define BA0_AC97_LINE_IN_VOLUME                 0x00001010L
+#define BA0_AC97_CD_VOLUME                      0x00001012L
+#define BA0_AC97_VIDEO_VOLUME                   0x00001014L
+#define BA0_AC97_AUX_VOLUME                     0x00001016L
+#define BA0_AC97_PCM_OUT_VOLUME                 0x00001018L
+#define BA0_AC97_RECORD_SELECT                  0x0000101AL
+#define BA0_AC97_RECORD_GAIN                    0x0000101CL
+#define BA0_AC97_RECORD_GAIN_MIC                0x0000101EL
+#define BA0_AC97_GENERAL_PURPOSE                0x00001020L
+#define BA0_AC97_3D_CONTROL                     0x00001022L
+#define BA0_AC97_MODEM_RATE                     0x00001024L
+#define BA0_AC97_POWERDOWN                      0x00001026L
+#define BA0_AC97_RESERVED_28                    0x00001028L
+#define BA0_AC97_RESERVED_2A                    0x0000102AL
+#define BA0_AC97_RESERVED_2C                    0x0000102CL
+#define BA0_AC97_RESERVED_2E                    0x0000102EL
+#define BA0_AC97_RESERVED_30                    0x00001030L
+#define BA0_AC97_RESERVED_32                    0x00001032L
+#define BA0_AC97_RESERVED_34                    0x00001034L
+#define BA0_AC97_RESERVED_36                    0x00001036L
+#define BA0_AC97_RESERVED_38                    0x00001038L
+#define BA0_AC97_RESERVED_3A                    0x0000103AL
+#define BA0_AC97_RESERVED_3C                    0x0000103CL
+#define BA0_AC97_RESERVED_3E                    0x0000103EL
+#define BA0_AC97_RESERVED_40                    0x00001040L
+#define BA0_AC97_RESERVED_42                    0x00001042L
+#define BA0_AC97_RESERVED_44                    0x00001044L
+#define BA0_AC97_RESERVED_46                    0x00001046L
+#define BA0_AC97_RESERVED_48                    0x00001048L
+#define BA0_AC97_RESERVED_4A                    0x0000104AL
+#define BA0_AC97_RESERVED_4C                    0x0000104CL
+#define BA0_AC97_RESERVED_4E                    0x0000104EL
+#define BA0_AC97_RESERVED_50                    0x00001050L
+#define BA0_AC97_RESERVED_52                    0x00001052L
+#define BA0_AC97_RESERVED_54                    0x00001054L
+#define BA0_AC97_RESERVED_56                    0x00001056L
+#define BA0_AC97_RESERVED_58                    0x00001058L
+#define BA0_AC97_VENDOR_RESERVED_5A             0x0000105AL
+#define BA0_AC97_VENDOR_RESERVED_5C             0x0000105CL
+#define BA0_AC97_VENDOR_RESERVED_5E             0x0000105EL
+#define BA0_AC97_VENDOR_RESERVED_60             0x00001060L
+#define BA0_AC97_VENDOR_RESERVED_62             0x00001062L
+#define BA0_AC97_VENDOR_RESERVED_64             0x00001064L
+#define BA0_AC97_VENDOR_RESERVED_66             0x00001066L
+#define BA0_AC97_VENDOR_RESERVED_68             0x00001068L
+#define BA0_AC97_VENDOR_RESERVED_6A             0x0000106AL
+#define BA0_AC97_VENDOR_RESERVED_6C             0x0000106CL
+#define BA0_AC97_VENDOR_RESERVED_6E             0x0000106EL
+#define BA0_AC97_VENDOR_RESERVED_70             0x00001070L
+#define BA0_AC97_VENDOR_RESERVED_72             0x00001072L
+#define BA0_AC97_VENDOR_RESERVED_74             0x00001074L
+#define BA0_AC97_VENDOR_RESERVED_76             0x00001076L
+#define BA0_AC97_VENDOR_RESERVED_78             0x00001078L
+#define BA0_AC97_VENDOR_RESERVED_7A             0x0000107AL
+#define BA0_AC97_VENDOR_ID1                     0x0000107CL
+#define BA0_AC97_VENDOR_ID2                     0x0000107EL
+
+/*****************************************************************************
+ *
+ * The following define the offsets of the registers and memories accessed via
+ * base address register one on the CS461x part.
+ *
+ *****************************************************************************/
+#define BA1_SP_DMEM0                            0x00000000L
+#define BA1_SP_DMEM1                            0x00010000L
+#define BA1_SP_PMEM                             0x00020000L
+#define BA1_SPCR                                0x00030000L
+#define BA1_DREG                                0x00030004L
+#define BA1_DSRWP                               0x00030008L
+#define BA1_TWPR                                0x0003000CL
+#define BA1_SPWR                                0x00030010L
+#define BA1_SPIR                                0x00030014L
+#define BA1_FGR1                                0x00030020L
+#define BA1_SPCS                                0x00030028L
+#define BA1_SDSR                                0x0003002CL
+#define BA1_FRMT                                0x00030030L
+#define BA1_FRCC                                0x00030034L
+#define BA1_FRSC                                0x00030038L
+#define BA1_OMNI_MEM                            0x000E0000L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the PCI interrupt register.
+ *
+ *****************************************************************************/
+#define PI_LINE_MASK                            0x000000FFL
+#define PI_PIN_MASK                             0x0000FF00L
+#define PI_MIN_GRANT_MASK                       0x00FF0000L
+#define PI_MAX_LATENCY_MASK                     0xFF000000L
+#define PI_LINE_SHIFT                           0L
+#define PI_PIN_SHIFT                            8L
+#define PI_MIN_GRANT_SHIFT                      16L
+#define PI_MAX_LATENCY_SHIFT                    24L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the host interrupt status
+ * register.
+ *
+ *****************************************************************************/
+#define HISR_VC_MASK                            0x0000FFFFL
+#define HISR_VC0                                0x00000001L
+#define HISR_VC1                                0x00000002L
+#define HISR_VC2                                0x00000004L
+#define HISR_VC3                                0x00000008L
+#define HISR_VC4                                0x00000010L
+#define HISR_VC5                                0x00000020L
+#define HISR_VC6                                0x00000040L
+#define HISR_VC7                                0x00000080L
+#define HISR_VC8                                0x00000100L
+#define HISR_VC9                                0x00000200L
+#define HISR_VC10                               0x00000400L
+#define HISR_VC11                               0x00000800L
+#define HISR_VC12                               0x00001000L
+#define HISR_VC13                               0x00002000L
+#define HISR_VC14                               0x00004000L
+#define HISR_VC15                               0x00008000L
+#define HISR_INT0                               0x00010000L
+#define HISR_INT1                               0x00020000L
+#define HISR_DMAI                               0x00040000L
+#define HISR_FROVR                              0x00080000L
+#define HISR_MIDI                               0x00100000L
+#ifdef NO_CS4612
+#define HISR_RESERVED                           0x0FE00000L
+#else
+#define HISR_SBINT                              0x00200000L
+#define HISR_RESERVED                           0x0FC00000L
+#endif
+#define HISR_H0P                                0x40000000L
+#define HISR_INTENA                             0x80000000L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the host signal register 0.
+ *
+ *****************************************************************************/
+#define HSR0_VC_MASK                            0xFFFFFFFFL
+#define HSR0_VC16                               0x00000001L
+#define HSR0_VC17                               0x00000002L
+#define HSR0_VC18                               0x00000004L
+#define HSR0_VC19                               0x00000008L
+#define HSR0_VC20                               0x00000010L
+#define HSR0_VC21                               0x00000020L
+#define HSR0_VC22                               0x00000040L
+#define HSR0_VC23                               0x00000080L
+#define HSR0_VC24                               0x00000100L
+#define HSR0_VC25                               0x00000200L
+#define HSR0_VC26                               0x00000400L
+#define HSR0_VC27                               0x00000800L
+#define HSR0_VC28                               0x00001000L
+#define HSR0_VC29                               0x00002000L
+#define HSR0_VC30                               0x00004000L
+#define HSR0_VC31                               0x00008000L
+#define HSR0_VC32                               0x00010000L
+#define HSR0_VC33                               0x00020000L
+#define HSR0_VC34                               0x00040000L
+#define HSR0_VC35                               0x00080000L
+#define HSR0_VC36                               0x00100000L
+#define HSR0_VC37                               0x00200000L
+#define HSR0_VC38                               0x00400000L
+#define HSR0_VC39                               0x00800000L
+#define HSR0_VC40                               0x01000000L
+#define HSR0_VC41                               0x02000000L
+#define HSR0_VC42                               0x04000000L
+#define HSR0_VC43                               0x08000000L
+#define HSR0_VC44                               0x10000000L
+#define HSR0_VC45                               0x20000000L
+#define HSR0_VC46                               0x40000000L
+#define HSR0_VC47                               0x80000000L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the host interrupt control
+ * register.
+ *
+ *****************************************************************************/
+#define HICR_IEV                                0x00000001L
+#define HICR_CHGM                               0x00000002L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the DMA status register.
+ *
+ *****************************************************************************/
+#define DMSR_HP                                 0x00000001L
+#define DMSR_HR                                 0x00000002L
+#define DMSR_SP                                 0x00000004L
+#define DMSR_SR                                 0x00000008L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the host DMA source address
+ * register.
+ *
+ *****************************************************************************/
+#define HSAR_HOST_ADDR_MASK                     0xFFFFFFFFL
+#define HSAR_DSP_ADDR_MASK                      0x0000FFFFL
+#define HSAR_MEMID_MASK                         0x000F0000L
+#define HSAR_MEMID_SP_DMEM0                     0x00000000L
+#define HSAR_MEMID_SP_DMEM1                     0x00010000L
+#define HSAR_MEMID_SP_PMEM                      0x00020000L
+#define HSAR_MEMID_SP_DEBUG                     0x00030000L
+#define HSAR_MEMID_OMNI_MEM                     0x000E0000L
+#define HSAR_END                                0x40000000L
+#define HSAR_ERR                                0x80000000L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the host DMA destination address
+ * register.
+ *
+ *****************************************************************************/
+#define HDAR_HOST_ADDR_MASK                     0xFFFFFFFFL
+#define HDAR_DSP_ADDR_MASK                      0x0000FFFFL
+#define HDAR_MEMID_MASK                         0x000F0000L
+#define HDAR_MEMID_SP_DMEM0                     0x00000000L
+#define HDAR_MEMID_SP_DMEM1                     0x00010000L
+#define HDAR_MEMID_SP_PMEM                      0x00020000L
+#define HDAR_MEMID_SP_DEBUG                     0x00030000L
+#define HDAR_MEMID_OMNI_MEM                     0x000E0000L
+#define HDAR_END                                0x40000000L
+#define HDAR_ERR                                0x80000000L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the host DMA control register.
+ *
+ *****************************************************************************/
+#define HDMR_AC_MASK                            0x0000F000L
+#define HDMR_AC_8_16                            0x00001000L
+#define HDMR_AC_M_S                             0x00002000L
+#define HDMR_AC_B_L                             0x00004000L
+#define HDMR_AC_S_U                             0x00008000L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the host DMA control register.
+ *
+ *****************************************************************************/
+#define HDCR_COUNT_MASK                         0x000003FFL
+#define HDCR_DONE                               0x00004000L
+#define HDCR_OPT                                0x00008000L
+#define HDCR_WBD                                0x00400000L
+#define HDCR_WBS                                0x00800000L
+#define HDCR_DMS_MASK                           0x07000000L
+#define HDCR_DMS_LINEAR                         0x00000000L
+#define HDCR_DMS_16_DWORDS                      0x01000000L
+#define HDCR_DMS_32_DWORDS                      0x02000000L
+#define HDCR_DMS_64_DWORDS                      0x03000000L
+#define HDCR_DMS_128_DWORDS                     0x04000000L
+#define HDCR_DMS_256_DWORDS                     0x05000000L
+#define HDCR_DMS_512_DWORDS                     0x06000000L
+#define HDCR_DMS_1024_DWORDS                    0x07000000L
+#define HDCR_DH                                 0x08000000L
+#define HDCR_SMS_MASK                           0x70000000L
+#define HDCR_SMS_LINEAR                         0x00000000L
+#define HDCR_SMS_16_DWORDS                      0x10000000L
+#define HDCR_SMS_32_DWORDS                      0x20000000L
+#define HDCR_SMS_64_DWORDS                      0x30000000L
+#define HDCR_SMS_128_DWORDS                     0x40000000L
+#define HDCR_SMS_256_DWORDS                     0x50000000L
+#define HDCR_SMS_512_DWORDS                     0x60000000L
+#define HDCR_SMS_1024_DWORDS                    0x70000000L
+#define HDCR_SH                                 0x80000000L
+#define HDCR_COUNT_SHIFT                        0L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the performance monitor control
+ * register.
+ *
+ *****************************************************************************/
+#define PFMC_C1SS_MASK                          0x0000001FL
+#define PFMC_C1EV                               0x00000020L
+#define PFMC_C1RS                               0x00008000L
+#define PFMC_C2SS_MASK                          0x001F0000L
+#define PFMC_C2EV                               0x00200000L
+#define PFMC_C2RS                               0x80000000L
+#define PFMC_C1SS_SHIFT                         0L
+#define PFMC_C2SS_SHIFT                         16L
+#define PFMC_BUS_GRANT                          0L
+#define PFMC_GRANT_AFTER_REQ                    1L
+#define PFMC_TRANSACTION                        2L
+#define PFMC_DWORD_TRANSFER                     3L
+#define PFMC_SLAVE_READ                         4L
+#define PFMC_SLAVE_WRITE                        5L
+#define PFMC_PREEMPTION                         6L
+#define PFMC_DISCONNECT_RETRY                   7L
+#define PFMC_INTERRUPT                          8L
+#define PFMC_BUS_OWNERSHIP                      9L
+#define PFMC_TRANSACTION_LAG                    10L
+#define PFMC_PCI_CLOCK                          11L
+#define PFMC_SERIAL_CLOCK                       12L
+#define PFMC_SP_CLOCK                           13L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the performance counter value 1
+ * register.
+ *
+ *****************************************************************************/
+#define PFCV1_PC1V_MASK                         0xFFFFFFFFL
+#define PFCV1_PC1V_SHIFT                        0L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the performance counter value 2
+ * register.
+ *
+ *****************************************************************************/
+#define PFCV2_PC2V_MASK                         0xFFFFFFFFL
+#define PFCV2_PC2V_SHIFT                        0L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the clock control register 1.
+ *
+ *****************************************************************************/
+#define CLKCR1_OSCS                             0x00000001L
+#define CLKCR1_OSCP                             0x00000002L
+#define CLKCR1_PLLSS_MASK                       0x0000000CL
+#define CLKCR1_PLLSS_SERIAL                     0x00000000L
+#define CLKCR1_PLLSS_CRYSTAL                    0x00000004L
+#define CLKCR1_PLLSS_PCI                        0x00000008L
+#define CLKCR1_PLLSS_RESERVED                   0x0000000CL
+#define CLKCR1_PLLP                             0x00000010L
+#define CLKCR1_SWCE                             0x00000020L
+#define CLKCR1_PLLOS                            0x00000040L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the clock control register 2.
+ *
+ *****************************************************************************/
+#define CLKCR2_PDIVS_MASK                       0x0000000FL
+#define CLKCR2_PDIVS_1                          0x00000001L
+#define CLKCR2_PDIVS_2                          0x00000002L
+#define CLKCR2_PDIVS_4                          0x00000004L
+#define CLKCR2_PDIVS_7                          0x00000007L
+#define CLKCR2_PDIVS_8                          0x00000008L
+#define CLKCR2_PDIVS_16                         0x00000000L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the PLL multiplier register.
+ *
+ *****************************************************************************/
+#define PLLM_MASK                               0x000000FFL
+#define PLLM_SHIFT                              0L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the PLL capacitor coefficient
+ * register.
+ *
+ *****************************************************************************/
+#define PLLCC_CDR_MASK                          0x00000007L
+#ifndef NO_CS4610
+#define PLLCC_CDR_240_350_MHZ                   0x00000000L
+#define PLLCC_CDR_184_265_MHZ                   0x00000001L
+#define PLLCC_CDR_144_205_MHZ                   0x00000002L
+#define PLLCC_CDR_111_160_MHZ                   0x00000003L
+#define PLLCC_CDR_87_123_MHZ                    0x00000004L
+#define PLLCC_CDR_67_96_MHZ                     0x00000005L
+#define PLLCC_CDR_52_74_MHZ                     0x00000006L
+#define PLLCC_CDR_45_58_MHZ                     0x00000007L
+#endif
+#ifndef NO_CS4612
+#define PLLCC_CDR_271_398_MHZ                   0x00000000L
+#define PLLCC_CDR_227_330_MHZ                   0x00000001L
+#define PLLCC_CDR_167_239_MHZ                   0x00000002L
+#define PLLCC_CDR_150_215_MHZ                   0x00000003L
+#define PLLCC_CDR_107_154_MHZ                   0x00000004L
+#define PLLCC_CDR_98_140_MHZ                    0x00000005L
+#define PLLCC_CDR_73_104_MHZ                    0x00000006L
+#define PLLCC_CDR_63_90_MHZ                     0x00000007L
+#endif
+#define PLLCC_LPF_MASK                          0x000000F8L
+#ifndef NO_CS4610
+#define PLLCC_LPF_23850_60000_KHZ               0x00000000L
+#define PLLCC_LPF_7960_26290_KHZ                0x00000008L
+#define PLLCC_LPF_4160_10980_KHZ                0x00000018L
+#define PLLCC_LPF_1740_4580_KHZ                 0x00000038L
+#define PLLCC_LPF_724_1910_KHZ                  0x00000078L
+#define PLLCC_LPF_317_798_KHZ                   0x000000F8L
+#endif
+#ifndef NO_CS4612
+#define PLLCC_LPF_25580_64530_KHZ               0x00000000L
+#define PLLCC_LPF_14360_37270_KHZ               0x00000008L
+#define PLLCC_LPF_6100_16020_KHZ                0x00000018L
+#define PLLCC_LPF_2540_6690_KHZ                 0x00000038L
+#define PLLCC_LPF_1050_2780_KHZ                 0x00000078L
+#define PLLCC_LPF_450_1160_KHZ                  0x000000F8L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the feature reporting register.
+ *
+ *****************************************************************************/
+#define FRR_FAB_MASK                            0x00000003L
+#define FRR_MASK_MASK                           0x0000001CL
+#ifdef NO_CS4612
+#define FRR_CFOP_MASK                           0x000000E0L
+#else
+#define FRR_CFOP_MASK                           0x00000FE0L
+#endif
+#define FRR_CFOP_NOT_DVD                        0x00000020L
+#define FRR_CFOP_A3D                            0x00000040L
+#define FRR_CFOP_128_PIN                        0x00000080L
+#ifndef NO_CS4612
+#define FRR_CFOP_CS4280                         0x00000800L
+#endif
+#define FRR_FAB_SHIFT                           0L
+#define FRR_MASK_SHIFT                          2L
+#define FRR_CFOP_SHIFT                          5L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the configuration load 1
+ * register.
+ *
+ *****************************************************************************/
+#define CFL1_CLOCK_SOURCE_MASK                  0x00000003L
+#define CFL1_CLOCK_SOURCE_CS423X                0x00000000L
+#define CFL1_CLOCK_SOURCE_AC97                  0x00000001L
+#define CFL1_CLOCK_SOURCE_CRYSTAL               0x00000002L
+#define CFL1_CLOCK_SOURCE_DUAL_AC97             0x00000003L
+#define CFL1_VALID_DATA_MASK                    0x000000FFL
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the configuration load 2
+ * register.
+ *
+ *****************************************************************************/
+#define CFL2_VALID_DATA_MASK                    0x000000FFL
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the serial port master control
+ * register 1.
+ *
+ *****************************************************************************/
+#define SERMC1_MSPE                             0x00000001L
+#define SERMC1_PTC_MASK                         0x0000000EL
+#define SERMC1_PTC_CS423X                       0x00000000L
+#define SERMC1_PTC_AC97                         0x00000002L
+#define SERMC1_PTC_DAC                          0x00000004L
+#define SERMC1_PLB                              0x00000010L
+#define SERMC1_XLB                              0x00000020L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the serial port master control
+ * register 2.
+ *
+ *****************************************************************************/
+#define SERMC2_LROE                             0x00000001L
+#define SERMC2_MCOE                             0x00000002L
+#define SERMC2_MCDIV                            0x00000004L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the serial port 1 configuration
+ * register.
+ *
+ *****************************************************************************/
+#define SERC1_SO1EN                             0x00000001L
+#define SERC1_SO1F_MASK                         0x0000000EL
+#define SERC1_SO1F_CS423X                       0x00000000L
+#define SERC1_SO1F_AC97                         0x00000002L
+#define SERC1_SO1F_DAC                          0x00000004L
+#define SERC1_SO1F_SPDIF                        0x00000006L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the serial port 2 configuration
+ * register.
+ *
+ *****************************************************************************/
+#define SERC2_SI1EN                             0x00000001L
+#define SERC2_SI1F_MASK                         0x0000000EL
+#define SERC2_SI1F_CS423X                       0x00000000L
+#define SERC2_SI1F_AC97                         0x00000002L
+#define SERC2_SI1F_ADC                          0x00000004L
+#define SERC2_SI1F_SPDIF                        0x00000006L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the serial port 3 configuration
+ * register.
+ *
+ *****************************************************************************/
+#define SERC3_SO2EN                             0x00000001L
+#define SERC3_SO2F_MASK                         0x00000006L
+#define SERC3_SO2F_DAC                          0x00000000L
+#define SERC3_SO2F_SPDIF                        0x00000002L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the serial port 4 configuration
+ * register.
+ *
+ *****************************************************************************/
+#define SERC4_SO3EN                             0x00000001L
+#define SERC4_SO3F_MASK                         0x00000006L
+#define SERC4_SO3F_DAC                          0x00000000L
+#define SERC4_SO3F_SPDIF                        0x00000002L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the serial port 5 configuration
+ * register.
+ *
+ *****************************************************************************/
+#define SERC5_SI2EN                             0x00000001L
+#define SERC5_SI2F_MASK                         0x00000006L
+#define SERC5_SI2F_ADC                          0x00000000L
+#define SERC5_SI2F_SPDIF                        0x00000002L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the serial port backdoor sample
+ * pointer register.
+ *
+ *****************************************************************************/
+#define SERBSP_FSP_MASK                         0x0000000FL
+#define SERBSP_FSP_SHIFT                        0L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the serial port backdoor status
+ * register.
+ *
+ *****************************************************************************/
+#define SERBST_RRDY                             0x00000001L
+#define SERBST_WBSY                             0x00000002L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the serial port backdoor command
+ * register.
+ *
+ *****************************************************************************/
+#define SERBCM_RDC                              0x00000001L
+#define SERBCM_WRC                              0x00000002L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the serial port backdoor address
+ * register.
+ *
+ *****************************************************************************/
+#ifdef NO_CS4612
+#define SERBAD_FAD_MASK                         0x000000FFL
+#else
+#define SERBAD_FAD_MASK                         0x000001FFL
+#endif
+#define SERBAD_FAD_SHIFT                        0L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the serial port backdoor
+ * configuration register.
+ *
+ *****************************************************************************/
+#define SERBCF_HBP                              0x00000001L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the serial port backdoor write
+ * port register.
+ *
+ *****************************************************************************/
+#define SERBWP_FWD_MASK                         0x000FFFFFL
+#define SERBWP_FWD_SHIFT                        0L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the serial port backdoor read
+ * port register.
+ *
+ *****************************************************************************/
+#define SERBRP_FRD_MASK                         0x000FFFFFL
+#define SERBRP_FRD_SHIFT                        0L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the async FIFO address register.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define ASER_FADDR_A1_MASK                      0x000001FFL
+#define ASER_FADDR_EN1                          0x00008000L
+#define ASER_FADDR_A2_MASK                      0x01FF0000L
+#define ASER_FADDR_EN2                          0x80000000L
+#define ASER_FADDR_A1_SHIFT                     0L
+#define ASER_FADDR_A2_SHIFT                     16L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the AC97 control register.
+ *
+ *****************************************************************************/
+#define ACCTL_RSTN                              0x00000001L
+#define ACCTL_ESYN                              0x00000002L
+#define ACCTL_VFRM                              0x00000004L
+#define ACCTL_DCV                               0x00000008L
+#define ACCTL_CRW                               0x00000010L
+#define ACCTL_ASYN                              0x00000020L
+#ifndef NO_CS4612
+#define ACCTL_TC                                0x00000040L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the AC97 status register.
+ *
+ *****************************************************************************/
+#define ACSTS_CRDY                              0x00000001L
+#define ACSTS_VSTS                              0x00000002L
+#ifndef NO_CS4612
+#define ACSTS_WKUP                              0x00000004L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the AC97 output slot valid
+ * register.
+ *
+ *****************************************************************************/
+#define ACOSV_SLV3                              0x00000001L
+#define ACOSV_SLV4                              0x00000002L
+#define ACOSV_SLV5                              0x00000004L
+#define ACOSV_SLV6                              0x00000008L
+#define ACOSV_SLV7                              0x00000010L
+#define ACOSV_SLV8                              0x00000020L
+#define ACOSV_SLV9                              0x00000040L
+#define ACOSV_SLV10                             0x00000080L
+#define ACOSV_SLV11                             0x00000100L
+#define ACOSV_SLV12                             0x00000200L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the AC97 command address
+ * register.
+ *
+ *****************************************************************************/
+#define ACCAD_CI_MASK                           0x0000007FL
+#define ACCAD_CI_SHIFT                          0L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the AC97 command data register.
+ *
+ *****************************************************************************/
+#define ACCDA_CD_MASK                           0x0000FFFFL
+#define ACCDA_CD_SHIFT                          0L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the AC97 input slot valid
+ * register.
+ *
+ *****************************************************************************/
+#define ACISV_ISV3                              0x00000001L
+#define ACISV_ISV4                              0x00000002L
+#define ACISV_ISV5                              0x00000004L
+#define ACISV_ISV6                              0x00000008L
+#define ACISV_ISV7                              0x00000010L
+#define ACISV_ISV8                              0x00000020L
+#define ACISV_ISV9                              0x00000040L
+#define ACISV_ISV10                             0x00000080L
+#define ACISV_ISV11                             0x00000100L
+#define ACISV_ISV12                             0x00000200L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the AC97 status address
+ * register.
+ *
+ *****************************************************************************/
+#define ACSAD_SI_MASK                           0x0000007FL
+#define ACSAD_SI_SHIFT                          0L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the AC97 status data register.
+ *
+ *****************************************************************************/
+#define ACSDA_SD_MASK                           0x0000FFFFL
+#define ACSDA_SD_SHIFT                          0L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the joystick poll/trigger
+ * register.
+ *
+ *****************************************************************************/
+#define JSPT_CAX                                0x00000001L
+#define JSPT_CAY                                0x00000002L
+#define JSPT_CBX                                0x00000004L
+#define JSPT_CBY                                0x00000008L
+#define JSPT_BA1                                0x00000010L
+#define JSPT_BA2                                0x00000020L
+#define JSPT_BB1                                0x00000040L
+#define JSPT_BB2                                0x00000080L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the joystick control register.
+ *
+ *****************************************************************************/
+#define JSCTL_SP_MASK                           0x00000003L
+#define JSCTL_SP_SLOW                           0x00000000L
+#define JSCTL_SP_MEDIUM_SLOW                    0x00000001L
+#define JSCTL_SP_MEDIUM_FAST                    0x00000002L
+#define JSCTL_SP_FAST                           0x00000003L
+#define JSCTL_ARE                               0x00000004L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the joystick coordinate pair 1
+ * readback register.
+ *
+ *****************************************************************************/
+#define JSC1_Y1V_MASK                           0x0000FFFFL
+#define JSC1_X1V_MASK                           0xFFFF0000L
+#define JSC1_Y1V_SHIFT                          0L
+#define JSC1_X1V_SHIFT                          16L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the joystick coordinate pair 2
+ * readback register.
+ *
+ *****************************************************************************/
+#define JSC2_Y2V_MASK                           0x0000FFFFL
+#define JSC2_X2V_MASK                           0xFFFF0000L
+#define JSC2_Y2V_SHIFT                          0L
+#define JSC2_X2V_SHIFT                          16L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the MIDI control register.
+ *
+ *****************************************************************************/
+#define MIDCR_TXE                               0x00000001L
+#define MIDCR_RXE                               0x00000002L
+#define MIDCR_RIE                               0x00000004L
+#define MIDCR_TIE                               0x00000008L
+#define MIDCR_MLB                               0x00000010L
+#define MIDCR_MRST                              0x00000020L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the MIDI status register.
+ *
+ *****************************************************************************/
+#define MIDSR_TBF                               0x00000001L
+#define MIDSR_RBE                               0x00000002L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the MIDI write port register.
+ *
+ *****************************************************************************/
+#define MIDWP_MWD_MASK                          0x000000FFL
+#define MIDWP_MWD_SHIFT                         0L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the MIDI read port register.
+ *
+ *****************************************************************************/
+#define MIDRP_MRD_MASK                          0x000000FFL
+#define MIDRP_MRD_SHIFT                         0L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the joystick GPIO register.
+ *
+ *****************************************************************************/
+#define JSIO_DAX                                0x00000001L
+#define JSIO_DAY                                0x00000002L
+#define JSIO_DBX                                0x00000004L
+#define JSIO_DBY                                0x00000008L
+#define JSIO_AXOE                               0x00000010L
+#define JSIO_AYOE                               0x00000020L
+#define JSIO_BXOE                               0x00000040L
+#define JSIO_BYOE                               0x00000080L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the master async/sync serial
+ * port enable register.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define ASER_MASTER_ME                          0x00000001L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the configuration interface
+ * register.
+ *
+ *****************************************************************************/
+#define CFGI_CLK                                0x00000001L
+#define CFGI_DOUT                               0x00000002L
+#define CFGI_DIN_EEN                            0x00000004L
+#define CFGI_EELD                               0x00000008L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the subsystem ID and vendor ID
+ * register.
+ *
+ *****************************************************************************/
+#define SSVID_VID_MASK                          0x0000FFFFL
+#define SSVID_SID_MASK                          0xFFFF0000L
+#define SSVID_VID_SHIFT                         0L
+#define SSVID_SID_SHIFT                         16L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the GPIO pin interface register.
+ *
+ *****************************************************************************/
+#define GPIOR_VOLDN                             0x00000001L
+#define GPIOR_VOLUP                             0x00000002L
+#define GPIOR_SI2D                              0x00000004L
+#define GPIOR_SI2OE                             0x00000008L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the extended GPIO pin direction
+ * register.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define EGPIODR_GPOE0                           0x00000001L
+#define EGPIODR_GPOE1                           0x00000002L
+#define EGPIODR_GPOE2                           0x00000004L
+#define EGPIODR_GPOE3                           0x00000008L
+#define EGPIODR_GPOE4                           0x00000010L
+#define EGPIODR_GPOE5                           0x00000020L
+#define EGPIODR_GPOE6                           0x00000040L
+#define EGPIODR_GPOE7                           0x00000080L
+#define EGPIODR_GPOE8                           0x00000100L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the extended GPIO pin polarity/
+ * type register.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define EGPIOPTR_GPPT0                          0x00000001L
+#define EGPIOPTR_GPPT1                          0x00000002L
+#define EGPIOPTR_GPPT2                          0x00000004L
+#define EGPIOPTR_GPPT3                          0x00000008L
+#define EGPIOPTR_GPPT4                          0x00000010L
+#define EGPIOPTR_GPPT5                          0x00000020L
+#define EGPIOPTR_GPPT6                          0x00000040L
+#define EGPIOPTR_GPPT7                          0x00000080L
+#define EGPIOPTR_GPPT8                          0x00000100L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the extended GPIO pin sticky
+ * register.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define EGPIOTR_GPS0                            0x00000001L
+#define EGPIOTR_GPS1                            0x00000002L
+#define EGPIOTR_GPS2                            0x00000004L
+#define EGPIOTR_GPS3                            0x00000008L
+#define EGPIOTR_GPS4                            0x00000010L
+#define EGPIOTR_GPS5                            0x00000020L
+#define EGPIOTR_GPS6                            0x00000040L
+#define EGPIOTR_GPS7                            0x00000080L
+#define EGPIOTR_GPS8                            0x00000100L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the extended GPIO ping wakeup
+ * register.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define EGPIOWR_GPW0                            0x00000001L
+#define EGPIOWR_GPW1                            0x00000002L
+#define EGPIOWR_GPW2                            0x00000004L
+#define EGPIOWR_GPW3                            0x00000008L
+#define EGPIOWR_GPW4                            0x00000010L
+#define EGPIOWR_GPW5                            0x00000020L
+#define EGPIOWR_GPW6                            0x00000040L
+#define EGPIOWR_GPW7                            0x00000080L
+#define EGPIOWR_GPW8                            0x00000100L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the extended GPIO pin status
+ * register.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define EGPIOSR_GPS0                            0x00000001L
+#define EGPIOSR_GPS1                            0x00000002L
+#define EGPIOSR_GPS2                            0x00000004L
+#define EGPIOSR_GPS3                            0x00000008L
+#define EGPIOSR_GPS4                            0x00000010L
+#define EGPIOSR_GPS5                            0x00000020L
+#define EGPIOSR_GPS6                            0x00000040L
+#define EGPIOSR_GPS7                            0x00000080L
+#define EGPIOSR_GPS8                            0x00000100L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the serial port 6 configuration
+ * register.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define SERC6_ASDO2EN                           0x00000001L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the serial port 7 configuration
+ * register.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define SERC7_ASDI2EN                           0x00000001L
+#define SERC7_POSILB                            0x00000002L
+#define SERC7_SIPOLB                            0x00000004L
+#define SERC7_SOSILB                            0x00000008L
+#define SERC7_SISOLB                            0x00000010L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the serial port AC link
+ * configuration register.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define SERACC_CODEC_TYPE_MASK                  0x00000001L
+#define SERACC_CODEC_TYPE_1_03                  0x00000000L
+#define SERACC_CODEC_TYPE_2_0                   0x00000001L
+#define SERACC_TWO_CODECS                       0x00000002L
+#define SERACC_MDM                              0x00000004L
+#define SERACC_HSP                              0x00000008L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the AC97 control register 2.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define ACCTL2_RSTN                             0x00000001L
+#define ACCTL2_ESYN                             0x00000002L
+#define ACCTL2_VFRM                             0x00000004L
+#define ACCTL2_DCV                              0x00000008L
+#define ACCTL2_CRW                              0x00000010L
+#define ACCTL2_ASYN                             0x00000020L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the AC97 status register 2.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define ACSTS2_CRDY                             0x00000001L
+#define ACSTS2_VSTS                             0x00000002L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the AC97 output slot valid
+ * register 2.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define ACOSV2_SLV3                             0x00000001L
+#define ACOSV2_SLV4                             0x00000002L
+#define ACOSV2_SLV5                             0x00000004L
+#define ACOSV2_SLV6                             0x00000008L
+#define ACOSV2_SLV7                             0x00000010L
+#define ACOSV2_SLV8                             0x00000020L
+#define ACOSV2_SLV9                             0x00000040L
+#define ACOSV2_SLV10                            0x00000080L
+#define ACOSV2_SLV11                            0x00000100L
+#define ACOSV2_SLV12                            0x00000200L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the AC97 command address
+ * register 2.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define ACCAD2_CI_MASK                          0x0000007FL
+#define ACCAD2_CI_SHIFT                         0L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the AC97 command data register
+ * 2.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define ACCDA2_CD_MASK                          0x0000FFFFL
+#define ACCDA2_CD_SHIFT                         0L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the AC97 input slot valid
+ * register 2.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define ACISV2_ISV3                             0x00000001L
+#define ACISV2_ISV4                             0x00000002L
+#define ACISV2_ISV5                             0x00000004L
+#define ACISV2_ISV6                             0x00000008L
+#define ACISV2_ISV7                             0x00000010L
+#define ACISV2_ISV8                             0x00000020L
+#define ACISV2_ISV9                             0x00000040L
+#define ACISV2_ISV10                            0x00000080L
+#define ACISV2_ISV11                            0x00000100L
+#define ACISV2_ISV12                            0x00000200L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the AC97 status address
+ * register 2.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define ACSAD2_SI_MASK                          0x0000007FL
+#define ACSAD2_SI_SHIFT                         0L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the AC97 status data register 2.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define ACSDA2_SD_MASK                          0x0000FFFFL
+#define ACSDA2_SD_SHIFT                         0L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the I/O trap address and control
+ * registers (all 12).
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define IOTAC_SA_MASK                           0x0000FFFFL
+#define IOTAC_MSK_MASK                          0x000F0000L
+#define IOTAC_IODC_MASK                         0x06000000L
+#define IOTAC_IODC_16_BIT                       0x00000000L
+#define IOTAC_IODC_10_BIT                       0x02000000L
+#define IOTAC_IODC_12_BIT                       0x04000000L
+#define IOTAC_WSPI                              0x08000000L
+#define IOTAC_RSPI                              0x10000000L
+#define IOTAC_WSE                               0x20000000L
+#define IOTAC_WE                                0x40000000L
+#define IOTAC_RE                                0x80000000L
+#define IOTAC_SA_SHIFT                          0L
+#define IOTAC_MSK_SHIFT                         16L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the I/O trap fast read registers
+ * (all 8).
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define IOTFR_D_MASK                            0x0000FFFFL
+#define IOTFR_A_MASK                            0x000F0000L
+#define IOTFR_R_MASK                            0x0F000000L
+#define IOTFR_ALL                               0x40000000L
+#define IOTFR_VL                                0x80000000L
+#define IOTFR_D_SHIFT                           0L
+#define IOTFR_A_SHIFT                           16L
+#define IOTFR_R_SHIFT                           24L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the I/O trap FIFO register.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define IOTFIFO_BA_MASK                         0x00003FFFL
+#define IOTFIFO_S_MASK                          0x00FF0000L
+#define IOTFIFO_OF                              0x40000000L
+#define IOTFIFO_SPIOF                           0x80000000L
+#define IOTFIFO_BA_SHIFT                        0L
+#define IOTFIFO_S_SHIFT                         16L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the I/O trap retry read data
+ * register.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define IOTRRD_D_MASK                           0x0000FFFFL
+#define IOTRRD_RDV                              0x80000000L
+#define IOTRRD_D_SHIFT                          0L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the I/O trap FIFO pointer
+ * register.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define IOTFP_CA_MASK                           0x00003FFFL
+#define IOTFP_PA_MASK                           0x3FFF0000L
+#define IOTFP_CA_SHIFT                          0L
+#define IOTFP_PA_SHIFT                          16L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the I/O trap control register.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define IOTCR_ITD                               0x00000001L
+#define IOTCR_HRV                               0x00000002L
+#define IOTCR_SRV                               0x00000004L
+#define IOTCR_DTI                               0x00000008L
+#define IOTCR_DFI                               0x00000010L
+#define IOTCR_DDP                               0x00000020L
+#define IOTCR_JTE                               0x00000040L
+#define IOTCR_PPE                               0x00000080L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the direct PCI data register.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define DPCID_D_MASK                            0xFFFFFFFFL
+#define DPCID_D_SHIFT                           0L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the direct PCI address register.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define DPCIA_A_MASK                            0xFFFFFFFFL
+#define DPCIA_A_SHIFT                           0L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the direct PCI command register.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define DPCIC_C_MASK                            0x0000000FL
+#define DPCIC_C_IOREAD                          0x00000002L
+#define DPCIC_C_IOWRITE                         0x00000003L
+#define DPCIC_BE_MASK                           0x000000F0L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the PC/PCI request register.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define PCPCIR_RDC_MASK                         0x00000007L
+#define PCPCIR_C_MASK                           0x00007000L
+#define PCPCIR_REQ                              0x00008000L
+#define PCPCIR_RDC_SHIFT                        0L
+#define PCPCIR_C_SHIFT                          12L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the PC/PCI grant register.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define PCPCIG_GDC_MASK                         0x00000007L
+#define PCPCIG_VL                               0x00008000L
+#define PCPCIG_GDC_SHIFT                        0L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the PC/PCI master enable
+ * register.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define PCPCIEN_EN                              0x00000001L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the extended PCI power
+ * management control register.
+ *
+ *****************************************************************************/
+#ifndef NO_CS4612
+#define EPCIPMC_GWU                             0x00000001L
+#define EPCIPMC_FSPC                            0x00000002L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the SP control register.
+ *
+ *****************************************************************************/
+#define SPCR_RUN                                0x00000001L
+#define SPCR_STPFR                              0x00000002L
+#define SPCR_RUNFR                              0x00000004L
+#define SPCR_TICK                               0x00000008L
+#define SPCR_DRQEN                              0x00000020L
+#define SPCR_RSTSP                              0x00000040L
+#define SPCR_OREN                               0x00000080L
+#ifndef NO_CS4612
+#define SPCR_PCIINT                             0x00000100L
+#define SPCR_OINTD                              0x00000200L
+#define SPCR_CRE                                0x00008000L
+#endif
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the debug index register.
+ *
+ *****************************************************************************/
+#define DREG_REGID_MASK                         0x0000007FL
+#define DREG_DEBUG                              0x00000080L
+#define DREG_RGBK_MASK                          0x00000700L
+#define DREG_TRAP                               0x00000800L
+#if !defined(NO_CS4612)
+#if !defined(NO_CS4615)
+#define DREG_TRAPX                              0x00001000L
+#endif
+#endif
+#define DREG_REGID_SHIFT                        0L
+#define DREG_RGBK_SHIFT                         8L
+#define DREG_RGBK_REGID_MASK                    0x0000077FL
+#define DREG_REGID_R0                           0x00000010L
+#define DREG_REGID_R1                           0x00000011L
+#define DREG_REGID_R2                           0x00000012L
+#define DREG_REGID_R3                           0x00000013L
+#define DREG_REGID_R4                           0x00000014L
+#define DREG_REGID_R5                           0x00000015L
+#define DREG_REGID_R6                           0x00000016L
+#define DREG_REGID_R7                           0x00000017L
+#define DREG_REGID_R8                           0x00000018L
+#define DREG_REGID_R9                           0x00000019L
+#define DREG_REGID_RA                           0x0000001AL
+#define DREG_REGID_RB                           0x0000001BL
+#define DREG_REGID_RC                           0x0000001CL
+#define DREG_REGID_RD                           0x0000001DL
+#define DREG_REGID_RE                           0x0000001EL
+#define DREG_REGID_RF                           0x0000001FL
+#define DREG_REGID_RA_BUS_LOW                   0x00000020L
+#define DREG_REGID_RA_BUS_HIGH                  0x00000038L
+#define DREG_REGID_YBUS_LOW                     0x00000050L
+#define DREG_REGID_YBUS_HIGH                    0x00000058L
+#define DREG_REGID_TRAP_0                       0x00000100L
+#define DREG_REGID_TRAP_1                       0x00000101L
+#define DREG_REGID_TRAP_2                       0x00000102L
+#define DREG_REGID_TRAP_3                       0x00000103L
+#define DREG_REGID_TRAP_4                       0x00000104L
+#define DREG_REGID_TRAP_5                       0x00000105L
+#define DREG_REGID_TRAP_6                       0x00000106L
+#define DREG_REGID_TRAP_7                       0x00000107L
+#define DREG_REGID_INDIRECT_ADDRESS             0x0000010EL
+#define DREG_REGID_TOP_OF_STACK                 0x0000010FL
+#if !defined(NO_CS4612)
+#if !defined(NO_CS4615)
+#define DREG_REGID_TRAP_8                       0x00000110L
+#define DREG_REGID_TRAP_9                       0x00000111L
+#define DREG_REGID_TRAP_10                      0x00000112L
+#define DREG_REGID_TRAP_11                      0x00000113L
+#define DREG_REGID_TRAP_12                      0x00000114L
+#define DREG_REGID_TRAP_13                      0x00000115L
+#define DREG_REGID_TRAP_14                      0x00000116L
+#define DREG_REGID_TRAP_15                      0x00000117L
+#define DREG_REGID_TRAP_16                      0x00000118L
+#define DREG_REGID_TRAP_17                      0x00000119L
+#define DREG_REGID_TRAP_18                      0x0000011AL
+#define DREG_REGID_TRAP_19                      0x0000011BL
+#define DREG_REGID_TRAP_20                      0x0000011CL
+#define DREG_REGID_TRAP_21                      0x0000011DL
+#define DREG_REGID_TRAP_22                      0x0000011EL
+#define DREG_REGID_TRAP_23                      0x0000011FL
+#endif
+#endif
+#define DREG_REGID_RSA0_LOW                     0x00000200L
+#define DREG_REGID_RSA0_HIGH                    0x00000201L
+#define DREG_REGID_RSA1_LOW                     0x00000202L
+#define DREG_REGID_RSA1_HIGH                    0x00000203L
+#define DREG_REGID_RSA2                         0x00000204L
+#define DREG_REGID_RSA3                         0x00000205L
+#define DREG_REGID_RSI0_LOW                     0x00000206L
+#define DREG_REGID_RSI0_HIGH                    0x00000207L
+#define DREG_REGID_RSI1                         0x00000208L
+#define DREG_REGID_RSI2                         0x00000209L
+#define DREG_REGID_SAGUSTATUS                   0x0000020AL
+#define DREG_REGID_RSCONFIG01_LOW               0x0000020BL
+#define DREG_REGID_RSCONFIG01_HIGH              0x0000020CL
+#define DREG_REGID_RSCONFIG23_LOW               0x0000020DL
+#define DREG_REGID_RSCONFIG23_HIGH              0x0000020EL
+#define DREG_REGID_RSDMA01E                     0x0000020FL
+#define DREG_REGID_RSDMA23E                     0x00000210L
+#define DREG_REGID_RSD0_LOW                     0x00000211L
+#define DREG_REGID_RSD0_HIGH                    0x00000212L
+#define DREG_REGID_RSD1_LOW                     0x00000213L
+#define DREG_REGID_RSD1_HIGH                    0x00000214L
+#define DREG_REGID_RSD2_LOW                     0x00000215L
+#define DREG_REGID_RSD2_HIGH                    0x00000216L
+#define DREG_REGID_RSD3_LOW                     0x00000217L
+#define DREG_REGID_RSD3_HIGH                    0x00000218L
+#define DREG_REGID_SRAR_HIGH                    0x0000021AL
+#define DREG_REGID_SRAR_LOW                     0x0000021BL
+#define DREG_REGID_DMA_STATE                    0x0000021CL
+#define DREG_REGID_CURRENT_DMA_STREAM           0x0000021DL
+#define DREG_REGID_NEXT_DMA_STREAM              0x0000021EL
+#define DREG_REGID_CPU_STATUS                   0x00000300L
+#define DREG_REGID_MAC_MODE                     0x00000301L
+#define DREG_REGID_STACK_AND_REPEAT             0x00000302L
+#define DREG_REGID_INDEX0                       0x00000304L
+#define DREG_REGID_INDEX1                       0x00000305L
+#define DREG_REGID_DMA_STATE_0_3                0x00000400L
+#define DREG_REGID_DMA_STATE_4_7                0x00000404L
+#define DREG_REGID_DMA_STATE_8_11               0x00000408L
+#define DREG_REGID_DMA_STATE_12_15              0x0000040CL
+#define DREG_REGID_DMA_STATE_16_19              0x00000410L
+#define DREG_REGID_DMA_STATE_20_23              0x00000414L
+#define DREG_REGID_DMA_STATE_24_27              0x00000418L
+#define DREG_REGID_DMA_STATE_28_31              0x0000041CL
+#define DREG_REGID_DMA_STATE_32_35              0x00000420L
+#define DREG_REGID_DMA_STATE_36_39              0x00000424L
+#define DREG_REGID_DMA_STATE_40_43              0x00000428L
+#define DREG_REGID_DMA_STATE_44_47              0x0000042CL
+#define DREG_REGID_DMA_STATE_48_51              0x00000430L
+#define DREG_REGID_DMA_STATE_52_55              0x00000434L
+#define DREG_REGID_DMA_STATE_56_59              0x00000438L
+#define DREG_REGID_DMA_STATE_60_63              0x0000043CL
+#define DREG_REGID_DMA_STATE_64_67              0x00000440L
+#define DREG_REGID_DMA_STATE_68_71              0x00000444L
+#define DREG_REGID_DMA_STATE_72_75              0x00000448L
+#define DREG_REGID_DMA_STATE_76_79              0x0000044CL
+#define DREG_REGID_DMA_STATE_80_83              0x00000450L
+#define DREG_REGID_DMA_STATE_84_87              0x00000454L
+#define DREG_REGID_DMA_STATE_88_91              0x00000458L
+#define DREG_REGID_DMA_STATE_92_95              0x0000045CL
+#define DREG_REGID_TRAP_SELECT                  0x00000500L
+#define DREG_REGID_TRAP_WRITE_0                 0x00000500L
+#define DREG_REGID_TRAP_WRITE_1                 0x00000501L
+#define DREG_REGID_TRAP_WRITE_2                 0x00000502L
+#define DREG_REGID_TRAP_WRITE_3                 0x00000503L
+#define DREG_REGID_TRAP_WRITE_4                 0x00000504L
+#define DREG_REGID_TRAP_WRITE_5                 0x00000505L
+#define DREG_REGID_TRAP_WRITE_6                 0x00000506L
+#define DREG_REGID_TRAP_WRITE_7                 0x00000507L
+#if !defined(NO_CS4612)
+#if !defined(NO_CS4615)
+#define DREG_REGID_TRAP_WRITE_8                 0x00000510L
+#define DREG_REGID_TRAP_WRITE_9                 0x00000511L
+#define DREG_REGID_TRAP_WRITE_10                0x00000512L
+#define DREG_REGID_TRAP_WRITE_11                0x00000513L
+#define DREG_REGID_TRAP_WRITE_12                0x00000514L
+#define DREG_REGID_TRAP_WRITE_13                0x00000515L
+#define DREG_REGID_TRAP_WRITE_14                0x00000516L
+#define DREG_REGID_TRAP_WRITE_15                0x00000517L
+#define DREG_REGID_TRAP_WRITE_16                0x00000518L
+#define DREG_REGID_TRAP_WRITE_17                0x00000519L
+#define DREG_REGID_TRAP_WRITE_18                0x0000051AL
+#define DREG_REGID_TRAP_WRITE_19                0x0000051BL
+#define DREG_REGID_TRAP_WRITE_20                0x0000051CL
+#define DREG_REGID_TRAP_WRITE_21                0x0000051DL
+#define DREG_REGID_TRAP_WRITE_22                0x0000051EL
+#define DREG_REGID_TRAP_WRITE_23                0x0000051FL
+#endif
+#endif
+#define DREG_REGID_MAC0_ACC0_LOW                0x00000600L
+#define DREG_REGID_MAC0_ACC1_LOW                0x00000601L
+#define DREG_REGID_MAC0_ACC2_LOW                0x00000602L
+#define DREG_REGID_MAC0_ACC3_LOW                0x00000603L
+#define DREG_REGID_MAC1_ACC0_LOW                0x00000604L
+#define DREG_REGID_MAC1_ACC1_LOW                0x00000605L
+#define DREG_REGID_MAC1_ACC2_LOW                0x00000606L
+#define DREG_REGID_MAC1_ACC3_LOW                0x00000607L
+#define DREG_REGID_MAC0_ACC0_MID                0x00000608L
+#define DREG_REGID_MAC0_ACC1_MID                0x00000609L
+#define DREG_REGID_MAC0_ACC2_MID                0x0000060AL
+#define DREG_REGID_MAC0_ACC3_MID                0x0000060BL
+#define DREG_REGID_MAC1_ACC0_MID                0x0000060CL
+#define DREG_REGID_MAC1_ACC1_MID                0x0000060DL
+#define DREG_REGID_MAC1_ACC2_MID                0x0000060EL
+#define DREG_REGID_MAC1_ACC3_MID                0x0000060FL
+#define DREG_REGID_MAC0_ACC0_HIGH               0x00000610L
+#define DREG_REGID_MAC0_ACC1_HIGH               0x00000611L
+#define DREG_REGID_MAC0_ACC2_HIGH               0x00000612L
+#define DREG_REGID_MAC0_ACC3_HIGH               0x00000613L
+#define DREG_REGID_MAC1_ACC0_HIGH               0x00000614L
+#define DREG_REGID_MAC1_ACC1_HIGH               0x00000615L
+#define DREG_REGID_MAC1_ACC2_HIGH               0x00000616L
+#define DREG_REGID_MAC1_ACC3_HIGH               0x00000617L
+#define DREG_REGID_RSHOUT_LOW                   0x00000620L
+#define DREG_REGID_RSHOUT_MID                   0x00000628L
+#define DREG_REGID_RSHOUT_HIGH                  0x00000630L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the DMA stream requestor write
+ * port register.
+ *
+ *****************************************************************************/
+#define DSRWP_DSR_MASK                          0x0000000FL
+#define DSRWP_DSR_BG_RQ                         0x00000001L
+#define DSRWP_DSR_PRIORITY_MASK                 0x00000006L
+#define DSRWP_DSR_PRIORITY_0                    0x00000000L
+#define DSRWP_DSR_PRIORITY_1                    0x00000002L
+#define DSRWP_DSR_PRIORITY_2                    0x00000004L
+#define DSRWP_DSR_PRIORITY_3                    0x00000006L
+#define DSRWP_DSR_RQ_PENDING                    0x00000008L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the trap write port register.
+ *
+ *****************************************************************************/
+#define TWPR_TW_MASK                            0x0000FFFFL
+#define TWPR_TW_SHIFT                           0L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the stack pointer write
+ * register.
+ *
+ *****************************************************************************/
+#define SPWR_STKP_MASK                          0x0000000FL
+#define SPWR_STKP_SHIFT                         0L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the SP interrupt register.
+ *
+ *****************************************************************************/
+#define SPIR_FRI                                0x00000001L
+#define SPIR_DOI                                0x00000002L
+#define SPIR_GPI2                               0x00000004L
+#define SPIR_GPI3                               0x00000008L
+#define SPIR_IP0                                0x00000010L
+#define SPIR_IP1                                0x00000020L
+#define SPIR_IP2                                0x00000040L
+#define SPIR_IP3                                0x00000080L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the functional group 1 register.
+ *
+ *****************************************************************************/
+#define FGR1_F1S_MASK                           0x0000FFFFL
+#define FGR1_F1S_SHIFT                          0L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the SP clock status register.
+ *
+ *****************************************************************************/
+#define SPCS_FRI                                0x00000001L
+#define SPCS_DOI                                0x00000002L
+#define SPCS_GPI2                               0x00000004L
+#define SPCS_GPI3                               0x00000008L
+#define SPCS_IP0                                0x00000010L
+#define SPCS_IP1                                0x00000020L
+#define SPCS_IP2                                0x00000040L
+#define SPCS_IP3                                0x00000080L
+#define SPCS_SPRUN                              0x00000100L
+#define SPCS_SLEEP                              0x00000200L
+#define SPCS_FG                                 0x00000400L
+#define SPCS_ORUN                               0x00000800L
+#define SPCS_IRQ                                0x00001000L
+#define SPCS_FGN_MASK                           0x0000E000L
+#define SPCS_FGN_SHIFT                          13L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the SP DMA requestor status
+ * register.
+ *
+ *****************************************************************************/
+#define SDSR_DCS_MASK                           0x000000FFL
+#define SDSR_DCS_SHIFT                          0L
+#define SDSR_DCS_NONE                           0x00000007L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the frame timer register.
+ *
+ *****************************************************************************/
+#define FRMT_FTV_MASK                           0x0000FFFFL
+#define FRMT_FTV_SHIFT                          0L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the frame timer current count
+ * register.
+ *
+ *****************************************************************************/
+#define FRCC_FCC_MASK                           0x0000FFFFL
+#define FRCC_FCC_SHIFT                          0L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the frame timer save count
+ * register.
+ *
+ *****************************************************************************/
+#define FRSC_FCS_MASK                           0x0000FFFFL
+#define FRSC_FCS_SHIFT                          0L
+
+/*****************************************************************************
+ *
+ * The following define the various flags stored in the scatter/gather
+ * descriptors.
+ *
+ *****************************************************************************/
+#define DMA_SG_NEXT_ENTRY_MASK                  0x00000FF8L
+#define DMA_SG_SAMPLE_END_MASK                  0x0FFF0000L
+#define DMA_SG_SAMPLE_END_FLAG                  0x10000000L
+#define DMA_SG_LOOP_END_FLAG                    0x20000000L
+#define DMA_SG_SIGNAL_END_FLAG                  0x40000000L
+#define DMA_SG_SIGNAL_PAGE_FLAG                 0x80000000L
+#define DMA_SG_NEXT_ENTRY_SHIFT                 3L
+#define DMA_SG_SAMPLE_END_SHIFT                 16L
+
+/*****************************************************************************
+ *
+ * The following define the offsets of the fields within the on-chip generic
+ * DMA requestor.
+ *
+ *****************************************************************************/
+#define DMA_RQ_CONTROL1                         0x00000000L
+#define DMA_RQ_CONTROL2                         0x00000004L
+#define DMA_RQ_SOURCE_ADDR                      0x00000008L
+#define DMA_RQ_DESTINATION_ADDR                 0x0000000CL
+#define DMA_RQ_NEXT_PAGE_ADDR                   0x00000010L
+#define DMA_RQ_NEXT_PAGE_SGDESC                 0x00000014L
+#define DMA_RQ_LOOP_START_ADDR                  0x00000018L
+#define DMA_RQ_POST_LOOP_ADDR                   0x0000001CL
+#define DMA_RQ_PAGE_MAP_ADDR                    0x00000020L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the first control word of the
+ * on-chip generic DMA requestor.
+ *
+ *****************************************************************************/
+#define DMA_RQ_C1_COUNT_MASK                    0x000003FFL
+#define DMA_RQ_C1_DESTINATION_SCATTER           0x00001000L
+#define DMA_RQ_C1_SOURCE_GATHER                 0x00002000L
+#define DMA_RQ_C1_DONE_FLAG                     0x00004000L
+#define DMA_RQ_C1_OPTIMIZE_STATE                0x00008000L
+#define DMA_RQ_C1_SAMPLE_END_STATE_MASK         0x00030000L
+#define DMA_RQ_C1_FULL_PAGE                     0x00000000L
+#define DMA_RQ_C1_BEFORE_SAMPLE_END             0x00010000L
+#define DMA_RQ_C1_PAGE_MAP_ERROR                0x00020000L
+#define DMA_RQ_C1_AT_SAMPLE_END                 0x00030000L
+#define DMA_RQ_C1_LOOP_END_STATE_MASK           0x000C0000L
+#define DMA_RQ_C1_NOT_LOOP_END                  0x00000000L
+#define DMA_RQ_C1_BEFORE_LOOP_END               0x00040000L
+#define DMA_RQ_C1_2PAGE_LOOP_BEGIN              0x00080000L
+#define DMA_RQ_C1_LOOP_BEGIN                    0x000C0000L
+#define DMA_RQ_C1_PAGE_MAP_MASK                 0x00300000L
+#define DMA_RQ_C1_PM_NONE_PENDING               0x00000000L
+#define DMA_RQ_C1_PM_NEXT_PENDING               0x00100000L
+#define DMA_RQ_C1_PM_RESERVED                   0x00200000L
+#define DMA_RQ_C1_PM_LOOP_NEXT_PENDING          0x00300000L
+#define DMA_RQ_C1_WRITEBACK_DEST_FLAG           0x00400000L
+#define DMA_RQ_C1_WRITEBACK_SRC_FLAG            0x00800000L
+#define DMA_RQ_C1_DEST_SIZE_MASK                0x07000000L
+#define DMA_RQ_C1_DEST_LINEAR                   0x00000000L
+#define DMA_RQ_C1_DEST_MOD16                    0x01000000L
+#define DMA_RQ_C1_DEST_MOD32                    0x02000000L
+#define DMA_RQ_C1_DEST_MOD64                    0x03000000L
+#define DMA_RQ_C1_DEST_MOD128                   0x04000000L
+#define DMA_RQ_C1_DEST_MOD256                   0x05000000L
+#define DMA_RQ_C1_DEST_MOD512                   0x06000000L
+#define DMA_RQ_C1_DEST_MOD1024                  0x07000000L
+#define DMA_RQ_C1_DEST_ON_HOST                  0x08000000L
+#define DMA_RQ_C1_SOURCE_SIZE_MASK              0x70000000L
+#define DMA_RQ_C1_SOURCE_LINEAR                 0x00000000L
+#define DMA_RQ_C1_SOURCE_MOD16                  0x10000000L
+#define DMA_RQ_C1_SOURCE_MOD32                  0x20000000L
+#define DMA_RQ_C1_SOURCE_MOD64                  0x30000000L
+#define DMA_RQ_C1_SOURCE_MOD128                 0x40000000L
+#define DMA_RQ_C1_SOURCE_MOD256                 0x50000000L
+#define DMA_RQ_C1_SOURCE_MOD512                 0x60000000L
+#define DMA_RQ_C1_SOURCE_MOD1024                0x70000000L
+#define DMA_RQ_C1_SOURCE_ON_HOST                0x80000000L
+#define DMA_RQ_C1_COUNT_SHIFT                   0L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the second control word of the
+ * on-chip generic DMA requestor.
+ *
+ *****************************************************************************/
+#define DMA_RQ_C2_VIRTUAL_CHANNEL_MASK          0x0000003FL
+#define DMA_RQ_C2_VIRTUAL_SIGNAL_MASK           0x00000300L
+#define DMA_RQ_C2_NO_VIRTUAL_SIGNAL             0x00000000L
+#define DMA_RQ_C2_SIGNAL_EVERY_DMA              0x00000100L
+#define DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG        0x00000200L
+#define DMA_RQ_C2_SIGNAL_DEST_PINGPONG          0x00000300L
+#define DMA_RQ_C2_AUDIO_CONVERT_MASK            0x0000F000L
+#define DMA_RQ_C2_AC_NONE                       0x00000000L
+#define DMA_RQ_C2_AC_8_TO_16_BIT                0x00001000L
+#define DMA_RQ_C2_AC_MONO_TO_STEREO             0x00002000L
+#define DMA_RQ_C2_AC_ENDIAN_CONVERT             0x00004000L
+#define DMA_RQ_C2_AC_SIGNED_CONVERT             0x00008000L
+#define DMA_RQ_C2_LOOP_END_MASK                 0x0FFF0000L
+#define DMA_RQ_C2_LOOP_MASK                     0x30000000L
+#define DMA_RQ_C2_NO_LOOP                       0x00000000L
+#define DMA_RQ_C2_ONE_PAGE_LOOP                 0x10000000L
+#define DMA_RQ_C2_TWO_PAGE_LOOP                 0x20000000L
+#define DMA_RQ_C2_MULTI_PAGE_LOOP               0x30000000L
+#define DMA_RQ_C2_SIGNAL_LOOP_BACK              0x40000000L
+#define DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE        0x80000000L
+#define DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT         0L
+#define DMA_RQ_C2_LOOP_END_SHIFT                16L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the source and destination words
+ * of the on-chip generic DMA requestor.
+ *
+ *****************************************************************************/
+#define DMA_RQ_SD_ADDRESS_MASK                  0x0000FFFFL
+#define DMA_RQ_SD_MEMORY_ID_MASK                0x000F0000L
+#define DMA_RQ_SD_SP_PARAM_ADDR                 0x00000000L
+#define DMA_RQ_SD_SP_SAMPLE_ADDR                0x00010000L
+#define DMA_RQ_SD_SP_PROGRAM_ADDR               0x00020000L
+#define DMA_RQ_SD_SP_DEBUG_ADDR                 0x00030000L
+#define DMA_RQ_SD_OMNIMEM_ADDR                  0x000E0000L
+#define DMA_RQ_SD_END_FLAG                      0x40000000L
+#define DMA_RQ_SD_ERROR_FLAG                    0x80000000L
+#define DMA_RQ_SD_ADDRESS_SHIFT                 0L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the page map address word of the
+ * on-chip generic DMA requestor.
+ *
+ *****************************************************************************/
+#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK   0x00000FF8L
+#define DMA_RQ_PMA_PAGE_TABLE_MASK              0xFFFFF000L
+#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT  3L
+#define DMA_RQ_PMA_PAGE_TABLE_SHIFT             12L
+
+/*****************************************************************************
+ *
+ * The following defines are for the flags in the rsConfig01/23 registers of
+ * the SP.
+ *
+ *****************************************************************************/
+#define RSCONFIG_MODULO_SIZE_MASK               0x0000000FL
+#define RSCONFIG_MODULO_16                      0x00000001L
+#define RSCONFIG_MODULO_32                      0x00000002L
+#define RSCONFIG_MODULO_64                      0x00000003L
+#define RSCONFIG_MODULO_128                     0x00000004L
+#define RSCONFIG_MODULO_256                     0x00000005L
+#define RSCONFIG_MODULO_512                     0x00000006L
+#define RSCONFIG_MODULO_1024                    0x00000007L
+#define RSCONFIG_MODULO_4                       0x00000008L
+#define RSCONFIG_MODULO_8                       0x00000009L
+#define RSCONFIG_SAMPLE_SIZE_MASK               0x000000C0L
+#define RSCONFIG_SAMPLE_8MONO                   0x00000000L
+#define RSCONFIG_SAMPLE_8STEREO                 0x00000040L
+#define RSCONFIG_SAMPLE_16MONO                  0x00000080L
+#define RSCONFIG_SAMPLE_16STEREO                0x000000C0L
+#define RSCONFIG_UNDERRUN_ZERO                  0x00004000L
+#define RSCONFIG_DMA_TO_HOST                    0x00008000L
+#define RSCONFIG_STREAM_NUM_MASK                0x00FF0000L
+#define RSCONFIG_MAX_DMA_SIZE_MASK              0x1F000000L
+#define RSCONFIG_DMA_ENABLE                     0x20000000L
+#define RSCONFIG_PRIORITY_MASK                  0xC0000000L
+#define RSCONFIG_PRIORITY_HIGH                  0x00000000L
+#define RSCONFIG_PRIORITY_MEDIUM_HIGH           0x40000000L
+#define RSCONFIG_PRIORITY_MEDIUM_LOW            0x80000000L
+#define RSCONFIG_PRIORITY_LOW                   0xC0000000L
+#define RSCONFIG_STREAM_NUM_SHIFT               16L
+#define RSCONFIG_MAX_DMA_SIZE_SHIFT             24L
+
+#define BA1_VARIDEC_BUF_1       0x000
+
+#define BA1_PDTC                0x0c0    /* BA1_PLAY_DMA_TRANSACTION_COUNT_REG */
+#define BA1_PFIE                0x0c4    /* BA1_PLAY_FORMAT_&_INTERRUPT_ENABLE_REG */
+#define BA1_PBA                 0x0c8    /* BA1_PLAY_BUFFER_ADDRESS */
+#define BA1_PVOL                0x0f8    /* BA1_PLAY_VOLUME_REG */
+#define BA1_PSRC                0x288    /* BA1_PLAY_SAMPLE_RATE_CORRECTION_REG */
+#define BA1_PCTL                0x2a4    /* BA1_PLAY_CONTROL_REG */
+#define BA1_PPI                 0x2b4    /* BA1_PLAY_PHASE_INCREMENT_REG */
+
+#define BA1_CCTL                0x064    /* BA1_CAPTURE_CONTROL_REG */
+#define BA1_CIE                 0x104    /* BA1_CAPTURE_INTERRUPT_ENABLE_REG */
+#define BA1_CBA                 0x10c    /* BA1_CAPTURE_BUFFER_ADDRESS */
+#define BA1_CSRC                0x2c8    /* BA1_CAPTURE_SAMPLE_RATE_CORRECTION_REG */
+#define BA1_CCI                 0x2d8    /* BA1_CAPTURE_COEFFICIENT_INCREMENT_REG */
+#define BA1_CD                  0x2e0    /* BA1_CAPTURE_DELAY_REG */
+#define BA1_CPI                 0x2f4    /* BA1_CAPTURE_PHASE_INCREMENT_REG */
+#define BA1_CVOL                0x2f8    /* BA1_CAPTURE_VOLUME_REG */
+
+#define BA1_CFG1                0x134    /* BA1_CAPTURE_FRAME_GROUP_1_REG */
+#define BA1_CFG2                0x138    /* BA1_CAPTURE_FRAME_GROUP_2_REG */
+#define BA1_CCST                0x13c    /* BA1_CAPTURE_CONSTANT_REG */
+#define BA1_CSPB                0x340    /* BA1_CAPTURE_SPB_ADDRESS */
+
+/* The following struct holds the initialization array. */
+
+/*
+ * this is 3*1024 for parameter, 3.5*1024 for sample and 2*3.5*1024 for code since 
+ * each instruction is 40 bits and takes two dwords 
+ */
+#define INKY_BA1_DWORD_SIZE (13 * 1024 + 512)
+#define INKY_MEMORY_COUNT 3
+
+struct BA1struct 
+{
+	struct
+	{
+		u_long ulDestByteOffset,
+		    ulSourceByteSize;
+	} MemoryStat[INKY_MEMORY_COUNT];
+
+	u_long BA1Array[INKY_BA1_DWORD_SIZE];
+};
+
+#endif /* _CSA_REG_H */
diff --git a/sys/dev/sound/pci/csavar.h b/sys/dev/sound/pci/csavar.h
new file mode 100644
index 0000000..0f3d4f9
--- /dev/null
+++ b/sys/dev/sound/pci/csavar.h
@@ -0,0 +1,52 @@
+/*-
+ * Copyright (c) 1999 Seigo Tanimura
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _CSA_VAR_H
+#define _CSA_VAR_H
+
+/* Resources. */
+struct csa_res {
+	int io_rid; /* io rid */
+	struct resource *io; /* io */
+	int mem_rid; /* memory rid */
+	struct resource *mem; /* memory */
+	int irq_rid; /* irq rid */
+	struct resource *irq; /* irq */
+};
+typedef struct csa_res csa_res;
+
+/* Common functions for csa. */
+int csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data);
+int csa_writecodec(csa_res *resp, u_long offset, u_int32_t data);
+
+u_int32_t csa_readio(csa_res *resp, u_long offset);
+void csa_writeio(csa_res *resp, u_long offset, u_int32_t data);
+u_int32_t csa_readmem(csa_res *resp, u_long offset);
+void csa_writemem(csa_res *resp, u_long offset, u_int32_t data);
+
+#endif /* _CSA_VAR_H */