mss and sb drivers updated for newpcm

Reviewed by:	peter, dfr

1 files changed, 180 insertions, 45 deletions

diff --git a/sys/dev/sound/isa/mss.h b/sys/dev/sound/isa/mss.h
index 20ceaaf..ab41964 100644
--- a/sys/dev/sound/isa/mss.h
+++ b/sys/dev/sound/isa/mss.h
@@ -28,9 +28,9 @@ ahead.
  *
  */
 
-#define io_Index_Addr(d)        ((d)->io_base + 4)
-#define	IA_BUSY			0x80	/* readonly, set when busy */
-#define	IA_MCE			0x40	/* the MCE bit. */
+#define MSS_INDEX        (0 + 4)
+#define	MSS_IDXBUSY		0x80	/* readonly, set when busy */
+#define	MSS_MCE			0x40	/* the MCE bit. */
 	/*
 	 * the MCE bit must be set whenever the current mode of the
 	 * codec is changed; this in particular is true for the
@@ -38,15 +38,15 @@ ahead.
 	 * Only exception are CEN and PEN which can be changed on the fly.
 	 * The DAC output is muted when MCE is set.
 	 */
-#define	IA_TRD			0x20	/* Transfer request disable */
+#define	MSS_TRD			0x20	/* Transfer request disable */
 	/*
 	 * When TRD is set, DMA transfers cease when the INT bit in
 	 * the MSS status reg is set. Must be cleared for automode
 	 * DMA, set otherwise.
 	 */
-#define	IA_AMASK		0x1f	/* mask for indirect address */
+#define	MSS_IDXMASK		0x1f	/* mask for indirect address */
 
-#define io_Indexed_Data(d)      ((d)->io_base+1+4)
+#define MSS_IDATA  	(1 + 4)
 	/*
 	 * data to be transferred to the indirect register addressed
 	 * by index addr. During init and sw. powerdown, cannot be
@@ -54,7 +54,7 @@ ahead.
 	 * busy flag).
 	 */
 
-#define io_Status(d)            ((d)->io_base+2+4)
+#define MSS_STATUS      (2 + 4)
 
 #define	IS_CUL		0x80	/* capture upper/lower */
 #define	IS_CLR		0x40	/* capture left/right */
@@ -67,11 +67,12 @@ ahead.
 	/*
 	 * IS_INT is clreared by any write to the status register.
 	 */
-	
+#if 0
 #define io_Polled_IO(d)         ((d)->io_base+3+4)
 	/*
 	 * this register is used in case of polled i/o
 	 */
+#endif
 
 /*
  * The MSS has a set of 16 (or 32 depending on the model) indirect
@@ -104,18 +105,22 @@ ahead.
 #define	BD_F_MCE_BIT	0x0001
 #define	BD_F_IRQ_OK	0x0002
 #define	BD_F_TMR_RUN	0x0004
+#define BD_F_MSS_OFFSET 0x0008	/* offset mss writes by -4 */
+#define BD_F_DUPLEX	0x0010
 
 /* AD1816 register macros */
 
-#define ad1816_ale(d)  ((d)->io_base+0) /* indirect reg access */
-#define ad1816_int(d)  ((d)->io_base+1) /* interupt status     */
-#define ad1816_low(d)  ((d)->io_base+2) /* indirect low byte   */
-#define ad1816_high(d) ((d)->io_base+3) /* indirect high byte  */
-/* unused */
-#define ad1816_pioD(d) ((d)->io_base+4) /* PIO debug           */
-#define ad1816_pios(d) ((d)->io_base+5) /* PIO status          */
-#define ad1816_piod(d) ((d)->io_base+6) /* PIO data            */
-/* end of unused */
+#define AD1816_ALE	0 	/* indirect reg access 		*/
+#define AD1816_INT	1 	/* interupt status     		*/
+#define AD1816_LOW	2 	/* indirect low byte   		*/
+#define AD1816_HIGH	3 	/* indirect high byte  		*/
+
+#if 0
+#define ad1816_pioD(d) ((d)->io_base+4) /* PIO debug		*/
+#define ad1816_pios(d) ((d)->io_base+5) /* PIO status		*/
+#define ad1816_piod(d) ((d)->io_base+6) /* PIO data 		*/
+#endif
+
 /* values for playback/capture config:
    bits: 0   enable/disable
          1   pio/dma
@@ -127,19 +132,22 @@ ahead.
                       01 8bit  alaw   (comp)
                       11 16bit be     (uncomp)
 */
-#define ad1816_play(d) ((d)->io_base+8) /* playback config     */
-#define ad1816_capt(d) ((d)->io_base+9) /* capture config      */
+
+#define AD1816_PLAY	8 	/* playback config     		*/
+#define AD1816_CAPT 	9	/* capture config      		*/
 
 #define	AD1816_BUSY	0x80	/* chip is busy			*/
 #define	AD1816_ALEMASK	0x3F	/* mask for indirect adr.	*/
-/* unusud */
+
+#if 0
 #define	AD1816_INTRSI	0x01	/* sb intr			*/
 #define	AD1816_INTRGI	0x02	/* game intr			*/
 #define	AD1816_INTRRI	0x04	/* ring intr			*/
 #define	AD1816_INTRDI	0x08	/* dsp intr			*/
 #define	AD1816_INTRVI	0x10	/* vol intr			*/
 #define	AD1816_INTRTI	0x20 	/* timer intr			*/
-/* used again */
+#endif
+
 #define	AD1816_INTRCI	0x40	/* capture intr			*/
 #define	AD1816_INTRPI	0x80	/* playback intr		*/
 /* PIO stuff is not supplied here */
@@ -155,13 +163,16 @@ ahead.
 #define	AD1816_S16BE	0x30	/* 16 bit linear big endian	*/
 #define	AD1816_FORMASK  0x38	/* format mask			*/
 
+
+
+
 /*
  * sound/ad1848_mixer.h
- * 
+ *
  * Definitions for the mixer of AD1848 and compatible codecs.
- * 
+ *
  * Copyright by Hannu Savolainen 1994
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
  * met: 1. Redistributions of source code must retain the above copyright
@@ -169,7 +180,7 @@ ahead.
  * Redistributions in binary form must reproduce the above copyright notice,
  * this list of conditions and the following disclaimer in the documentation
  * and/or other materials provided with the distribution.
- * 
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -281,24 +292,148 @@ MIX_NONE(SOUND_MIXER_LINE3),
     (SOUND_MASK_VOLUME | SOUND_MASK_PCM | SOUND_MASK_SYNTH | \
      SOUND_MASK_LINE   | SOUND_MASK_MIC | SOUND_MASK_CD | SOUND_MASK_IGAIN)
 
-static u_short default_mixer_levels[SOUND_MIXER_NRDEVICES] = {
-  0x5a5a,			/* Master Volume */
-  0x3232,			/* Bass */
-  0x3232,			/* Treble */
-  0x4b4b,			/* FM */
-  0x4040,			/* PCM */
-  0x4b4b,			/* PC Speaker */
-  0x2020,			/* Ext Line */
-  0x4040,			/* Mic */
-  0x4b4b,			/* CD */
-  0x0000,			/* Recording monitor */
-  0x4b4b,			/* SB PCM */
-  0x4b4b,			/* Recording level */
-  0x2525,			/* Input gain */
-  0x0000,			/* Output gain */
-  /*  0x4040,			Line1 */
-  0x0000,			/* Line1 */
-  0x0000,			/* Line2 */
-  0x1515			/* Line3 (usually line in)*/
-};
+/*-
+ * Copyright (c) 1999 Doug Rabson
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	$Id$
+ */
+
+/*
+ * Register definitions for the Yamaha OPL3-SA[23x].
+ */
+#define OPL3SAx_POWER	0x01		/* Power Management (R/W) */
+#define OPL3SAx_POWER_PDX	0x01	/* Set to 1 to halt oscillator */
+#define OPL3SAx_POWER_PDN	0x02	/* Set to 1 to power down */
+#define OPL3SAx_POWER_PSV	0x04	/* Set to 1 to power save */
+#define OPL3SAx_POWER_ADOWN	0x20	/* Analog power (?) */
+
+#define OPL3SAx_SYSTEM	0x02		/* System control (R/W) */
+#define OPL3SAx_SYSTEM_VZE	0x01	/* I2S audio routing */
+#define OPL3SAx_SYSTEM_IDSEL	0x03	/* SB compat version select */
+#define OPL3SAx_SYSTEM_SBHE	0x80	/* 0 for AT bus, 1 for XT bus */
+
+#define OPL3SAx_IRQCONF	0x03		/* Interrupt configuration (R/W */
+#define OPL3SAx_IRQCONF_WSSA	0x01	/* WSS interrupts through IRQA */
+#define OPL3SAx_IRQCONF_SBA	0x02	/* WSS interrupts through IRQA */
+#define OPL3SAx_IRQCONF_MPUA	0x04	/* WSS interrupts through IRQA */
+#define OPL3SAx_IRQCONF_OPL3A	0x08	/* WSS interrupts through IRQA */
+#define OPL3SAx_IRQCONF_WSSB	0x10	/* WSS interrupts through IRQB */
+#define OPL3SAx_IRQCONF_SBB	0x20	/* WSS interrupts through IRQB */
+#define OPL3SAx_IRQCONF_MPUB	0x40	/* WSS interrupts through IRQB */
+#define OPL3SAx_IRQCONF_OPL3B	0x80	/* WSS interrupts through IRQB */
+
+#define OPL3SAx_IRQSTATUSA 0x04		/* Interrupt (IRQ-A) Status (RO) */
+#define OPL3SAx_IRQSTATUSB 0x05		/* Interrupt (IRQ-B) Status (RO) */
+#define OPL3SAx_IRQSTATUS_PI	0x01	/* Playback Flag of CODEC */
+#define OPL3SAx_IRQSTATUS_CI	0x02	/* Recording Flag of CODEC */
+#define OPL3SAx_IRQSTATUS_TI	0x04	/* Timer Flag of CODEC */
+#define OPL3SAx_IRQSTATUS_SB	0x08	/* SB compat Playback Interrupt Flag */
+#define OPL3SAx_IRQSTATUS_MPU	0x10	/* MPU401 Interrupt Flag */
+#define OPL3SAx_IRQSTATUS_OPL3	0x20	/* Internal FM Timer Flag */
+#define OPL3SAx_IRQSTATUS_MV	0x40	/* HW Volume Interrupt Flag */
+#define OPL3SAx_IRQSTATUS_PI	0x01	/* Playback Flag of CODEC */
+#define OPL3SAx_IRQSTATUS_CI	0x02	/* Recording Flag of CODEC */
+#define OPL3SAx_IRQSTATUS_TI	0x04	/* Timer Flag of CODEC */
+#define OPL3SAx_IRQSTATUS_SB	0x08	/* SB compat Playback Interrupt Flag */
+#define OPL3SAx_IRQSTATUS_MPU	0x10	/* MPU401 Interrupt Flag */
+#define OPL3SAx_IRQSTATUS_OPL3	0x20	/* Internal FM Timer Flag */
+#define OPL3SAx_IRQSTATUS_MV	0x40	/* HW Volume Interrupt Flag */
+
+#define OPL3SAx_DMACONF	0x06		/* DMA configuration (R/W) */
+#define OPL3SAx_DMACONF_WSSPA	0x01	/* WSS Playback on DMA-A */
+#define OPL3SAx_DMACONF_WSSRA	0x02	/* WSS Recording on DMA-A */
+#define OPL3SAx_DMACONF_SBA	0x02	/* SB Playback on DMA-A */
+#define OPL3SAx_DMACONF_WSSPB	0x10	/* WSS Playback on DMA-A */
+#define OPL3SAx_DMACONF_WSSRB	0x20	/* WSS Recording on DMA-A */
+#define OPL3SAx_DMACONF_SBB	0x20	/* SB Playback on DMA-A */
+
+#define OPL3SAx_VOLUMEL	0x07		/* Master Volume Left (R/W) */
+#define OPL3SAx_VOLUMEL_MVL	0x0f	/* Attenuation level */
+#define OPL3SAx_VOLUMEL_MVLM	0x80	/* Mute */
+
+#define OPL3SAx_VOLUMER	0x08		/* Master Volume Right (R/W) */
+#define OPL3SAx_VOLUMER_MVR	0x0f	/* Attenuation level */
+#define OPL3SAx_VOLUMER_MVRM	0x80	/* Mute */
+
+#define OPL3SAx_MIC	0x09		/* MIC Volume (R/W) */
+#define OPL3SAx_VOLUMER_MCV	0x1f	/* Attenuation level */
+#define OPL3SAx_VOLUMER_MICM	0x80	/* Mute */
+
+#define OPL3SAx_MISC	0x0a		/* Miscellaneous */
+#define OPL3SAx_MISC_VER	0x07	/* Version */
+#define OPL3SAx_MISC_MODE	0x08	/* SB or WSS mode */
+#define OPL3SAx_MISC_MCSW	0x10	/*  */
+#define OPL3SAx_MISC_VEN	0x80	/* Enable hardware volume control */
+
+#define OPL3SAx_WSSDMA	0x0b		/* WSS DMA Counter (RW) (4 regs) */
+
+#define OPL3SAx_WSSIRQSCAN 0x0f		/* WSS Interrupt Scan out/in (R/W) */
+#define OPL3SAx_WSSIRQSCAN_SPI	0x01
+#define OPL3SAx_WSSIRQSCAN_SCI	0x02
+#define OPL3SAx_WSSIRQSCAN_STI	0x04
+
+#define OPL3SAx_SBSTATE	0x10		/* SB compat Internal State (R/W) */
+#define OPL3SAx_SBSTATE_SBPDR	0x01	/* SB Power Down Request */
+#define OPL3SAx_SBSTATE_SE	0x02	/* Scan Enable */
+#define OPL3SAx_SBSTATE_SM	0x04	/* Scan Mode */
+#define OPL3SAx_SBSTATE_SS	0x08	/* Scan Select */
+#define OPL3SAx_SBSTATE_SBPDA	0x80	/* SB Power Down Acknowledge */
+
+#define OPL3SAx_SBDATA 0x11		/* SB compat State Scan Data (R/W) */
+
+#define OPL3SAx_DIGITALPOWER 0x12	/* Digital Partial Power Down (R/W) */
+#define OPL3SAx_DIGITALPOWER_PnP  0x01
+#define OPL3SAx_DIGITALPOWER_SB	  0x02
+#define OPL3SAx_DIGITALPOWER_WSSP 0x04
+#define OPL3SAx_DIGITALPOWER_WSSR 0x08
+#define OPL3SAx_DIGITALPOWER_FM	  0x10
+#define OPL3SAx_DIGITALPOWER_MCLK0 0x20
+#define OPL3SAx_DIGITALPOWER_MPU  0x40
+#define OPL3SAx_DIGITALPOWER_JOY  0x80
+
+#define OPL3SAx_ANALOGPOWER 0x13	/* Analog Partial Power Down (R/W) */
+#define OPL3SAx_ANALOGPOWER_WIDE  0x01
+#define OPL3SAx_ANALOGPOWER_SBDAC 0x02
+#define OPL3SAx_ANALOGPOWER_DA    0x04
+#define OPL3SAx_ANALOGPOWER_AD    0x08
+#define OPL3SAx_ANALOGPOWER_FMDAC 0x10
+
+#define OPL3SAx_WIDE	0x14		/* Enhanced control(WIDE) (R/W) */
+#define OPL3SAx_WIDE_WIDEL	0x07	/* Wide level on Left Channel */
+#define OPL3SAx_WIDE_WIDER	0x70	/* Wide level on Right Channel */
+
+#define OPL3SAx_BASS	0x15		/* Enhanced control(BASS) (R/W) */
+#define OPL3SAx_BASS_BASSL	0x07	/* Bass level on Left Channel */
+#define OPL3SAx_BASS_BASSR	0x70	/* Bass level on Right Channel */
+
+#define OPL3SAx_TREBLE	0x16		/* Enhanced control(TREBLE) (R/W) */
+#define OPL3SAx_TREBLE_TREBLEL	0x07	/* Treble level on Left Channel */
+#define OPL3SAx_TREBLE_TREBLER	0x70	/* Treble level on Right Channel */
+
+#define OPL3SAx_HWVOL	0x17		/* HW Volume IRQ Configuration (R/W) */
+#define OPL3SAx_HWVOL_IRQA	0x10	/* HW Volume IRQ on IRQ-A */
+#define OPL3SAx_HWVOL_IRQB	0x20	/* HW Volume IRQ on IRQ-B */
+