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authordillon <dillon@FreeBSD.org>2001-12-23 02:48:25 +0000
committerdillon <dillon@FreeBSD.org>2001-12-23 02:48:25 +0000
commit1fc3d5eabbb36f21ac98f6aff037c9a84f547d7e (patch)
treeb7ce1fca595cfa5c7c6a759f261fdd9a3feab1af /sys/dev/sio/sio.c
parent811c978c99001d53cb81f6ef8fed461a0e352498 (diff)
downloadFreeBSD-src-1fc3d5eabbb36f21ac98f6aff037c9a84f547d7e.zip
FreeBSD-src-1fc3d5eabbb36f21ac98f6aff037c9a84f547d7e.tar.gz
Back out an inappropriate backout. If Anyone wants to set the FIFO
level that high they should first fix the problems with the system that cause silo overflows. It is far more important for the serial device to work.
Diffstat (limited to 'sys/dev/sio/sio.c')
-rw-r--r--sys/dev/sio/sio.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/sys/dev/sio/sio.c b/sys/dev/sio/sio.c
index 59bcdad..2ba205b 100644
--- a/sys/dev/sio/sio.c
+++ b/sys/dev/sio/sio.c
@@ -2161,9 +2161,14 @@ comparam(tp, t)
* latencies are reasonable for humans. Serial comms
* protocols shouldn't expect anything better since modem
* latencies are larger.
+ *
+ * The fifo trigger level cannot be set at RX_HIGH for high
+ * speed connections without further work on reducing
+ * interrupt disablement times in other parts of the system,
+ * without producing silo overflow errors.
*/
com->fifo_image = t->c_ospeed <= 4800
- ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH;
+ ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDHI;
#ifdef COM_ESP
/*
* The Hayes ESP card needs the fifo DMA mode bit set
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