o uses bus accessor macros to read values from ivar so no more values

  are referenced directly from ivar pointer.  It's to do like what other
  buses do. [1]
o changes exported prototypes.  It doesn't use struct siba_* structures
  anymore that instead of it it uses only device_t.
o removes duplicate code and debug messages.
o style(9)

Pointed out by:	imp [1]

3 files changed, 846 insertions, 120 deletions

diff --git a/sys/dev/siba/siba_bwn.c b/sys/dev/siba/siba_bwn.c
index f33f9b3..56e16fd 100644
--- a/sys/dev/siba/siba_bwn.c
+++ b/sys/dev/siba/siba_bwn.c
@@ -152,6 +152,7 @@ siba_bwn_attach(device_t dev)
 	siba->siba_pci_vid = pci_get_vendor(dev);
 	siba->siba_pci_subvid = pci_get_subvendor(dev);
 	siba->siba_pci_subdid = pci_get_subdevice(dev);
+	siba->siba_pci_revid = pci_get_revid(dev);
 
 	return (siba_core_attach(siba));
 }
@@ -321,6 +322,71 @@ siba_bwn_msi_count(device_t dev, device_t child)
 	return (pci_msi_count(dev));
 }
 
+static int
+siba_bwn_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
+{
+	struct siba_dev_softc *sd;
+	struct siba_softc *siba;;
+
+	sd = device_get_ivars(child);
+	siba = sd->sd_bus;
+
+	switch (which) {
+	case SIBA_IVAR_VENDOR:
+		*result = sd->sd_id.sd_vendor;
+		break;
+	case SIBA_IVAR_DEVICE:
+		*result = sd->sd_id.sd_device;
+		break;
+	case SIBA_IVAR_REVID:
+		*result = sd->sd_id.sd_rev;
+		break;
+	case SIBA_IVAR_PCI_VENDOR:
+		*result = siba->siba_pci_vid;
+		break;
+	case SIBA_IVAR_PCI_DEVICE:
+		*result = siba->siba_pci_did;
+		break;
+	case SIBA_IVAR_PCI_SUBVENDOR:
+		*result = siba->siba_pci_subvid;
+		break;
+	case SIBA_IVAR_PCI_SUBDEVICE:
+		*result = siba->siba_pci_subdid;
+		break;
+	case SIBA_IVAR_PCI_REVID:
+		*result = siba->siba_pci_revid;
+		break;
+	case SIBA_IVAR_CHIPID:
+		*result = siba->siba_chipid;
+		break;
+	case SIBA_IVAR_CHIPREV:
+		*result = siba->siba_chiprev;
+		break;
+	case SIBA_IVAR_CHIPPKG:
+		*result = siba->siba_chippkg;
+		break;
+	case SIBA_IVAR_TYPE:
+		*result = siba->siba_type;
+		break;
+	case SIBA_IVAR_CC_PMUFREQ:
+		*result = siba->siba_cc.scc_pmu.freq;
+		break;
+	case SIBA_IVAR_CC_CAPS:
+		*result = siba->siba_cc.scc_caps;
+		break;
+	case SIBA_IVAR_CC_POWERDELAY:
+		*result = siba->siba_cc.scc_powerup_delay;
+		break;
+	case SIBA_IVAR_PCICORE_REVID:
+		*result = siba->siba_pci.spc_dev->sd_id.sd_rev;
+		break;
+	default:
+		return (ENOENT);
+	}
+
+	return (0);
+}
+
 static device_method_t siba_bwn_methods[] = {
 	/* Device interface */
 	DEVMETHOD(device_probe,		siba_bwn_probe),
@@ -333,6 +399,7 @@ static device_method_t siba_bwn_methods[] = {
 	/* Bus interface */
 	DEVMETHOD(bus_alloc_resource,   siba_bwn_alloc_resource),
 	DEVMETHOD(bus_release_resource, siba_bwn_release_resource),
+	DEVMETHOD(bus_read_ivar,	siba_bwn_read_ivar),
 	DEVMETHOD(bus_setup_intr,       siba_bwn_setup_intr),
 	DEVMETHOD(bus_teardown_intr,    siba_bwn_teardown_intr),
 
diff --git a/sys/dev/siba/siba_core.c b/sys/dev/siba/siba_core.c
index 748b426..44eaef5 100644
--- a/sys/dev/siba/siba_core.c
+++ b/sys/dev/siba/siba_core.c
@@ -133,6 +133,13 @@ static void	siba_pci_write_multi_4(struct siba_dev_softc *, const void *,
 		    size_t, uint16_t);
 static const char *siba_core_name(uint16_t);
 static void	siba_pcicore_init(struct siba_pci *);
+static uint32_t	siba_read_4_sub(struct siba_dev_softc *, uint16_t);
+static void	siba_write_4_sub(struct siba_dev_softc *, uint16_t, uint32_t);
+static void	siba_powerup_sub(struct siba_softc *, int);
+static int	siba_powerdown_sub(struct siba_softc *);
+static int	siba_dev_isup_sub(struct siba_dev_softc *);
+static void	siba_dev_up_sub(struct siba_dev_softc *, uint32_t);
+static void	siba_dev_down_sub(struct siba_dev_softc *, uint32_t);
 int		siba_core_attach(struct siba_softc *);
 int		siba_core_detach(struct siba_softc *);
 int		siba_core_suspend(struct siba_softc *);
@@ -181,7 +188,7 @@ siba_core_attach(struct siba_softc *siba)
 
 	/* XXX init PCI or PCMCIA host devices */
 
-	siba_powerup(siba, 0);
+	siba_powerup_sub(siba, 0);
 
 	/* init ChipCommon */
 	scc = &siba->siba_cc;
@@ -192,21 +199,15 @@ siba_core_attach(struct siba_softc *siba)
 		siba_cc_powerup_delay(scc);
 	}
 
-	/* fetch various internal informations for PCI */
-	siba->siba_board_vendor = pci_read_config(siba->siba_dev,
-	    PCIR_SUBVEND_0, 2);
-	siba->siba_board_type = pci_read_config(siba->siba_dev, PCIR_SUBDEV_0,
-	    2);
-	siba->siba_board_rev = pci_read_config(siba->siba_dev, PCIR_REVID, 2);
 	error = siba_pci_sprom(siba, &siba->siba_sprom);
 	if (error) {
-		siba_powerdown(siba);
+		siba_powerdown_sub(siba);
 		return (error);
 	}
 
 	siba_pcicore_init(&siba->siba_pci);
-	siba_powerdown(siba);
-	
+	siba_powerdown_sub(siba);
+
 	return (bus_generic_attach(siba->siba_dev));
 }
 
@@ -746,7 +747,16 @@ siba_pci_write_multi_4(struct siba_dev_softc *sd, const void *buffer,
 }
 
 void
-siba_powerup(struct siba_softc *siba, int dynamic)
+siba_powerup(device_t dev, int dynamic)
+{
+	struct siba_dev_softc *sd = device_get_ivars(dev);
+	struct siba_softc *siba = sd->sd_bus;
+
+	siba_powerup_sub(siba, dynamic);
+}
+
+static void
+siba_powerup_sub(struct siba_softc *siba, int dynamic)
 {
 
 	siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 1);
@@ -802,77 +812,101 @@ siba_cc_clock(struct siba_cc *scc, enum siba_clock clock)
 }
 
 uint16_t
-siba_read_2(struct siba_dev_softc *sd, uint16_t offset)
+siba_read_2(device_t dev, uint16_t offset)
 {
+	struct siba_dev_softc *sd = device_get_ivars(dev);
 
 	return (sd->sd_ops->read_2(sd, offset));
 }
 
 uint32_t
-siba_read_4(struct siba_dev_softc *sd, uint16_t offset)
+siba_read_4(device_t dev, uint16_t offset)
+{
+	struct siba_dev_softc *sd = device_get_ivars(dev);
+
+	return (siba_read_4_sub(sd, offset));
+}
+
+static uint32_t
+siba_read_4_sub(struct siba_dev_softc *sd, uint16_t offset)
 {
 
 	return (sd->sd_ops->read_4(sd, offset));
 }
 
 void
-siba_write_2(struct siba_dev_softc *sd, uint16_t offset, uint16_t value)
+siba_write_2(device_t dev, uint16_t offset, uint16_t value)
 {
+	struct siba_dev_softc *sd = device_get_ivars(dev);
 
 	sd->sd_ops->write_2(sd, offset, value);
 }
 
 void
-siba_write_4(struct siba_dev_softc *sd, uint16_t offset, uint32_t value)
+siba_write_4(device_t dev, uint16_t offset, uint32_t value)
+{
+	struct siba_dev_softc *sd = device_get_ivars(dev);
+
+	return (siba_write_4_sub(sd, offset, value));
+}
+
+static void
+siba_write_4_sub(struct siba_dev_softc *sd, uint16_t offset, uint32_t value)
 {
 
 	sd->sd_ops->write_4(sd, offset, value);
 }
 
 void
-siba_read_multi_1(struct siba_dev_softc *sd, void *buffer, size_t count,
+siba_read_multi_1(device_t dev, void *buffer, size_t count,
     uint16_t offset)
 {
+	struct siba_dev_softc *sd = device_get_ivars(dev);
 
 	sd->sd_ops->read_multi_1(sd, buffer, count, offset);
 }
 
 void
-siba_read_multi_2(struct siba_dev_softc *sd, void *buffer, size_t count,
+siba_read_multi_2(device_t dev, void *buffer, size_t count,
     uint16_t offset)
 {
+	struct siba_dev_softc *sd = device_get_ivars(dev);
 
 	sd->sd_ops->read_multi_2(sd, buffer, count, offset);
 }
 
 void
-siba_read_multi_4(struct siba_dev_softc *sd, void *buffer, size_t count,
+siba_read_multi_4(device_t dev, void *buffer, size_t count,
     uint16_t offset)
 {
+	struct siba_dev_softc *sd = device_get_ivars(dev);
 
 	sd->sd_ops->read_multi_4(sd, buffer, count, offset);
 }
 
 void
-siba_write_multi_1(struct siba_dev_softc *sd, const void *buffer,
-    size_t count, uint16_t offset)
+siba_write_multi_1(device_t dev, const void *buffer, size_t count,
+    uint16_t offset)
 {
+	struct siba_dev_softc *sd = device_get_ivars(dev);
 
 	sd->sd_ops->write_multi_1(sd, buffer, count, offset);
 }
 
 void
-siba_write_multi_2(struct siba_dev_softc *sd, const void *buffer,
-    size_t count, uint16_t offset)
+siba_write_multi_2(device_t dev, const void *buffer, size_t count,
+    uint16_t offset)
 {
+	struct siba_dev_softc *sd = device_get_ivars(dev);
 
 	sd->sd_ops->write_multi_2(sd, buffer, count, offset);
 }
 
 void
-siba_write_multi_4(struct siba_dev_softc *sd, const void *buffer,
-    size_t count, uint16_t offset)
+siba_write_multi_4(device_t dev, const void *buffer, size_t count,
+    uint16_t offset)
 {
+	struct siba_dev_softc *sd = device_get_ivars(dev);
 
 	sd->sd_ops->write_multi_4(sd, buffer, count, offset);
 }
@@ -1685,7 +1719,16 @@ siba_sprom_r123_antgain(uint8_t sprom_revision, const uint16_t *in,
 #undef SIBA_SHIFTOUT
 
 int
-siba_powerdown(struct siba_softc *siba)
+siba_powerdown(device_t dev)
+{
+	struct siba_dev_softc *sd = device_get_ivars(dev);
+	struct siba_softc *siba = sd->sd_bus;
+
+	return (siba_powerdown_sub(siba));
+}
+
+static int
+siba_powerdown_sub(struct siba_softc *siba)
 {
 	struct siba_cc *scc;
 
@@ -1710,61 +1753,77 @@ siba_pcicore_init(struct siba_pci *spc)
 		return;
 
 	siba = sd->sd_bus;
-	if (!siba_dev_isup(sd))
-		siba_dev_up(sd, 0);
+	if (!siba_dev_isup_sub(sd))
+		siba_dev_up_sub(sd, 0);
 
 	KASSERT(spc->spc_hostmode == 0,
 	    ("%s:%d: hostmode", __func__, __LINE__));
 	/* disable PCI interrupt */
-	siba_write_4(spc->spc_dev, SIBA_INTR_MASK, 0);
+	siba_write_4_sub(spc->spc_dev, SIBA_INTR_MASK, 0);
 }
 
 int
-siba_dev_isup(struct siba_dev_softc *sd)
+siba_dev_isup(device_t dev)
+{
+	struct siba_dev_softc *sd = device_get_ivars(dev);
+
+	return (siba_dev_isup_sub(sd));
+}
+
+static int
+siba_dev_isup_sub(struct siba_dev_softc *sd)
 {
 	uint32_t reject, val;
 
 	reject = siba_tmslow_reject_bitmask(sd);
-	val = siba_read_4(sd, SIBA_TGSLOW);
+	val = siba_read_4_sub(sd, SIBA_TGSLOW);
 	val &= SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_RESET | reject;
 
 	return (val == SIBA_TGSLOW_CLOCK);
 }
 
 void
-siba_dev_up(struct siba_dev_softc *sd, uint32_t flags)
+siba_dev_up(device_t dev, uint32_t flags)
+{
+	struct siba_dev_softc *sd = device_get_ivars(dev);
+
+	siba_dev_up_sub(sd, flags);
+}
+
+static void
+siba_dev_up_sub(struct siba_dev_softc *sd, uint32_t flags)
 {
 	uint32_t val;
 
-	siba_dev_down(sd, flags);
-	siba_write_4(sd, SIBA_TGSLOW, SIBA_TGSLOW_RESET | SIBA_TGSLOW_CLOCK |
-	    SIBA_TGSLOW_FGC | flags);
-	siba_read_4(sd, SIBA_TGSLOW);
+	siba_dev_down_sub(sd, flags);
+	siba_write_4_sub(sd, SIBA_TGSLOW,
+	    SIBA_TGSLOW_RESET | SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags);
+	siba_read_4_sub(sd, SIBA_TGSLOW);
 	DELAY(1);
 
-	if (siba_read_4(sd, SIBA_TGSHIGH) & SIBA_TGSHIGH_SERR)
-		siba_write_4(sd, SIBA_TGSHIGH, 0);
+	if (siba_read_4_sub(sd, SIBA_TGSHIGH) & SIBA_TGSHIGH_SERR)
+		siba_write_4_sub(sd, SIBA_TGSHIGH, 0);
 
-	val = siba_read_4(sd, SIBA_IAS);
+	val = siba_read_4_sub(sd, SIBA_IAS);
 	if (val & (SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT)) {
 		val &= ~(SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT);
-		siba_write_4(sd, SIBA_IAS, val);
+		siba_write_4_sub(sd, SIBA_IAS, val);
 	}
 
-	siba_write_4(sd, SIBA_TGSLOW,
+	siba_write_4_sub(sd, SIBA_TGSLOW,
 	    SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags);
-	siba_read_4(sd, SIBA_TGSLOW);
+	siba_read_4_sub(sd, SIBA_TGSLOW);
 	DELAY(1);
 
-	siba_write_4(sd, SIBA_TGSLOW, SIBA_TGSLOW_CLOCK | flags);
-	siba_read_4(sd, SIBA_TGSLOW);
+	siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_CLOCK | flags);
+	siba_read_4_sub(sd, SIBA_TGSLOW);
 	DELAY(1);
 }
 
 static uint32_t
 siba_tmslow_reject_bitmask(struct siba_dev_softc *sd)
 {
-	uint32_t rev = siba_read_4(sd, SIBA_IDLOW) & SIBA_IDLOW_SSBREV;
+	uint32_t rev = siba_read_4_sub(sd, SIBA_IDLOW) & SIBA_IDLOW_SSBREV;
 
 	switch (rev) {
 	case SIBA_IDLOW_SSBREV_22:
@@ -1785,20 +1844,28 @@ siba_tmslow_reject_bitmask(struct siba_dev_softc *sd)
 }
 
 void
-siba_dev_down(struct siba_dev_softc *sd, uint32_t flags)
+siba_dev_down(device_t dev, uint32_t flags)
+{
+	struct siba_dev_softc *sd = device_get_ivars(dev);
+
+	siba_dev_down_sub(sd, flags);
+}
+
+static void
+siba_dev_down_sub(struct siba_dev_softc *sd, uint32_t flags)
 {
 	struct siba_softc *siba = sd->sd_bus;
 	uint32_t reject, val;
 	int i;
 
-	if (siba_read_4(sd, SIBA_TGSLOW) & SIBA_TGSLOW_RESET)
+	if (siba_read_4_sub(sd, SIBA_TGSLOW) & SIBA_TGSLOW_RESET)
 		return;
 
 	reject = siba_tmslow_reject_bitmask(sd);
-	siba_write_4(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_CLOCK);
+	siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_CLOCK);
 
 	for (i = 0; i < 1000; i++) {
-		val = siba_read_4(sd, SIBA_TGSLOW);
+		val = siba_read_4_sub(sd, SIBA_TGSLOW);
 		if (val & reject)
 			break;
 		DELAY(10);
@@ -1808,7 +1875,7 @@ siba_dev_down(struct siba_dev_softc *sd, uint32_t flags)
 		    reject, SIBA_TGSLOW);
 	}
 	for (i = 0; i < 1000; i++) {
-		val = siba_read_4(sd, SIBA_TGSHIGH);
+		val = siba_read_4_sub(sd, SIBA_TGSHIGH);
 		if (!(val & SIBA_TGSHIGH_BUSY))
 			break;
 		DELAY(10);
@@ -1818,12 +1885,12 @@ siba_dev_down(struct siba_dev_softc *sd, uint32_t flags)
 		    SIBA_TGSHIGH_BUSY, SIBA_TGSHIGH);
 	}
 
-	siba_write_4(sd, SIBA_TGSLOW, SIBA_TGSLOW_FGC | SIBA_TGSLOW_CLOCK |
+	siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_FGC | SIBA_TGSLOW_CLOCK |
 	    reject | SIBA_TGSLOW_RESET | flags);
-	siba_read_4(sd, SIBA_TGSLOW);
+	siba_read_4_sub(sd, SIBA_TGSLOW);
 	DELAY(1);
-	siba_write_4(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_RESET | flags);
-	siba_read_4(sd, SIBA_TGSLOW);
+	siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_RESET | flags);
+	siba_read_4_sub(sd, SIBA_TGSLOW);
 	DELAY(1);
 }
 
@@ -1840,21 +1907,22 @@ siba_pcicore_setup(struct siba_pci *spc, struct siba_dev_softc *sd)
 		    SIBA_PCICORE_SBTOPCI_PREF | SIBA_PCICORE_SBTOPCI_BURST);
 
 		if (psd->sd_id.sd_rev < 5) {
-			tmp = siba_read_4(psd, SIBA_IMCFGLO);
+			tmp = siba_read_4_sub(psd, SIBA_IMCFGLO);
 			tmp &= ~SIBA_IMCFGLO_SERTO;
 			tmp = (tmp | 2) & ~SIBA_IMCFGLO_REQTO;
 			tmp |= 3 << 4 /* SIBA_IMCFGLO_REQTO_SHIFT */;
-			siba_write_4(psd, SIBA_IMCFGLO, tmp);
+			siba_write_4_sub(psd, SIBA_IMCFGLO, tmp);
 
 			/* broadcast value */
 			sd = (siba->siba_cc.scc_dev != NULL) ?
 			    siba->siba_cc.scc_dev : siba->siba_pci.spc_dev;
 			if (sd != NULL) {
-				siba_write_4(sd, SIBA_PCICORE_BCAST_ADDR,
+				siba_write_4_sub(sd, SIBA_PCICORE_BCAST_ADDR,
 				    0xfd8);
-				siba_read_4(sd, SIBA_PCICORE_BCAST_ADDR);
-				siba_write_4(sd, SIBA_PCICORE_BCAST_DATA, 0);
-				siba_read_4(sd, SIBA_PCICORE_BCAST_DATA);
+				siba_read_4_sub(sd, SIBA_PCICORE_BCAST_ADDR);
+				siba_write_4_sub(sd,
+				    SIBA_PCICORE_BCAST_DATA, 0);
+				siba_read_4_sub(sd, SIBA_PCICORE_BCAST_DATA);
 			}
 		} else if (psd->sd_id.sd_rev >= 11) {
 			tmp = siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2);
@@ -1878,27 +1946,31 @@ siba_pcicore_setup(struct siba_pci *spc, struct siba_dev_softc *sd)
 }
 
 void
-siba_pcicore_intr(struct siba_pci *spc, struct siba_dev_softc *sd)
+siba_pcicore_intr(device_t dev)
 {
+	struct siba_dev_softc *sd = device_get_ivars(dev);
+	struct siba_softc *siba = sd->sd_bus;
+	struct siba_pci *spc = &siba->siba_pci;
 	struct siba_dev_softc *psd = spc->spc_dev;
-	struct siba_softc *siba;
 	uint32_t tmp;
 
-	if (sd->sd_bus->siba_type != SIBA_TYPE_PCI || !psd)
+	if (siba->siba_type != SIBA_TYPE_PCI || !psd)
 		return;
 
-	siba = psd->sd_bus;
+	KASSERT(siba == psd->sd_bus, ("different pointers"));
+
 	/* enable interrupts */
 	if (siba->siba_dev != NULL &&
-	    (psd->sd_id.sd_rev >= 6 || psd->sd_id.sd_device == SIBA_DEVID_PCIE)) {
+	    (psd->sd_id.sd_rev >= 6 ||
+	     psd->sd_id.sd_device == SIBA_DEVID_PCIE)) {
 		tmp = pci_read_config(siba->siba_dev, SIBA_IRQMASK, 4);
 		tmp |= (1 << sd->sd_coreidx) << 8;
 		pci_write_config(siba->siba_dev, SIBA_IRQMASK, tmp, 4);
 	} else {
-		tmp = siba_read_4(sd, SIBA_TPS);
+		tmp = siba_read_4_sub(sd, SIBA_TPS);
 		tmp &= SIBA_TPS_BPFLAG;
-		siba_write_4(psd, SIBA_INTR_MASK,
-		    siba_read_4(psd, SIBA_INTR_MASK) | (1 << tmp));
+		siba_write_4_sub(psd, SIBA_INTR_MASK,
+		    siba_read_4_sub(psd, SIBA_INTR_MASK) | (1 << tmp));
 	}
 
 	/* setup PCIcore */
@@ -1910,14 +1982,14 @@ static uint32_t
 siba_pcicore_read_4(struct siba_pci *spc, uint16_t offset)
 {
 
-	return (siba_read_4(spc->spc_dev, offset));
+	return (siba_read_4_sub(spc->spc_dev, offset));
 }
 
 static void
 siba_pcicore_write_4(struct siba_pci *spc, uint16_t offset, uint32_t value)
 {
 
-	siba_write_4(spc->spc_dev, offset, value);
+	siba_write_4_sub(spc->spc_dev, offset, value);
 }
 
 static uint32_t
@@ -1957,17 +2029,20 @@ siba_pcie_mdio_write(struct siba_pci *spc, uint8_t device, uint8_t address,
 }
 
 uint32_t
-siba_dma_translation(struct siba_dev_softc *sd)
+siba_dma_translation(device_t dev)
 {
+	struct siba_dev_softc *sd = device_get_ivars(dev);
+	struct siba_softc *siba = sd->sd_bus;
 
-	KASSERT(sd->sd_bus->siba_type == SIBA_TYPE_PCI,
-	    ("unsupported bustype %d\n", sd->sd_bus->siba_type));
+	KASSERT(siba->siba_type == SIBA_TYPE_PCI,
+	    ("unsupported bustype %d\n", siba->siba_type));
 	return (SIBA_PCI_DMA);
 }
 
 void
-siba_barrier(struct siba_dev_softc *sd, int flags)
+siba_barrier(device_t dev, int flags)
 {
+	struct siba_dev_softc *sd = device_get_ivars(dev);
 	struct siba_softc *siba = sd->sd_bus;
 
 	SIBA_BARRIER(siba, flags);
@@ -2004,10 +2079,10 @@ siba_core_resume(struct siba_softc *siba)
 	siba->siba_pci.spc_inited = 0;
 	siba->siba_curdev = NULL;
 
-	siba_powerup(siba, 0);
+	siba_powerup_sub(siba, 0);
 	/* XXX setup H/W for PCMCIA??? */
 	siba_cc_resume(&siba->siba_cc);
-	siba_powerdown(siba);
+	siba_powerdown_sub(siba);
 
 	return (0);
 }
@@ -2026,9 +2101,11 @@ siba_cc_regctl_setmask(struct siba_cc *cc, uint32_t offset, uint32_t mask,
 }
 
 void
-siba_cc_pmu_set_ldovolt(struct siba_cc *scc, int id, uint32_t volt)
+siba_cc_pmu_set_ldovolt(device_t dev, int id, uint32_t volt)
 {
-	struct siba_softc *siba = scc->scc_dev->sd_bus;
+	struct siba_dev_softc *sd = device_get_ivars(dev);
+	struct siba_softc *siba = sd->sd_bus;
+	struct siba_cc *scc = &siba->siba_cc;
 	uint32_t *p = NULL, info[5][3] = {
 		{ 2, 25,  0xf },
 		{ 3,  1,  0xf },
@@ -2070,9 +2147,11 @@ siba_cc_pmu_set_ldovolt(struct siba_cc *scc, int id, uint32_t volt)
 }
 
 void
-siba_cc_pmu_set_ldoparef(struct siba_cc *scc, uint8_t on)
+siba_cc_pmu_set_ldoparef(device_t dev, uint8_t on)
 {
-	struct siba_softc *siba = scc->scc_dev->sd_bus;
+	struct siba_dev_softc *sd = device_get_ivars(dev);
+	struct siba_softc *siba = sd->sd_bus;
+	struct siba_cc *scc = &siba->siba_cc;
 	int ldo;
 
 	ldo = ((siba->siba_chipid == 0x4312) ? SIBA_CC_PMU_4312_PA_REF :
@@ -2087,3 +2166,419 @@ siba_cc_pmu_set_ldoparef(struct siba_cc *scc, uint8_t on)
 		SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, ~(1 << ldo));
 	SIBA_CC_READ32(scc, SIBA_CC_PMU_MINRES);
 }
+
+int
+siba_read_sprom(device_t dev, device_t child, int which, uintptr_t *result)
+{
+	struct siba_dev_softc *sd = device_get_ivars(child);
+	struct siba_softc *siba = sd->sd_bus;
+
+	switch (which) {
+	case SIBA_SPROMVAR_REV:
+		*result = siba->siba_sprom.rev;
+		break;
+	case SIBA_SPROMVAR_MAC_80211BG:
+		*((uint8_t **) result) = siba->siba_sprom.mac_80211bg;
+		break;
+	case SIBA_SPROMVAR_MAC_ETH:
+		*((uint8_t **) result) = siba->siba_sprom.mac_eth;
+		break;
+	case SIBA_SPROMVAR_MAC_80211A:
+		*((uint8_t **) result) = siba->siba_sprom.mac_80211a;
+		break;
+	case SIBA_SPROMVAR_MII_ETH0:
+		*result = siba->siba_sprom.mii_eth0;
+		break;
+	case SIBA_SPROMVAR_MII_ETH1:
+		*result = siba->siba_sprom.mii_eth1;
+		break;
+	case SIBA_SPROMVAR_MDIO_ETH0:
+		*result = siba->siba_sprom.mdio_eth0;
+		break;
+	case SIBA_SPROMVAR_MDIO_ETH1:
+		*result = siba->siba_sprom.mdio_eth1;
+		break;
+	case SIBA_SPROMVAR_BREV:
+		*result = siba->siba_sprom.brev;
+		break;
+	case SIBA_SPROMVAR_CCODE:
+		*result = siba->siba_sprom.ccode;
+		break;
+	case SIBA_SPROMVAR_ANT_A:
+		*result = siba->siba_sprom.ant_a;
+		break;
+	case SIBA_SPROMVAR_ANT_BG:
+		*result = siba->siba_sprom.ant_bg;
+		break;
+	case SIBA_SPROMVAR_PA0B0:
+		*result = siba->siba_sprom.pa0b0;
+		break;
+	case SIBA_SPROMVAR_PA0B1:
+		*result = siba->siba_sprom.pa0b1;
+		break;
+	case SIBA_SPROMVAR_PA0B2:
+		*result = siba->siba_sprom.pa0b2;
+		break;
+	case SIBA_SPROMVAR_PA1B0:
+		*result = siba->siba_sprom.pa1b0;
+		break;
+	case SIBA_SPROMVAR_PA1B1:
+		*result = siba->siba_sprom.pa1b1;
+		break;
+	case SIBA_SPROMVAR_PA1B2:
+		*result = siba->siba_sprom.pa1b2;
+		break;
+	case SIBA_SPROMVAR_PA1LOB0:
+		*result = siba->siba_sprom.pa1lob0;
+		break;
+	case SIBA_SPROMVAR_PA1LOB1:
+		*result = siba->siba_sprom.pa1lob1;
+		break;
+	case SIBA_SPROMVAR_PA1LOB2:
+		*result = siba->siba_sprom.pa1lob2;
+		break;
+	case SIBA_SPROMVAR_PA1HIB0:
+		*result = siba->siba_sprom.pa1hib0;
+		break;
+	case SIBA_SPROMVAR_PA1HIB1:
+		*result = siba->siba_sprom.pa1hib1;
+		break;
+	case SIBA_SPROMVAR_PA1HIB2:
+		*result = siba->siba_sprom.pa1hib2;
+		break;
+	case SIBA_SPROMVAR_GPIO0:
+		*result = siba->siba_sprom.gpio0;
+		break;
+	case SIBA_SPROMVAR_GPIO1:
+		*result = siba->siba_sprom.gpio1;
+		break;
+	case SIBA_SPROMVAR_GPIO2:
+		*result = siba->siba_sprom.gpio2;
+		break;
+	case SIBA_SPROMVAR_GPIO3:
+		*result = siba->siba_sprom.gpio3;
+		break;
+	case SIBA_SPROMVAR_MAXPWR_AL:
+		*result = siba->siba_sprom.maxpwr_al;
+		break;
+	case SIBA_SPROMVAR_MAXPWR_A:
+		*result = siba->siba_sprom.maxpwr_a;
+		break;
+	case SIBA_SPROMVAR_MAXPWR_AH:
+		*result = siba->siba_sprom.maxpwr_ah;
+		break;
+	case SIBA_SPROMVAR_MAXPWR_BG:
+		*result = siba->siba_sprom.maxpwr_bg;
+		break;
+	case SIBA_SPROMVAR_RXPO2G:
+		*result = siba->siba_sprom.rxpo2g;
+		break;
+	case SIBA_SPROMVAR_RXPO5G:
+		*result = siba->siba_sprom.rxpo5g;
+		break;
+	case SIBA_SPROMVAR_TSSI_A:
+		*result = siba->siba_sprom.tssi_a;
+		break;
+	case SIBA_SPROMVAR_TSSI_BG:
+		*result = siba->siba_sprom.tssi_bg;
+		break;
+	case SIBA_SPROMVAR_TRI2G:
+		*result = siba->siba_sprom.tri2g;
+		break;
+	case SIBA_SPROMVAR_TRI5GL:
+		*result = siba->siba_sprom.tri5gl;
+		break;
+	case SIBA_SPROMVAR_TRI5G:
+		*result = siba->siba_sprom.tri5g;
+		break;
+	case SIBA_SPROMVAR_TRI5GH:
+		*result = siba->siba_sprom.tri5gh;
+		break;
+	case SIBA_SPROMVAR_RSSISAV2G:
+		*result = siba->siba_sprom.rssisav2g;
+		break;
+	case SIBA_SPROMVAR_RSSISMC2G:
+		*result = siba->siba_sprom.rssismc2g;
+		break;
+	case SIBA_SPROMVAR_RSSISMF2G:
+		*result = siba->siba_sprom.rssismf2g;
+		break;
+	case SIBA_SPROMVAR_BXA2G:
+		*result = siba->siba_sprom.bxa2g;
+		break;
+	case SIBA_SPROMVAR_RSSISAV5G:
+		*result = siba->siba_sprom.rssisav5g;
+		break;
+	case SIBA_SPROMVAR_RSSISMC5G:
+		*result = siba->siba_sprom.rssismc5g;
+		break;
+	case SIBA_SPROMVAR_RSSISMF5G:
+		*result = siba->siba_sprom.rssismf5g;
+		break;
+	case SIBA_SPROMVAR_BXA5G:
+		*result = siba->siba_sprom.bxa5g;
+		break;
+	case SIBA_SPROMVAR_CCK2GPO:
+		*result = siba->siba_sprom.cck2gpo;
+		break;
+	case SIBA_SPROMVAR_OFDM2GPO:
+		*result = siba->siba_sprom.ofdm2gpo;
+		break;
+	case SIBA_SPROMVAR_OFDM5GLPO:
+		*result = siba->siba_sprom.ofdm5glpo;
+		break;
+	case SIBA_SPROMVAR_OFDM5GPO:
+		*result = siba->siba_sprom.ofdm5gpo;
+		break;
+	case SIBA_SPROMVAR_OFDM5GHPO:
+		*result = siba->siba_sprom.ofdm5ghpo;
+		break;
+	case SIBA_SPROMVAR_BF_LO:
+		*result = siba->siba_sprom.bf_lo;
+		break;
+	case SIBA_SPROMVAR_BF_HI:
+		*result = siba->siba_sprom.bf_hi;
+		break;
+	case SIBA_SPROMVAR_BF2_LO:
+		*result = siba->siba_sprom.bf2_lo;
+		break;
+	case SIBA_SPROMVAR_BF2_HI:
+		*result = siba->siba_sprom.bf2_hi;
+		break;
+	default:
+		return (ENOENT);
+	}
+	return (0);
+}
+
+int
+siba_write_sprom(device_t dev, device_t child, int which, uintptr_t value)
+{
+	struct siba_dev_softc *sd = device_get_ivars(child);
+	struct siba_softc *siba = sd->sd_bus;
+
+	switch (which) {
+	case SIBA_SPROMVAR_REV:
+		siba->siba_sprom.rev = value;
+		break;
+	case SIBA_SPROMVAR_MII_ETH0:
+		siba->siba_sprom.mii_eth0 = value;
+		break;
+	case SIBA_SPROMVAR_MII_ETH1:
+		siba->siba_sprom.mii_eth1 = value;
+		break;
+	case SIBA_SPROMVAR_MDIO_ETH0:
+		siba->siba_sprom.mdio_eth0 = value;
+		break;
+	case SIBA_SPROMVAR_MDIO_ETH1:
+		siba->siba_sprom.mdio_eth1 = value;
+		break;
+	case SIBA_SPROMVAR_BREV:
+		siba->siba_sprom.brev = value;
+		break;
+	case SIBA_SPROMVAR_CCODE:
+		siba->siba_sprom.ccode = value;
+		break;
+	case SIBA_SPROMVAR_ANT_A:
+		siba->siba_sprom.ant_a = value;
+		break;
+	case SIBA_SPROMVAR_ANT_BG:
+		siba->siba_sprom.ant_bg = value;
+		break;
+	case SIBA_SPROMVAR_PA0B0:
+		siba->siba_sprom.pa0b0 = value;
+		break;
+	case SIBA_SPROMVAR_PA0B1:
+		siba->siba_sprom.pa0b1 = value;
+		break;
+	case SIBA_SPROMVAR_PA0B2:
+		siba->siba_sprom.pa0b2 = value;
+		break;
+	case SIBA_SPROMVAR_PA1B0:
+		siba->siba_sprom.pa1b0 = value;
+		break;
+	case SIBA_SPROMVAR_PA1B1:
+		siba->siba_sprom.pa1b1 = value;
+		break;
+	case SIBA_SPROMVAR_PA1B2:
+		siba->siba_sprom.pa1b2 = value;
+		break;
+	case SIBA_SPROMVAR_PA1LOB0:
+		siba->siba_sprom.pa1lob0 = value;
+		break;
+	case SIBA_SPROMVAR_PA1LOB1:
+		siba->siba_sprom.pa1lob1 = value;
+		break;
+	case SIBA_SPROMVAR_PA1LOB2:
+		siba->siba_sprom.pa1lob2 = value;
+		break;
+	case SIBA_SPROMVAR_PA1HIB0:
+		siba->siba_sprom.pa1hib0 = value;
+		break;
+	case SIBA_SPROMVAR_PA1HIB1:
+		siba->siba_sprom.pa1hib1 = value;
+		break;
+	case SIBA_SPROMVAR_PA1HIB2:
+		siba->siba_sprom.pa1hib2 = value;
+		break;
+	case SIBA_SPROMVAR_GPIO0:
+		siba->siba_sprom.gpio0 = value;
+		break;
+	case SIBA_SPROMVAR_GPIO1:
+		siba->siba_sprom.gpio1 = value;
+		break;
+	case SIBA_SPROMVAR_GPIO2:
+		siba->siba_sprom.gpio2 = value;
+		break;
+	case SIBA_SPROMVAR_GPIO3:
+		siba->siba_sprom.gpio3 = value;
+		break;
+	case SIBA_SPROMVAR_MAXPWR_AL:
+		siba->siba_sprom.maxpwr_al = value;
+		break;
+	case SIBA_SPROMVAR_MAXPWR_A:
+		siba->siba_sprom.maxpwr_a = value;
+		break;
+	case SIBA_SPROMVAR_MAXPWR_AH:
+		siba->siba_sprom.maxpwr_ah = value;
+		break;
+	case SIBA_SPROMVAR_MAXPWR_BG:
+		siba->siba_sprom.maxpwr_bg = value;
+		break;
+	case SIBA_SPROMVAR_RXPO2G:
+		siba->siba_sprom.rxpo2g = value;
+		break;
+	case SIBA_SPROMVAR_RXPO5G:
+		siba->siba_sprom.rxpo5g = value;
+		break;
+	case SIBA_SPROMVAR_TSSI_A:
+		siba->siba_sprom.tssi_a = value;
+		break;
+	case SIBA_SPROMVAR_TSSI_BG:
+		siba->siba_sprom.tssi_bg = value;
+		break;
+	case SIBA_SPROMVAR_TRI2G:
+		siba->siba_sprom.tri2g = value;
+		break;
+	case SIBA_SPROMVAR_TRI5GL:
+		siba->siba_sprom.tri5gl = value;
+		break;
+	case SIBA_SPROMVAR_TRI5G:
+		siba->siba_sprom.tri5g = value;
+		break;
+	case SIBA_SPROMVAR_TRI5GH:
+		siba->siba_sprom.tri5gh = value;
+		break;
+	case SIBA_SPROMVAR_RSSISAV2G:
+		siba->siba_sprom.rssisav2g = value;
+		break;
+	case SIBA_SPROMVAR_RSSISMC2G:
+		siba->siba_sprom.rssismc2g = value;
+		break;
+	case SIBA_SPROMVAR_RSSISMF2G:
+		siba->siba_sprom.rssismf2g = value;
+		break;
+	case SIBA_SPROMVAR_BXA2G:
+		siba->siba_sprom.bxa2g = value;
+		break;
+	case SIBA_SPROMVAR_RSSISAV5G:
+		siba->siba_sprom.rssisav5g = value;
+		break;
+	case SIBA_SPROMVAR_RSSISMC5G:
+		siba->siba_sprom.rssismc5g = value;
+		break;
+	case SIBA_SPROMVAR_RSSISMF5G:
+		siba->siba_sprom.rssismf5g = value;
+		break;
+	case SIBA_SPROMVAR_BXA5G:
+		siba->siba_sprom.bxa5g = value;
+		break;
+	case SIBA_SPROMVAR_CCK2GPO:
+		siba->siba_sprom.cck2gpo = value;
+		break;
+	case SIBA_SPROMVAR_OFDM2GPO:
+		siba->siba_sprom.ofdm2gpo = value;
+		break;
+	case SIBA_SPROMVAR_OFDM5GLPO:
+		siba->siba_sprom.ofdm5glpo = value;
+		break;
+	case SIBA_SPROMVAR_OFDM5GPO:
+		siba->siba_sprom.ofdm5gpo = value;
+		break;
+	case SIBA_SPROMVAR_OFDM5GHPO:
+		siba->siba_sprom.ofdm5ghpo = value;
+		break;
+	case SIBA_SPROMVAR_BF_LO:
+		siba->siba_sprom.bf_lo = value;
+		break;
+	case SIBA_SPROMVAR_BF_HI:
+		siba->siba_sprom.bf_hi = value;
+		break;
+	case SIBA_SPROMVAR_BF2_LO:
+		siba->siba_sprom.bf2_lo = value;
+		break;
+	case SIBA_SPROMVAR_BF2_HI:
+		siba->siba_sprom.bf2_hi = value;
+		break;
+	default:
+		return (ENOENT);
+	}
+	return (0);
+}
+
+#define	SIBA_GPIOCTL			0x06c
+
+uint32_t
+siba_gpio_get(device_t dev)
+{
+	struct siba_dev_softc *sd = device_get_ivars(dev);
+	struct siba_softc *siba = sd->sd_bus;
+	struct siba_dev_softc *gpiodev, *pcidev = NULL;
+
+	pcidev = siba->siba_pci.spc_dev;
+	gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev;
+	if (!gpiodev)
+		return (-1);
+	return (siba_read_4_sub(gpiodev, SIBA_GPIOCTL));
+}
+
+void
+siba_gpio_set(device_t dev, uint32_t value)
+{
+	struct siba_dev_softc *sd = device_get_ivars(dev);
+	struct siba_softc *siba = sd->sd_bus;
+	struct siba_dev_softc *gpiodev, *pcidev = NULL;
+
+	pcidev = siba->siba_pci.spc_dev;
+	gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev;
+	if (!gpiodev)
+		return;
+	siba_write_4_sub(gpiodev, SIBA_GPIOCTL, value);
+}
+
+void
+siba_fix_imcfglobug(device_t dev)
+{
+	struct siba_dev_softc *sd = device_get_ivars(dev);
+	struct siba_softc *siba = sd->sd_bus;
+	uint32_t tmp;
+
+	if (siba->siba_pci.spc_dev == NULL)
+		return;
+	if (siba->siba_pci.spc_dev->sd_id.sd_device != SIBA_DEVID_PCI ||
+	    siba->siba_pci.spc_dev->sd_id.sd_rev > 5)
+		return;
+
+	tmp = siba_read_4_sub(sd, SIBA_IMCFGLO) &
+	    ~(SIBA_IMCFGLO_REQTO | SIBA_IMCFGLO_SERTO);
+	switch (siba->siba_type) {
+	case SIBA_TYPE_PCI:
+	case SIBA_TYPE_PCMCIA:
+		tmp |= 0x32;
+		break;
+	case SIBA_TYPE_SSB:
+		tmp |= 0x53;
+		break;
+	}
+	siba_write_4_sub(sd, SIBA_IMCFGLO, tmp);
+}
diff --git a/sys/dev/siba/sibavar.h b/sys/dev/siba/sibavar.h
index 307903b..9b82310 100644
--- a/sys/dev/siba/sibavar.h
+++ b/sys/dev/siba/sibavar.h
@@ -34,11 +34,30 @@
 struct siba_softc;
 struct siba_dev_softc;
 
+enum siba_type {
+	SIBA_TYPE_SSB,
+	SIBA_TYPE_PCI,
+	SIBA_TYPE_PCMCIA,
+};
+
 enum siba_device_ivars {
 	SIBA_IVAR_VENDOR,
 	SIBA_IVAR_DEVICE,
 	SIBA_IVAR_REVID,
-	SIBA_IVAR_CORE_INDEX
+	SIBA_IVAR_CORE_INDEX,
+	SIBA_IVAR_PCI_VENDOR,
+	SIBA_IVAR_PCI_DEVICE,
+	SIBA_IVAR_PCI_SUBVENDOR,
+	SIBA_IVAR_PCI_SUBDEVICE,
+	SIBA_IVAR_PCI_REVID,
+	SIBA_IVAR_CHIPID,
+	SIBA_IVAR_CHIPREV,
+	SIBA_IVAR_CHIPPKG,
+	SIBA_IVAR_TYPE,
+	SIBA_IVAR_CC_PMUFREQ,
+	SIBA_IVAR_CC_CAPS,
+	SIBA_IVAR_CC_POWERDELAY,
+	SIBA_IVAR_PCICORE_REVID
 };
 
 #define	SIBA_ACCESSOR(var, ivar, type)				\
@@ -48,6 +67,19 @@ SIBA_ACCESSOR(vendor,		VENDOR,		uint16_t)
 SIBA_ACCESSOR(device,		DEVICE,		uint16_t)
 SIBA_ACCESSOR(revid,		REVID,		uint8_t)
 SIBA_ACCESSOR(core_index,	CORE_INDEX,	uint8_t)
+SIBA_ACCESSOR(pci_vendor,	PCI_VENDOR,	uint16_t)
+SIBA_ACCESSOR(pci_device,	PCI_DEVICE,	uint16_t)
+SIBA_ACCESSOR(pci_subvendor,	PCI_SUBVENDOR,	uint16_t)
+SIBA_ACCESSOR(pci_subdevice,	PCI_SUBDEVICE,	uint16_t)
+SIBA_ACCESSOR(pci_revid,	PCI_REVID,	uint8_t)
+SIBA_ACCESSOR(chipid,		CHIPID,		uint16_t)
+SIBA_ACCESSOR(chiprev,		CHIPREV,	uint16_t)
+SIBA_ACCESSOR(chippkg,		CHIPPKG,	uint8_t)
+SIBA_ACCESSOR(type,		TYPE,		enum siba_type)
+SIBA_ACCESSOR(cc_pmufreq,	CC_PMUFREQ,	uint32_t)
+SIBA_ACCESSOR(cc_caps,		CC_CAPS,	uint32_t)
+SIBA_ACCESSOR(cc_powerdelay,	CC_POWERDELAY,	uint16_t)
+SIBA_ACCESSOR(pcicore_revid,	PCICORE_REVID,	uint8_t)
 
 #undef SIBA_ACCESSOR
 
@@ -135,9 +167,9 @@ enum {
 	SIBA_WRITE_2((siba), (reg), SIBA_READ_2((siba), (reg)) & ~(bits))
 
 #define	SIBA_CC_READ32(scc, offset) \
-	siba_read_4((scc)->scc_dev, offset)
+	siba_read_4_sub((scc)->scc_dev, offset)
 #define	SIBA_CC_WRITE32(scc, offset, val) \
-	siba_write_4((scc)->scc_dev, offset, val)
+	siba_write_4_sub((scc)->scc_dev, offset, val)
 #define	SIBA_CC_MASK32(scc, offset, mask) \
 	SIBA_CC_WRITE32(scc, offset, SIBA_CC_READ32(scc, offset) & (mask))
 #define	SIBA_CC_SET32(scc, offset, set) \
@@ -146,12 +178,6 @@ enum {
 	SIBA_CC_WRITE32(scc, offset,			\
 	    (SIBA_CC_READ32(scc, offset) & (mask)) | (set))
 
-enum siba_type {
-	SIBA_TYPE_SSB,
-	SIBA_TYPE_PCI,
-	SIBA_TYPE_PCMCIA,
-};
-
 enum siba_clock {
 	SIBA_CLOCK_DYNAMIC,
 	SIBA_CLOCK_SLOW,
@@ -195,6 +221,152 @@ struct siba_cc_pmu_res_depend {
 	uint32_t		depend;
 };
 
+enum siba_sprom_vars {
+	SIBA_SPROMVAR_REV,
+	SIBA_SPROMVAR_MAC_80211BG,
+	SIBA_SPROMVAR_MAC_ETH,
+	SIBA_SPROMVAR_MAC_80211A,
+	SIBA_SPROMVAR_MII_ETH0,
+	SIBA_SPROMVAR_MII_ETH1,
+	SIBA_SPROMVAR_MDIO_ETH0,
+	SIBA_SPROMVAR_MDIO_ETH1,
+	SIBA_SPROMVAR_BREV,
+	SIBA_SPROMVAR_CCODE,
+	SIBA_SPROMVAR_ANT_A,
+	SIBA_SPROMVAR_ANT_BG,
+	SIBA_SPROMVAR_PA0B0,
+	SIBA_SPROMVAR_PA0B1,
+	SIBA_SPROMVAR_PA0B2,
+	SIBA_SPROMVAR_PA1B0,
+	SIBA_SPROMVAR_PA1B1,
+	SIBA_SPROMVAR_PA1B2,
+	SIBA_SPROMVAR_PA1LOB0,
+	SIBA_SPROMVAR_PA1LOB1,
+	SIBA_SPROMVAR_PA1LOB2,
+	SIBA_SPROMVAR_PA1HIB0,
+	SIBA_SPROMVAR_PA1HIB1,
+	SIBA_SPROMVAR_PA1HIB2,
+	SIBA_SPROMVAR_GPIO0,
+	SIBA_SPROMVAR_GPIO1,
+	SIBA_SPROMVAR_GPIO2,
+	SIBA_SPROMVAR_GPIO3,
+	SIBA_SPROMVAR_MAXPWR_AL,
+	SIBA_SPROMVAR_MAXPWR_A,
+	SIBA_SPROMVAR_MAXPWR_AH,
+	SIBA_SPROMVAR_MAXPWR_BG,
+	SIBA_SPROMVAR_RXPO2G,
+	SIBA_SPROMVAR_RXPO5G,
+	SIBA_SPROMVAR_TSSI_A,
+	SIBA_SPROMVAR_TSSI_BG,
+	SIBA_SPROMVAR_TRI2G,
+	SIBA_SPROMVAR_TRI5GL,
+	SIBA_SPROMVAR_TRI5G,
+	SIBA_SPROMVAR_TRI5GH,
+	SIBA_SPROMVAR_RSSISAV2G,
+	SIBA_SPROMVAR_RSSISMC2G,
+	SIBA_SPROMVAR_RSSISMF2G,
+	SIBA_SPROMVAR_BXA2G,
+	SIBA_SPROMVAR_RSSISAV5G,
+	SIBA_SPROMVAR_RSSISMC5G,
+	SIBA_SPROMVAR_RSSISMF5G,
+	SIBA_SPROMVAR_BXA5G,
+	SIBA_SPROMVAR_CCK2GPO,
+	SIBA_SPROMVAR_OFDM2GPO,
+	SIBA_SPROMVAR_OFDM5GLPO,
+	SIBA_SPROMVAR_OFDM5GPO,
+	SIBA_SPROMVAR_OFDM5GHPO,
+	SIBA_SPROMVAR_BF_LO,
+	SIBA_SPROMVAR_BF_HI,
+	SIBA_SPROMVAR_BF2_LO,
+	SIBA_SPROMVAR_BF2_HI
+};
+
+int		siba_read_sprom(device_t, device_t, int, uintptr_t *);
+int		siba_write_sprom(device_t, device_t, int, uintptr_t);
+
+/**
+ * Generic sprom accessor generation macros for siba(4) drivers
+ */
+#define __SPROM_ACCESSOR(varp, var, ivarp, ivar, type)			\
+									\
+static __inline type varp ## _get_ ## var(device_t dev)			\
+{									\
+	uintptr_t v;							\
+	siba_read_sprom(device_get_parent(dev), dev,			\
+	    ivarp ## _SPROMVAR_ ## ivar, &v);				\
+	return ((type) v);						\
+}									\
+									\
+static __inline void varp ## _set_ ## var(device_t dev, type t)		\
+{									\
+	uintptr_t v = (uintptr_t) t;					\
+	siba_write_sprom(device_get_parent(dev), dev,			\
+	    ivarp ## _SPROMVAR_ ## ivar, v);				\
+}
+
+#define	SIBA_SPROM_ACCESSOR(var, ivar, type)				\
+	__SPROM_ACCESSOR(siba_sprom, var, SIBA, ivar, type)
+
+SIBA_SPROM_ACCESSOR(rev,	REV,		uint8_t);
+SIBA_SPROM_ACCESSOR(mac_80211bg,	MAC_80211BG,	uint8_t *);
+SIBA_SPROM_ACCESSOR(mac_eth,	MAC_ETH,	uint8_t *);
+SIBA_SPROM_ACCESSOR(mac_80211a,	MAC_80211A,	uint8_t *);
+SIBA_SPROM_ACCESSOR(mii_eth0,	MII_ETH0,	uint8_t);
+SIBA_SPROM_ACCESSOR(mii_eth1,	MII_ETH1,	uint8_t);
+SIBA_SPROM_ACCESSOR(mdio_eth0,	MDIO_ETH0,	uint8_t);
+SIBA_SPROM_ACCESSOR(mdio_eth1,	MDIO_ETH1,	uint8_t);
+SIBA_SPROM_ACCESSOR(brev,	BREV,		uint8_t);
+SIBA_SPROM_ACCESSOR(ccode,	CCODE,		uint8_t);
+SIBA_SPROM_ACCESSOR(ant_a,	ANT_A,		uint8_t);
+SIBA_SPROM_ACCESSOR(ant_bg,	ANT_BG,		uint8_t);
+SIBA_SPROM_ACCESSOR(pa0b0,	PA0B0,		uint16_t);
+SIBA_SPROM_ACCESSOR(pa0b1,	PA0B1,		uint16_t);
+SIBA_SPROM_ACCESSOR(pa0b2,	PA0B2,		uint16_t);
+SIBA_SPROM_ACCESSOR(pa1b0,	PA1B0,		uint16_t);
+SIBA_SPROM_ACCESSOR(pa1b1,	PA1B1,		uint16_t);
+SIBA_SPROM_ACCESSOR(pa1b2,	PA1B2,		uint16_t);
+SIBA_SPROM_ACCESSOR(pa1lob0,	PA1LOB0,	uint16_t);
+SIBA_SPROM_ACCESSOR(pa1lob1,	PA1LOB1,	uint16_t);
+SIBA_SPROM_ACCESSOR(pa1lob2,	PA1LOB2,	uint16_t);
+SIBA_SPROM_ACCESSOR(pa1hib0,	PA1HIB0,	uint16_t);
+SIBA_SPROM_ACCESSOR(pa1hib1,	PA1HIB1,	uint16_t);
+SIBA_SPROM_ACCESSOR(pa1hib2,	PA1HIB2,	uint16_t);
+SIBA_SPROM_ACCESSOR(gpio0,	GPIO0,		uint8_t);
+SIBA_SPROM_ACCESSOR(gpio1,	GPIO1,		uint8_t);
+SIBA_SPROM_ACCESSOR(gpio2,	GPIO2,		uint8_t);
+SIBA_SPROM_ACCESSOR(gpio3,	GPIO3,		uint8_t);
+SIBA_SPROM_ACCESSOR(maxpwr_al,	MAXPWR_AL,	uint16_t);
+SIBA_SPROM_ACCESSOR(maxpwr_a,	MAXPWR_A,	uint16_t);
+SIBA_SPROM_ACCESSOR(maxpwr_ah,	MAXPWR_AH,	uint16_t);
+SIBA_SPROM_ACCESSOR(maxpwr_bg,	MAXPWR_BG,	uint16_t);
+SIBA_SPROM_ACCESSOR(rxpo2g,	RXPO2G,		uint8_t);
+SIBA_SPROM_ACCESSOR(rxpo5g,	RXPO5G,		uint8_t);
+SIBA_SPROM_ACCESSOR(tssi_a,	TSSI_A,		uint8_t);
+SIBA_SPROM_ACCESSOR(tssi_bg,	TSSI_BG,	uint8_t);
+SIBA_SPROM_ACCESSOR(tri2g,	TRI2G,		uint8_t);
+SIBA_SPROM_ACCESSOR(tri5gl,	TRI5GL,		uint8_t);
+SIBA_SPROM_ACCESSOR(tri5g,	TRI5G,		uint8_t);
+SIBA_SPROM_ACCESSOR(tri5gh,	TRI5GH,		uint8_t);
+SIBA_SPROM_ACCESSOR(rssisav2g,	RSSISAV2G,	uint8_t);
+SIBA_SPROM_ACCESSOR(rssismc2g,	RSSISMC2G,	uint8_t);
+SIBA_SPROM_ACCESSOR(rssismf2g,	RSSISMF2G,	uint8_t);
+SIBA_SPROM_ACCESSOR(bxa2g,	BXA2G,		uint8_t);
+SIBA_SPROM_ACCESSOR(rssisav5g,	RSSISAV5G,	uint8_t);
+SIBA_SPROM_ACCESSOR(rssismc5g,	RSSISMC5G,	uint8_t);
+SIBA_SPROM_ACCESSOR(rssismf5g,	RSSISMF5G,	uint8_t);
+SIBA_SPROM_ACCESSOR(bxa5g,	BXA5G,		uint8_t);
+SIBA_SPROM_ACCESSOR(cck2gpo,	CCK2GPO,	uint16_t);
+SIBA_SPROM_ACCESSOR(ofdm2gpo,	OFDM2GPO,	uint32_t);
+SIBA_SPROM_ACCESSOR(ofdm5glpo,	OFDM5GLPO,	uint32_t);
+SIBA_SPROM_ACCESSOR(ofdm5gpo,	OFDM5GPO,	uint32_t);
+SIBA_SPROM_ACCESSOR(ofdm5ghpo,	OFDM5GHPO,	uint32_t);
+SIBA_SPROM_ACCESSOR(bf_lo,	BF_LO,		uint16_t);
+SIBA_SPROM_ACCESSOR(bf_hi,	BF_HI,		uint16_t);
+SIBA_SPROM_ACCESSOR(bf2_lo,	BF2_LO,		uint16_t);
+SIBA_SPROM_ACCESSOR(bf2_hi,	BF2_HI,		uint16_t);
+
+#undef SIBA_SPROM_ACCESSOR
+
 struct siba_sprom {
 	uint8_t			rev;		/* revision */
 	uint8_t			mac_80211bg[6];	/* address for 802.11b/g */
@@ -358,6 +530,7 @@ struct siba_softc {
 	uint16_t			siba_pci_did;
 	uint16_t			siba_pci_subvid;
 	uint16_t			siba_pci_subdid;
+	uint8_t				siba_pci_revid;
 	int				siba_mem_rid;
 
 	uint16_t			siba_chipid;	/* for CORE 0 */
@@ -368,41 +541,32 @@ struct siba_softc {
 	struct siba_pci			siba_pci;	/* PCI-core */
 	const struct siba_bus_ops	*siba_ops;
 
-	/* board informations */
-	uint16_t			siba_board_vendor;
-	uint16_t			siba_board_type;
-	uint16_t			siba_board_rev;
 	struct siba_sprom		siba_sprom;	/* SPROM */
 	uint16_t			siba_spromsize;	/* in word size */
 };
 
-void		siba_powerup(struct siba_softc *, int);
-uint16_t	siba_read_2(struct siba_dev_softc *, uint16_t);
-void		siba_write_2(struct siba_dev_softc *, uint16_t, uint16_t);
-uint32_t	siba_read_4(struct siba_dev_softc *, uint16_t);
-void		siba_write_4(struct siba_dev_softc *, uint16_t, uint32_t);
-void		siba_dev_up(struct siba_dev_softc *, uint32_t);
-void		siba_dev_down(struct siba_dev_softc *, uint32_t);
-int		siba_powerdown(struct siba_softc *);
-int		siba_dev_isup(struct siba_dev_softc *);
-void		siba_pcicore_intr(struct siba_pci *, struct siba_dev_softc *);
-uint32_t	siba_dma_translation(struct siba_dev_softc *);
-void		*siba_dma_alloc_consistent(struct siba_dev_softc *, size_t,
-		    bus_addr_t *);
-void		siba_read_multi_1(struct siba_dev_softc *, void *, size_t,
-		    uint16_t);
-void		siba_read_multi_2(struct siba_dev_softc *, void *, size_t,
-		    uint16_t);
-void		siba_read_multi_4(struct siba_dev_softc *, void *, size_t,
-		    uint16_t);
-void		siba_write_multi_1(struct siba_dev_softc *, const void *,
-		    size_t, uint16_t);
-void		siba_write_multi_2(struct siba_dev_softc *, const void *,
-		    size_t, uint16_t);
-void		siba_write_multi_4(struct siba_dev_softc *, const void *,
-		    size_t, uint16_t);
-void		siba_barrier(struct siba_dev_softc *, int);
-void		siba_cc_pmu_set_ldovolt(struct siba_cc *, int, uint32_t);
-void		siba_cc_pmu_set_ldoparef(struct siba_cc *, uint8_t);
+void		siba_powerup(device_t, int);
+int		siba_powerdown(device_t);
+uint16_t	siba_read_2(device_t, uint16_t);
+void		siba_write_2(device_t, uint16_t, uint16_t);
+uint32_t	siba_read_4(device_t, uint16_t);
+void		siba_write_4(device_t, uint16_t, uint32_t);
+void		siba_dev_up(device_t, uint32_t);
+void		siba_dev_down(device_t, uint32_t);
+int		siba_dev_isup(device_t);
+void		siba_pcicore_intr(device_t);
+uint32_t	siba_dma_translation(device_t);
+void		siba_read_multi_1(device_t, void *, size_t, uint16_t);
+void		siba_read_multi_2(device_t, void *, size_t, uint16_t);
+void		siba_read_multi_4(device_t, void *, size_t, uint16_t);
+void		siba_write_multi_1(device_t, const void *, size_t, uint16_t);
+void		siba_write_multi_2(device_t, const void *, size_t, uint16_t);
+void		siba_write_multi_4(device_t, const void *, size_t, uint16_t);
+void		siba_barrier(device_t, int);
+void		siba_cc_pmu_set_ldovolt(device_t, int, uint32_t);
+void		siba_cc_pmu_set_ldoparef(device_t, uint8_t);
+void		siba_gpio_set(device_t, uint32_t);
+uint32_t	siba_gpio_get(device_t);
+void		siba_fix_imcfglobug(device_t);
 
 #endif /* _SIBA_SIBAVAR_H_ */