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author | raj <raj@FreeBSD.org> | 2008-03-03 18:20:17 +0000 |
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committer | raj <raj@FreeBSD.org> | 2008-03-03 18:20:17 +0000 |
commit | ddcbd7a1c933343caf6997ea48416ce7af082d83 (patch) | |
tree | 4bfcfaef6ba2a3d7ebf036eb0d0325e2431535cc /sys/dev/scc/scc_dev_quicc.c | |
parent | 0757a4afb5d18c5b874cc918eb56d7264456bd20 (diff) | |
download | FreeBSD-src-ddcbd7a1c933343caf6997ea48416ce7af082d83.zip FreeBSD-src-ddcbd7a1c933343caf6997ea48416ce7af082d83.tar.gz |
Support for Freescale QUad Integrated Communications Controller.
The QUICC engine is found on various Freescale parts including MPC85xx, and
provides multiple generic time-division serial channel resources, which are in
turn muxed/demuxed by the Serial Communications Controller (SCC).
Along with core QUICC/SCC functionality a uart(4)-compliant device driver is
provided which allows for serial ports over QUICC/SCC.
Approved by: cognet (mentor)
Obtained from: Juniper
MFp4: e500
Diffstat (limited to 'sys/dev/scc/scc_dev_quicc.c')
-rw-r--r-- | sys/dev/scc/scc_dev_quicc.c | 151 |
1 files changed, 151 insertions, 0 deletions
diff --git a/sys/dev/scc/scc_dev_quicc.c b/sys/dev/scc/scc_dev_quicc.c new file mode 100644 index 0000000..6f337b8 --- /dev/null +++ b/sys/dev/scc/scc_dev_quicc.c @@ -0,0 +1,151 @@ +/*- + * Copyright (c) 2004-2006 Marcel Moolenaar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#define __RMAN_RESOURCE_VISIBLE + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/conf.h> +#include <sys/endian.h> +#include <machine/bus.h> +#include <sys/rman.h> +#include <sys/serial.h> + +#include <dev/scc/scc_bfe.h> +#include <dev/scc/scc_bus.h> + +#include <dev/ic/quicc.h> + +#include "scc_if.h" + +#define quicc_read2(bas, reg) \ + bus_space_read_2((bas)->bst, (bas)->bsh, reg) + +#define quicc_write2(bas, reg, val) \ + bus_space_write_2((bas)->bst, (bas)->bsh, reg, val) + +static int quicc_bfe_attach(struct scc_softc *, int); +static int quicc_bfe_enabled(struct scc_softc *, struct scc_chan *); +static int quicc_bfe_iclear(struct scc_softc *, struct scc_chan *); +static int quicc_bfe_ipend(struct scc_softc *); +static int quicc_bfe_probe(struct scc_softc *); + +static kobj_method_t quicc_methods[] = { + KOBJMETHOD(scc_attach, quicc_bfe_attach), + KOBJMETHOD(scc_enabled, quicc_bfe_enabled), + KOBJMETHOD(scc_iclear, quicc_bfe_iclear), + KOBJMETHOD(scc_ipend, quicc_bfe_ipend), + KOBJMETHOD(scc_probe, quicc_bfe_probe), + { 0, 0 } +}; + +struct scc_class scc_quicc_class = { + "QUICC class", + quicc_methods, + sizeof(struct scc_softc), + .cl_channels = 4, + .cl_class = SCC_CLASS_QUICC, + .cl_modes = SCC_MODE_ASYNC | SCC_MODE_BISYNC | SCC_MODE_HDLC, + .cl_range = 0, +}; + +static int +quicc_bfe_attach(struct scc_softc *sc, int reset) +{ + struct scc_bas *bas; + + bas = &sc->sc_bas; + return (0); +} + +static int +quicc_bfe_enabled(struct scc_softc *sc, struct scc_chan *ch) +{ + struct scc_bas *bas; + int unit; + uint16_t val0, val1; + + bas = &sc->sc_bas; + unit = ch->ch_nr - 1; + val0 = quicc_read2(bas, QUICC_REG_SCC_TODR(unit)); + quicc_write2(bas, QUICC_REG_SCC_TODR(unit), ~val0); + val1 = quicc_read2(bas, QUICC_REG_SCC_TODR(unit)); + quicc_write2(bas, QUICC_REG_SCC_TODR(unit), val0); + return (((val0 | val1) == 0x8000) ? 1 : 0); +} + +static int +quicc_bfe_iclear(struct scc_softc *sc, struct scc_chan *ch) +{ + + return (0); +} + +static int +quicc_bfe_ipend(struct scc_softc *sc) +{ + struct scc_bas *bas; + struct scc_chan *ch; + int c, ipend; + uint16_t scce; + + bas = &sc->sc_bas; + ipend = 0; + for (c = 0; c < 4; c++) { + ch = &sc->sc_chan[c]; + if (!ch->ch_enabled) + continue; + ch->ch_ipend = 0; + mtx_lock_spin(&sc->sc_hwmtx); + scce = quicc_read2(bas, QUICC_REG_SCC_SCCE(c)); + quicc_write2(bas, QUICC_REG_SCC_SCCE(c), ~0); + mtx_unlock_spin(&sc->sc_hwmtx); + if (scce & 0x0001) + ch->ch_ipend |= SER_INT_RXREADY; + if (scce & 0x0002) + ch->ch_ipend |= SER_INT_TXIDLE; + if (scce & 0x0004) + ch->ch_ipend |= SER_INT_OVERRUN; + if (scce & 0x0020) + ch->ch_ipend |= SER_INT_BREAK; + /* XXX SIGNALS */ + ipend |= ch->ch_ipend; + } + return (ipend); +} + +static int +quicc_bfe_probe(struct scc_softc *sc) +{ + struct scc_bas *bas; + + bas = &sc->sc_bas; + return (0); +} |