Reduce spin wait time consumed in GMII register access routine.

There were a couple of attempts in the past to reduce it since it
took more than 1ms. Because mii_tick() periodically polls link
status, waiting more than 1ms for each GMII register access was
overkill. Unfortunately all previous attempts were failed with
various ways on different controllers.
This time, add additional 20us dealy at the end of GMII register
access which seems to requirement of all RealTek controllers to
issue next GMII register access request. This is the same way what
Linux does.

1 files changed, 12 insertions, 4 deletions

diff --git a/sys/dev/re/if_re.c b/sys/dev/re/if_re.c
index 95983af..8f8cfa1 100644
--- a/sys/dev/re/if_re.c
+++ b/sys/dev/re/if_re.c
@@ -423,13 +423,12 @@ re_gmii_readreg(device_t dev, int phy, int reg)
 	}
 
 	CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
-	DELAY(1000);
 
 	for (i = 0; i < RL_PHY_TIMEOUT; i++) {
 		rval = CSR_READ_4(sc, RL_PHYAR);
 		if (rval & RL_PHYAR_BUSY)
 			break;
-		DELAY(100);
+		DELAY(25);
 	}
 
 	if (i == RL_PHY_TIMEOUT) {
@@ -437,6 +436,11 @@ re_gmii_readreg(device_t dev, int phy, int reg)
 		return (0);
 	}
 
+	/*
+	 * Controller requires a 20us delay to process next MDIO request.
+	 */
+	DELAY(20);
+
 	return (rval & RL_PHYAR_PHYDATA);
 }
 
@@ -451,13 +455,12 @@ re_gmii_writereg(device_t dev, int phy, int reg, int data)
 
 	CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
 	    (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
-	DELAY(1000);
 
 	for (i = 0; i < RL_PHY_TIMEOUT; i++) {
 		rval = CSR_READ_4(sc, RL_PHYAR);
 		if (!(rval & RL_PHYAR_BUSY))
 			break;
-		DELAY(100);
+		DELAY(25);
 	}
 
 	if (i == RL_PHY_TIMEOUT) {
@@ -465,6 +468,11 @@ re_gmii_writereg(device_t dev, int phy, int reg, int data)
 		return (0);
 	}
 
+	/*
+	 * Controller requires a 20us delay to process next MDIO request.
+	 */
+	DELAY(20);
+
 	return (0);
 }