Major ppbus updates from the author.

 - ppbus now supports PLIP via the if_plip driver
 - ieee1284 infrastructure added, including parallel-port PnP
 - port microsequencer added, for scripting the sort of port I/O
   that is common with parallel devices without endless calls up and down
   through the driver structure.
 - improved bus ownership behaviour among the ppbus-using drivers.
 - improved I/O chipset feature detection

The vpo driver is now implemented using the microsequencer, leading to
some performance improvements as well as providing an extensive example
of its use.

Reviewed by:	msmith
Submitted by:	Nicolas Souchu <Nicolas.Souchu@prism.uvsq.fr>

1 files changed, 54 insertions, 25 deletions

diff --git a/sys/dev/ppc/ppcreg.h b/sys/dev/ppc/ppcreg.h
index 7ab6189e..27ab1a1 100644
--- a/sys/dev/ppc/ppcreg.h
+++ b/sys/dev/ppc/ppcreg.h
@@ -23,23 +23,25 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: ppcreg.h,v 1.1 1997/08/14 14:01:36 msmith Exp $
+ *	$Id: ppcreg.h,v 1.2 1997/08/16 14:07:26 msmith Exp $
  *
  */
-#ifndef __PPC_H
-#define __PPC_H
+#ifndef __PPCREG_H
+#define __PPCREG_H
 
 /*
  * Parallel Port Chipset type.
  */
-#define SMC_UNKNOWN	0x0
+#define SMC_LIKE	0x0
 #define SMC_37C665GT	0x1
 #define SMC_37C666GT	0x2
-#define NS_UNKNOWN	0x3
-#define NS_PC87332	0x4
-#define NS_PC87306	0x5
-#define INTEL_820191AA	0x6
-#define GENERIC		0x7
+#define NS_PC87332	0x3
+#define NS_PC87306	0x4
+#define INTEL_820191AA	0x5	/* XXX not implemented */
+#define GENERIC		0x6
+#define WINB_W83877F	0x7
+#define WINB_W83877AF	0x8
+#define WINB_UNKNOWN	0x9
 
 /*
  * Generic structure to hold parallel port chipset info.
@@ -49,10 +51,13 @@ struct ppc_data {
 	int ppc_unit;
 	int ppc_type;
 
+	int ppc_mode;		/* chipset current mode */
+	int ppc_avm;		/* chipset available modes */
+
 #define ppc_base ppc_link.base
-#define ppc_mode ppc_link.mode
 #define ppc_epp ppc_link.epp_protocol
 #define ppc_irq ppc_link.id_irq
+#define ppc_subm ppc_link.submicroseq
 
 	unsigned char ppc_flags;
 
@@ -60,11 +65,6 @@ struct ppc_data {
 };
 
 /*
- * Parallel Port Chipset errors.			XXX
- */
-#define PPC_ENOPORT		9
-
-/*
  * Parallel Port Chipset registers.
  */
 #define PPC_SPP_DTR	0	/* SPP data register */
@@ -74,12 +74,12 @@ struct ppc_data {
 #define PPC_ECP_FIFO	0x400	/* ECP fifo register */
 #define PPC_ECP_ECR	0x402	/* ECP extended control register */
 
-#define r_dtr(ppc) inb((ppc)->ppc_base + PPC_SPP_DTR)
-#define r_str(ppc) inb((ppc)->ppc_base + PPC_SPP_STR)
-#define r_ctr(ppc) inb((ppc)->ppc_base + PPC_SPP_CTR)
-#define r_epp(ppc) inb((ppc)->ppc_base + PPC_EPP_DATA)
-#define r_ecr(ppc) inb((ppc)->ppc_base + PPC_ECP_ECR)
-#define r_fifo(ppc) inb((ppc)->ppc_base + PPC_ECP_FIFO)
+#define r_dtr(ppc) ((char)inb((ppc)->ppc_base + PPC_SPP_DTR))
+#define r_str(ppc) ((char)inb((ppc)->ppc_base + PPC_SPP_STR))
+#define r_ctr(ppc) ((char)inb((ppc)->ppc_base + PPC_SPP_CTR))
+#define r_epp(ppc) ((char)inb((ppc)->ppc_base + PPC_EPP_DATA))
+#define r_ecr(ppc) ((char)inb((ppc)->ppc_base + PPC_ECP_ECR))
+#define r_fifo(ppc) ((char)inb((ppc)->ppc_base + PPC_ECP_FIFO))
 
 #define w_dtr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_DTR, byte)
 #define w_str(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_STR, byte)
@@ -111,7 +111,7 @@ struct ppc_data {
 #define PC873_SID	0x08
 
 /*
- * Register defines for the SMC FDC37C66xGT parts.
+ * Register defines for the SMC FDC37C66xGT parts
  */
 
 /* Init codes */
@@ -124,9 +124,9 @@ struct ppc_data {
 
 /* Bits */
 #define SMC_CR1_ADDR	0x3		/* bit 0 and 1 */
-#define SMC_CR1_MODE	0x8		/* bit 3 */
+#define SMC_CR1_MODE	(1<<3)		/* bit 3 */
 #define SMC_CR4_EMODE	0x3		/* bits 0 and 1 */
-#define SMC_CR4_EPPTYPE	0x40		/* bit 6 */
+#define SMC_CR4_EPPTYPE	(1<<6)		/* bit 6 */
 
 /* Extended modes */
 #define SMC_SPP		0x0		/* SPP */
@@ -134,5 +134,34 @@ struct ppc_data {
 #define SMC_ECP		0x2 		/* ECP */
 #define SMC_ECPEPP	0x3		/* ECP and EPP */
 
-#endif
+/*
+ * Register defines for the Winbond W83877F parts
+ */
 
+#define WINB_W83877F_ID		0xa
+#define WINB_W83877AF_ID	0xb
+
+/* Configuration bits */
+#define WINB_HEFERE	(1<<5)		/* CROC bit 5 */
+#define WINB_HEFRAS	(1<<0)		/* CR16 bit 0 */
+
+#define WINB_PNPCVS	(1<<2)		/* CR16 bit 2 */
+#define WINB_CHIPID	0xf		/* CR9 bits 0-3 */
+
+#define WINB_PRTMODS0	(1<<2)		/* CR0 bit 2 */
+#define WINB_PRTMODS1	(1<<3)		/* CR0 bit 3 */
+#define WINB_PRTMODS2	(1<<7)		/* CR9 bit 7 */
+
+/* W83877F modes: CR9/bit7 | CR0/bit3 | CR0/bit2 */
+#define WINB_W83757	0x0
+#define WINB_EXTFDC	0x4
+#define WINB_EXTADP	0x8
+#define WINB_EXT2FDD	0xc
+#define WINB_JOYSTICK	0x80
+
+#define WINB_PARALLEL	0x80
+#define WINB_EPP_SPP	0x4
+#define WINB_ECP	0x8
+#define WINB_ECP_EPP	0xc
+
+#endif