Major ppbus commit with:

	+ ECP parallel port chipset FIFO detection
	+ DMA+FIFO parallel I/O handled as chipset specific
	+ nlpt updated in order to use the above enhanced parallel I/O.
	  Use 'lptcontrol -e' to use enhanced I/O
	+ Various options documented in LINT
	+ Full IEEE1284 NIBBLE and BYTE modes support. See ppbus(4) for
	  an overview of the IEEE1284 standard
	+ Detection of PnP parallel devices at boot
	+ Read capability added to nlpt driver to get IEEE1284 compliant
	  printer status with a simple 'cat /dev/lpt0'
	+ IEEE1284 peripheral emulation added to BYTE mode. Two computers
	  may dialog according to IEEE1284 signaling method.
	  See PERIPH_1284 option and /sys/dev/ppbus/ppi.c

All this code is supposed to provide basic functions for IEEE1284 programming.
ppi.c and nlpt.c may act as examples.

1 files changed, 38 insertions, 11 deletions

diff --git a/sys/dev/ppbus/ppb_base.c b/sys/dev/ppbus/ppb_base.c
index 7555b24..83fc26e 100644
--- a/sys/dev/ppbus/ppb_base.c
+++ b/sys/dev/ppbus/ppb_base.c
@@ -23,12 +23,13 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: ppb_base.c,v 1.4 1998/08/03 19:14:31 msmith Exp $
+ *	$Id: ppb_base.c,v 1.5 1998/09/13 18:26:26 nsouch Exp $
  *
  */
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
+#include <machine/clock.h>
 
 #include <dev/ppbus/ppbconf.h>
 
@@ -70,28 +71,39 @@ int
 ppb_poll_device(struct ppb_device *dev, int max,
 		char mask, char status, int how)
 {
-	int i, error;
+	int i, j, error;
+	char r;
+
+	/* try at least up to 10ms */
+	for (j = 0; j < ((how & PPB_POLL) ? max : 1); j++) {
+		for (i = 0; i < 10000; i++) {
+			r = ppb_rstr(dev);
+			DELAY(1);
+			if ((r & mask) == status)
+				return (0);
+		}
+	}
 
-	for (i = 0; i < max; i++) {
+	if (!(how & PPB_POLL)) {
+	   for (i = 0; max == PPB_FOREVER || i < max-1; i++) {
 		if ((ppb_rstr(dev) & mask) == status)
 			return (0);
 
 		switch (how) {
 		case PPB_NOINTR:
 			/* wait 10 ms */
-			if ((error = tsleep((caddr_t)dev, PPBPRI,
-						"ppbpoll", hz/100)))
-				return (error);
+			tsleep((caddr_t)dev, PPBPRI, "ppbpoll", hz/100);
 			break;
 
 		case PPB_INTR:
 		default:
 			/* wait 10 ms */
 			if ((error = tsleep((caddr_t)dev, PPBPRI | PCATCH,
-						"ppbpoll", hz/100)))
+					"ppbpoll", hz/100)) != EWOULDBLOCK)
 				return (error);
 			break;
 		}
+	   }
 	}
 
 	return (EWOULDBLOCK);
@@ -108,16 +120,31 @@ ppb_set_mode(struct ppb_device *dev, int mode)
 	struct ppb_data *ppb = dev->ppb;
 	int old_mode = ppb_get_mode(dev);
 
-	if ((*ppb->ppb_link->adapter->setmode)(dev->id_unit, mode))
+	if ((*ppb->ppb_link->adapter->setmode)(
+			ppb->ppb_link->adapter_unit, mode))
 		return (-1);
 
 	/* XXX yet device mode = ppbus mode = chipset mode */
-	dev->mode = ppb->mode = mode;
+	dev->mode = ppb->mode = (mode & PPB_MASK);
 
 	return (old_mode);
 }
 
 /*
+ * ppb_write()
+ *
+ * Write charaters to the port
+ */
+int
+ppb_write(struct ppb_device *dev, char *buf, int len, int how)
+{
+	struct ppb_data *ppb = dev->ppb;
+
+	return (ppb->ppb_link->adapter->write(ppb->ppb_link->adapter_unit,
+						buf, len, how));
+}
+
+/*
  * ppb_reset_epp_timeout()
  *
  * Reset the EPP timeout bit in the status register
@@ -130,7 +157,7 @@ ppb_reset_epp_timeout(struct ppb_device *dev)
 	if (ppb->ppb_owner != dev)
 		return (EACCES);
 
-	(*ppb->ppb_link->adapter->reset_epp_timeout)(dev->id_unit);
+	(*ppb->ppb_link->adapter->reset_epp_timeout)(ppb->ppb_link->adapter_unit);
 
 	return (0);
 }
@@ -148,7 +175,7 @@ ppb_ecp_sync(struct ppb_device *dev)
 	if (ppb->ppb_owner != dev)
 		return (EACCES);
 
-	(*ppb->ppb_link->adapter->ecp_sync)(dev->id_unit);
+	(*ppb->ppb_link->adapter->ecp_sync)(ppb->ppb_link->adapter_unit);
 
 	return (0);
 }