Add support for Enhanced Allocation in pciconf

 * Modified pciconf to print EA capability structure
 * Added register description to pcireg.h

Obtained from:         Semihalf
Sponsored by:          Cavium
Approved by:           cognet (mentor)
Reviewed by:           jhb
Differential revision: https://reviews.freebsd.org/D5440

1 files changed, 47 insertions, 0 deletions

diff --git a/sys/dev/pci/pcireg.h b/sys/dev/pci/pcireg.h
index 85df48c..68b5378 100644
--- a/sys/dev/pci/pcireg.h
+++ b/sys/dev/pci/pcireg.h
@@ -146,6 +146,7 @@
 #define	PCIY_MSIX	0x11	/* MSI-X */
 #define	PCIY_SATA	0x12	/* SATA */
 #define	PCIY_PCIAF	0x13	/* PCI Advanced Features */
+#define	PCIY_EA		0x14	/* PCI Extended Allocation */
 
 /* Extended Capability Register Fields */
 
@@ -586,6 +587,52 @@
 #define	PCIR_MSI_MASK		0x10
 #define	PCIR_MSI_PENDING	0x14
 
+/* PCI Enhanced Allocation registers */
+#define	PCIR_EA_NUM_ENT		2	/* Number of Capability Entries */
+#define	PCIM_EA_NUM_ENT_MASK	0x3f	/* Num Entries Mask */
+#define	PCIR_EA_FIRST_ENT	4	/* First EA Entry in List */
+#define	PCIR_EA_FIRST_ENT_BRIDGE	8	/* First EA Entry for Bridges */
+#define	PCIM_EA_ES		0x00000007	/* Entry Size */
+#define	PCIM_EA_BEI		0x000000f0	/* BAR Equivalent Indicator */
+#define	PCIM_EA_BEI_OFFSET	4
+/* 0-5 map to BARs 0-5 respectively */
+#define	PCIM_EA_BEI_BAR_0	0
+#define	PCIM_EA_BEI_BAR_5	5
+#define	PCIM_EA_BEI_BAR(x)	(((x) >> PCIM_EA_BEI_OFFSET) & 0xf)
+#define	PCIM_EA_BEI_BRIDGE	0x6	/* Resource behind bridge */
+#define	PCIM_EA_BEI_ENI		0x7	/* Equivalent Not Indicated */
+#define	PCIM_EA_BEI_ROM		0x8	/* Expansion ROM */
+/* 9-14 map to VF BARs 0-5 respectively */
+#define	PCIM_EA_BEI_VF_BAR_0	9
+#define	PCIM_EA_BEI_VF_BAR_5	14
+#define	PCIM_EA_BEI_RESERVED	0xf	/* Reserved - Treat like ENI */
+#define	PCIM_EA_PP		0x0000ff00	/* Primary Properties */
+#define	PCIM_EA_PP_OFFSET	8
+#define	PCIM_EA_SP_OFFSET	16
+#define	PCIM_EA_SP		0x00ff0000	/* Secondary Properties */
+#define	PCIM_EA_P_MEM		0x00	/* Non-Prefetch Memory */
+#define	PCIM_EA_P_MEM_PREFETCH	0x01	/* Prefetchable Memory */
+#define	PCIM_EA_P_IO		0x02	/* I/O Space */
+#define	PCIM_EA_P_VF_MEM_PREFETCH	0x03	/* VF Prefetchable Memory */
+#define	PCIM_EA_P_VF_MEM	0x04	/* VF Non-Prefetch Memory */
+#define	PCIM_EA_P_BRIDGE_MEM	0x05	/* Bridge Non-Prefetch Memory */
+#define	PCIM_EA_P_BRIDGE_MEM_PREFETCH	0x06	/* Bridge Prefetchable Memory */
+#define	PCIM_EA_P_BRIDGE_IO	0x07	/* Bridge I/O Space */
+/* 0x08-0xfc reserved */
+#define	PCIM_EA_P_MEM_RESERVED	0xfd	/* Reserved Memory */
+#define	PCIM_EA_P_IO_RESERVED	0xfe	/* Reserved I/O Space */
+#define	PCIM_EA_P_UNAVAILABLE	0xff	/* Entry Unavailable */
+#define	PCIM_EA_WRITABLE	0x40000000	/* Writable: 1 = RW, 0 = HwInit */
+#define	PCIM_EA_ENABLE		0x80000000	/* Enable for this entry */
+#define	PCIM_EA_BASE		4	/* Base Address Offset */
+#define	PCIM_EA_MAX_OFFSET	8	/* MaxOffset (resource length) */
+/* bit 0 is reserved */
+#define	PCIM_EA_IS_64		0x00000002	/* 64-bit field flag */
+#define	PCIM_EA_FIELD_MASK	0xfffffffc	/* For Base & Max Offset */
+/* Bridge config register */
+#define	PCIM_EA_SEC_NR(reg)	((reg) & 0xff)
+#define	PCIM_EA_SUB_NR(reg)	(((reg) >> 8) & 0xff)
+
 /* PCI-X definitions */
 
 /* For header type 0 devices */