Completely replace the PCI bus driver code to make it better reflect

reality. There will be a new call interface, but for now the file
pci_compat.c (which is to be deleted, after all drivers are converted)
provides an emulation of the old PCI bus driver functions. The only
change that might be visible to drivers is, that the type pcici_t
(which had been meant to be just a handle, whose exact definition
should not be relied on), has been converted into a pcicfgregs* .

The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t
and has been converted to just call the PCI drivers functions to access
configuration space register, instead of inventing its own ...

This code is by no means complete, but assumed to be fully operational,
and brings the official code base more in line with my development code.

A new generic device descriptor data type has to be agreed on. The PCI
code will then use that data type to provide new functionality:

1) userconfig support
2) "wired" PCI devices
3) conflicts checking against ISA/EISA
4) maps will depend on the command register enable bits
5) PCI to Anything bridges can be defined as devices,
   and are probed like any "standard" PCI device.

The following features are currently missing, but will be added back,
soon:

1) unknown device probe message
2) suppression of "mirrored" devices caused by ancient, broken chip-sets

This code relies on generic shared interrupt support just commited to
kern_intr.c (plus the modifications of isa.c and isa_device.h).

1 files changed, 244 insertions, 202 deletions

diff --git a/sys/dev/pci/pcireg.h b/sys/dev/pci/pcireg.h
index 05e3c07..cd5c6e8 100644
--- a/sys/dev/pci/pcireg.h
+++ b/sys/dev/pci/pcireg.h
@@ -1,208 +1,250 @@
-/**************************************************************************
-**
-**  $Id: pcireg.h,v 1.13 1997/04/20 06:57:43 phk Exp $
-**
-**  Names for PCI configuration space registers.
-**
-** Copyright (c) 1994 Wolfgang Stanglmeier.  All rights reserved.
-**
-**
-** Redistribution and use in source and binary forms, with or without
-** modification, are permitted provided that the following conditions
-** are met:
-** 1. Redistributions of source code must retain the above copyright
-**    notice, this list of conditions and the following disclaimer.
-** 2. Redistributions in binary form must reproduce the above copyright
-**    notice, this list of conditions and the following disclaimer in the
-**    documentation and/or other materials provided with the distribution.
-** 3. The name of the author may not be used to endorse or promote products
-**    derived from this software without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-***************************************************************************
-*/
-
-#ifndef __PCI_REG_H__
-#define __PCI_REG_H__ "pl2 95/03/21"
-
+#ifndef PCI_COMPAT
+#define PCI_COMPAT
+#endif
 /*
-** Device identification register; contains a vendor ID and a device ID.
-** We have little need to distinguish the two parts.
-*/
-#define	PCI_ID_REG			0x00
+ * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice unmodified, this list of conditions, and the following
+ *    disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $Id$
+ *
+ */
 
 /*
-** Command and status register.
-*/
-#define	PCI_COMMAND_STATUS_REG		0x04
-
+ * PCIM_xxx: mask to locate subfield in register
+ * PCIR_xxx: config register offset
+ * PCIC_xxx: device class
+ * PCIS_xxx: device subclass
+ * PCIP_xxx: device programming interface
+ * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
+ * PCID_xxx: device ID
+ */
+
+/* some PCI bus constants */
+
+#define PCI_BUSMAX	255
+#define PCI_SLOTMAX	31
+#define PCI_FUNCMAX	7
+#define PCI_REGMAX	255
+
+/* PCI config header registers for all devices */
+
+#define PCIR_DEVVENDOR	0x00
+#define PCIR_VENDOR	0x00
+#define PCIR_DEVICE	0x02
+#define PCIR_COMMAND	0x04
+#define PCIR_STATUS	0x06
+#define PCIR_REVID	0x08
+#define PCIR_PROGIF	0x09
+#define PCIR_SUBCLASS	0x0a
+#define PCIR_CLASS	0x0b
+#define PCIR_CACHELNSZ	0x0c
+#define PCIR_LATTIMER	0x0d
+#define PCIR_HEADERTYPE	0x0e
+#define PCIM_MFDEV		0x80
+#define PCIR_BIST	0x0f
+
+/* config registers for header type 0 devices */
+
+#define PCIR_MAPS	0x10
+#define PCIR_CARDBUSCIS	0x28
+#define PCIR_SUBVEND_0	0x2c
+#define PCIR_SUBDEV_0	0x2e
+#define PCIR_INTLINE	0x3c
+#define PCIR_INTPIN	0x3d
+#define PCIR_MINGNT	0x3e
+#define PCIR_MAXLAT	0x3f
+
+/* config registers for header type 1 devices */
+
+#define PCIR_SECSTAT_1	0 /**/
+
+#define PCIR_PRIBUS_1	0x18
+#define PCIR_SECBUS_1	0x19
+#define PCIR_SUBBUS_1	0x1a
+#define PCIR_SECLAT_1	0x1b
+
+#define PCIR_IOBASEL_1	0x1c
+#define PCIR_IOLIMITL_1	0x1d
+#define PCIR_IOBASEH_1	0 /**/
+#define PCIR_IOLIMITH_1	0 /**/
+
+#define PCIR_MEMBASE_1	0x20
+#define PCIR_MEMLIMIT_1	0x22
+
+#define PCIR_PMBASEL_1	0x24
+#define PCIR_PMLIMITL_1	0x26
+#define PCIR_PMBASEH_1	0 /**/
+#define PCIR_PMLIMITH_1	0 /**/
+
+#define PCIR_BRIDGECTL_1 0 /**/
+
+#define PCIR_SUBVEND_1	0x34
+#define PCIR_SUBDEV_1	0x36
+
+/* config registers for header type 2 devices */
+
+#define PCIR_SECSTAT_2	0x16
+
+#define PCIR_PRIBUS_2	0x18
+#define PCIR_SECBUS_2	0x19
+#define PCIR_SUBBUS_2	0x1a
+#define PCIR_SECLAT_2	0x1b
+
+#define PCIR_MEMBASE0_2	0x1c
+#define PCIR_MEMLIMIT0_2 0x20
+#define PCIR_MEMBASE1_2	0x24
+#define PCIR_MEMLIMIT1_2 0x28
+#define PCIR_IOBASE0_2	0x2c
+#define PCIR_IOLIMIT0_2	0x30
+#define PCIR_IOBASE1_2	0x34
+#define PCIR_IOLIMIT1_2	0x38
+
+#define PCIR_BRIDGECTL_2 0x3e
+
+#define PCIR_SUBVEND_2	0x40
+#define PCIR_SUBDEV_2	0x42
+
+#define PCIR_PCCARDIF_2	0x44
+
+/* PCI device class, subclass and programming interface definitions */
+
+#define PCIC_OLD	0x00
+#define PCIS_OLD_NONVGA		0x00
+#define PCIS_OLD_VGA		0x01
+
+#define PCIC_STORAGE	0x01
+#define PCIS_STORAGE_SCSI	0x00
+#define PCIS_STORAGE_IDE	0x01
+#define PCIP_STORAGE_IDE_MODEPRIM	0x01
+#define PCIP_STORAGE_IDE_PROGINDPRIM	0x02
+#define PCIP_STORAGE_IDE_MODESEC	0x04
+#define PCIP_STORAGE_IDE_PROGINDSEC	0x08
+#define PCIP_STORAGE_IDE_MASTERDEV	0x80
+#define PCIS_STORAGE_FLOPPY	0x02
+#define PCIS_STORAGE_IPI	0x03
+#define PCIS_STORAGE_RAID	0x04
+#define PCIS_STORAGE_OTHER	0x80
+
+#define PCIC_NETWORK	0x02
+#define PCIS_NETWORK_ETHERNET	0x00
+#define PCIS_NETWORK_TOKENRING	0x01
+#define PCIS_NETWORK_FDDI	0x02
+#define PCIS_NETWORK_ATM	0x03
+#define PCIS_NETWORK_OTHER	0x80
+
+#define PCIC_DISPLAY	0x03
+#define PCIS_DISPLAY_VGA	0x00
+#define PCIS_DISPLAY_XGA	0x01
+#define PCIS_DISPLAY_OTHER	0x80
+
+#define PCIC_MULTIMEDIA	0x04
+#define PCIS_MULTIMEDIA_VIDEO	0x00
+#define PCIS_MULTIMEDIA_AUDIO	0x01
+#define PCIS_MULTIMEDIA_OTHER	0x80
+
+#define PCIC_MEMORY	0x05
+#define PCIS_MEMORY_RAM		0x00
+#define PCIS_MEMORY_FLASH	0x01
+#define PCIS_MEMORY_OTHER	0x80
+
+#define PCIC_BRIDGE	0x06
+#define PCIS_BRDIGE_HOST	0x00
+#define PCIS_BRIDGE_ISA		0x01
+#define PCIS_BRIDGE_EISA	0x02
+#define PCIS_BRIDGE_MCA		0x03
+#define PCIS_BRIDGE_PCI		0x04
+#define PCIS_BRIDGE_PCMCIA	0x05
+#define PCIS_BRIDGE_NUBUS	0x06
+#define PCIS_BRIDGE_CARDBUS	0x07
+#define PCIS_BRIDGE_OTHER	0x80
+
+#define PCIC_SIMPLECOMM	0x07
+#define PCIS_SIMPLECOMM_UART	0x00
+#define PCIS_SIMPLECOMM_PAR	0x01
+#define PCIS_SIMPLECOMM_OTHER	0x80
+
+#define PCIC_BASEPERIPH	0x08
+#define PCIS_BASEPERIPH_PIC	0x00
+#define PCIS_BASEPERIPH_DMA	0x01
+#define PCIS_BASEPERIPH_TIMER	0x02
+#define PCIS_BASEPERIPH_RTC	0x03
+#define PCIS_BASEPERIPH_OTHER	0x80
+
+#define PCIC_INPUTDEV	0x09
+#define PCIS_INPUTDEV_KEYBOARD	0x00
+#define PCIS_INPUTDEV_DIGITIZER	0x01
+#define PCIS_INPUTDEV_MOUSE	0x02
+#define PCIS_INPUTDEV_OTHER	0x80
+
+#define PCIC_DOCKING	0x0a
+#define PCIS_DOCKING_GENERIC	0x00
+#define PCIS_DOCKING_OTHER	0x80
+
+#define PCIC_PROCESSOR	0x0b
+#define PCIS_PROCESSOR_386	0x00
+#define PCIS_PROCESSOR_486	0x01
+#define PCIS_PROCESSOR_PENTIUM	0x02
+#define PCIS_PROCESSOR_ALPHA	0x10
+#define PCIS_PROCESSOR_POWERPC	0x20
+#define PCIS_PROCESSOR_COPROC	0x40
+
+#define PCIC_SERIALBUS	0x0c
+#define PCIS_SERIALBUS_FW	0x00
+#define PCIS_SERIALBUS_ACCESS	0x01
+#define PCIS_SERIALBUS_SSA	0x02
+#define PCIS_SERIALBUS_USB	0x03
+#define PCIS_SERIALBUS_FC	0x04
+#define PCIS_SERIALBUS
+#define PCIS_SERIALBUS
+
+#define PCIC_OTHER	0xff
+
+/* some PCI vendor definitions (only used to identify ancient devices !!! */
+
+#define PCIV_INTEL	0x8086
+
+#define PCID_INTEL_SATURN	0x0483
+#define PCID_INTEL_ORION	0x84c4
+
+/* for compatibility to FreeBSD-2.2 version of PCI code */
+
+#ifdef PCI_COMPAT
+
+#define PCI_ID_REG		0x00
+#define PCI_COMMAND_STATUS_REG	0x04
 #define	PCI_COMMAND_IO_ENABLE		0x00000001
-#define	PCI_COMMAND_MEM_ENABLE		0x00000002
-#define	PCI_COMMAND_MASTER_ENABLE	0x00000004
-#define	PCI_COMMAND_SPECIAL_ENABLE	0x00000008
-#define	PCI_COMMAND_INVALIDATE_ENABLE	0x00000010
-#define	PCI_COMMAND_PALETTE_ENABLE	0x00000020
-#define	PCI_COMMAND_PARITY_ENABLE	0x00000040
-#define	PCI_COMMAND_STEPPING_ENABLE	0x00000080
-#define	PCI_COMMAND_SERR_ENABLE		0x00000100
-#define	PCI_COMMAND_BACKTOBACK_ENABLE	0x00000200
-
-#define	PCI_STATUS_BACKTOBACK_OKAY	0x00800000
-#define	PCI_STATUS_PARITY_ERROR		0x01000000
-#define	PCI_STATUS_DEVSEL_FAST		0x00000000
-#define	PCI_STATUS_DEVSEL_MEDIUM	0x02000000
-#define	PCI_STATUS_DEVSEL_SLOW		0x04000000
-#define	PCI_STATUS_DEVSEL_MASK		0x06000000
-#define	PCI_STATUS_TARGET_TARGET_ABORT	0x08000000
-#define	PCI_STATUS_MASTER_TARGET_ABORT	0x10000000
-#define	PCI_STATUS_MASTER_ABORT		0x20000000
-#define	PCI_STATUS_SPECIAL_ERROR	0x40000000
-#define	PCI_STATUS_PARITY_DETECT	0x80000000
-
-/*
-** Class register; defines basic type of device.
-*/
-#define	PCI_CLASS_REG			0x08
-
-#define	PCI_CLASS_MASK			0xff000000
-#define	PCI_SUBCLASS_MASK		0x00ff0000
-
-/* base classes */
-#define	PCI_CLASS_PREHISTORIC		0x00000000
-#define	PCI_CLASS_MASS_STORAGE		0x01000000
-#define	PCI_CLASS_NETWORK		0x02000000
-#define	PCI_CLASS_DISPLAY		0x03000000
-#define	PCI_CLASS_MULTIMEDIA		0x04000000
-#define	PCI_CLASS_MEMORY		0x05000000
-#define	PCI_CLASS_BRIDGE		0x06000000
-#define	PCI_CLASS_UNDEFINED		0xff000000
-
-/* 0x00 prehistoric subclasses */
-#define	PCI_SUBCLASS_PREHISTORIC_MISC	0x00000000
-#define	PCI_SUBCLASS_PREHISTORIC_VGA	0x00010000
-
-/* 0x01 mass storage subclasses */
-#define	PCI_SUBCLASS_MASS_STORAGE_SCSI	0x00000000
-#define	PCI_SUBCLASS_MASS_STORAGE_IDE	0x00010000
-#define	PCI_SUBCLASS_MASS_STORAGE_FLOPPY	0x00020000
-#define	PCI_SUBCLASS_MASS_STORAGE_IPI	0x00030000
-#define	PCI_SUBCLASS_MASS_STORAGE_MISC	0x00800000
-
-/* 0x02 network subclasses */
-#define	PCI_SUBCLASS_NETWORK_ETHERNET	0x00000000
-#define	PCI_SUBCLASS_NETWORK_TOKENRING	0x00010000
-#define	PCI_SUBCLASS_NETWORK_FDDI	0x00020000
-#define	PCI_SUBCLASS_NETWORK_MISC	0x00800000
-
-/* 0x03 display subclasses */
-#define	PCI_SUBCLASS_DISPLAY_VGA	0x00000000
-#define	PCI_SUBCLASS_DISPLAY_XGA	0x00010000
-#define	PCI_SUBCLASS_DISPLAY_MISC	0x00800000
-
-/* 0x04 multimedia subclasses */
-#define	PCI_SUBCLASS_MULTIMEDIA_VIDEO	0x00000000
-#define	PCI_SUBCLASS_MULTIMEDIA_AUDIO	0x00010000
-#define	PCI_SUBCLASS_MULTIMEDIA_MISC	0x00800000
-
-/* 0x05 memory subclasses */
-#define	PCI_SUBCLASS_MEMORY_RAM		0x00000000
-#define	PCI_SUBCLASS_MEMORY_FLASH	0x00010000
-#define	PCI_SUBCLASS_MEMORY_MISC	0x00800000
-
-/* 0x06 bridge subclasses */
-#define	PCI_SUBCLASS_BRIDGE_HOST	0x00000000
-#define	PCI_SUBCLASS_BRIDGE_ISA		0x00010000
-#define	PCI_SUBCLASS_BRIDGE_EISA	0x00020000
-#define	PCI_SUBCLASS_BRIDGE_MC		0x00030000
-#define	PCI_SUBCLASS_BRIDGE_PCI		0x00040000
-#define	PCI_SUBCLASS_BRIDGE_PCMCIA	0x00050000
-#define	PCI_SUBCLASS_BRIDGE_CARDBUS	0x00070000
-#define	PCI_SUBCLASS_BRIDGE_MISC	0x00800000
-
-/*
-** Header registers
-*/
-#define PCI_HEADER_MISC			0x0c
-
-#define PCI_HEADER_MULTIFUNCTION	0x00800000
-
-/*
-** Mapping registers
-*/
-#define	PCI_MAP_REG_START		0x10
-#define	PCI_MAP_REG_END			0x28
-
-#define	PCI_MAP_MEMORY			0x00000000
+#define PCI_CLASS_REG		0x08
+#define PCI_CLASS_MASK			0xff000000
+#define PCI_SUBCLASS_MASK		0x00ff0000
+#define PCI_CLASS_PREHISTORIC		0x00000000
+#define PCI_SUBCLASS_PREHISTORIC_VGA		0x00010000
+#define PCI_CLASS_DISPLAY		0x03000000
+#define PCI_SUBCLASS_DISPLAY_VGA		0x00000000
+#define PCI_CLASS_BRIDGE		0x06000000
+#define PCI_MAP_REG_START	0x10
+#define	PCI_MAP_REG_END		0x28
 #define	PCI_MAP_IO			0x00000001
+#define	PCI_INTERRUPT_REG	0x3c
 
-#define	PCI_MAP_MEMORY_TYPE_32BIT	0x00000000
-#define	PCI_MAP_MEMORY_TYPE_32BIT_1M	0x00000002
-#define	PCI_MAP_MEMORY_TYPE_64BIT	0x00000004
-#define	PCI_MAP_MEMORY_TYPE_MASK	0x00000006
-#define	PCI_MAP_MEMORY_CACHABLE		0x00000008
-#define	PCI_MAP_MEMORY_ADDRESS_MASK	0xfffffff0
-
-#define	PCI_MAP_IO_ADDRESS_MASK         0xfffffffc
-/*
-** PCI-PCI bridge mapping registers
-*/
-#define PCI_PCI_BRIDGE_BUS_REG		0x18
-#define PCI_PCI_BRIDGE_IO_REG		0x1c
-#define PCI_PCI_BRIDGE_MEM_REG		0x20
-#define PCI_PCI_BRIDGE_PMEM_REG		0x24
-
-#define PCI_SUBID_REG0			0x2c
-#define PCI_SUBID_REG1			0x34
-#define PCI_SUBID_REG2			0x40
-
-#define PCI_SUBORDINATE_BUS_MASK	0x00ff0000
-#define PCI_SECONDARY_BUS_MASK		0x0000ff00
-#define PCI_PRIMARY_BUS_MASK		0x000000ff
-
-#define PCI_SUBORDINATE_BUS_EXTRACT(x)	(((x) >> 16) & 0xff)
-#define PCI_SECONDARY_BUS_EXTRACT(x)	(((x) >>  8) & 0xff)
-#define PCI_PRIMARY_BUS_EXTRACT(x)	(((x)      ) & 0xff)
-
-#define	PCI_PRIMARY_BUS_INSERT(x, y)	(((x) & ~PCI_PRIMARY_BUS_MASK) | ((y) <<  0))
-#define	PCI_SECONDARY_BUS_INSERT(x, y)	(((x) & ~PCI_SECONDARY_BUS_MASK) | ((y) <<  8))
-#define	PCI_SUBORDINATE_BUS_INSERT(x, y) (((x) & ~PCI_SUBORDINATE_BUS_MASK) | ((y) << 16))
-
-#define	PCI_PPB_IOBASE_EXTRACT(x)	(((x) << 8) & 0xF000)
-#define	PCI_PPB_IOLIMIT_EXTRACT(x)	(((x) << 0) & 0xF000 | 0x0FFF)
-
-#define	PCI_PPB_MEMBASE_EXTRACT(x)	(((x) << 16) & 0xFFF00000)
-#define	PCI_PPB_MEMLIMIT_EXTRACT(x)	(((x) <<  0) & 0xFFF00000 | 0x000FFFFF)
-
-/*
-** PCI-Cardbus bridge mapping registers
-*/
-#define PCI_CARDBUS_SOCKET_REG		0x10
-
-/*
-** Interrupt configuration register
-*/
-#define	PCI_INTERRUPT_REG		0x3c
-
-#define	PCI_INTERRUPT_PIN_MASK		0x0000ff00
-#define	PCI_INTERRUPT_PIN_EXTRACT(x)	((((x) & PCI_INTERRUPT_PIN_MASK) >> 8) & 0xff)
-#define	PCI_INTERRUPT_PIN_NONE		0x00
-#define	PCI_INTERRUPT_PIN_A		0x01
-#define	PCI_INTERRUPT_PIN_B		0x02
-#define	PCI_INTERRUPT_PIN_C		0x03
-#define	PCI_INTERRUPT_PIN_D		0x04
-
-#define	PCI_INTERRUPT_LINE_MASK		0x000000ff
-#define	PCI_INTERRUPT_LINE_EXTRACT(x)	((((x) & PCI_INTERRUPT_LINE_MASK) >> 0) & 0xff)
-#define	PCI_INTERRUPT_LINE_INSERT(x,v)	(((x) & ~PCI_INTERRUPT_LINE_MASK) | ((v) << 0))
-
-#endif /* __PCI_REG_H__ */
+#endif /* PCI_COMPAT */