Next round of PCI subsystem updates:

 - Break out the /dev/pci driver into a separate file.
 - Kill the COMPAT_OLDPCI support.
 - Make the EISA bridge attach a bit more like the old code; explicitly
   check for the existence of eisa0/isa0 and only attach if they don't
   already exist.  Only make one bus_generic_attach() pass over the
   bridge, once both busses are attached.  Note that the stupid Intel
   bridge's class is entirely unpredictable.
 - Add prototypes and re-layout the core PCI modules in line with
   current coding standards (not a major whitespace change, just moving
   the module data to the top of the file).
 - Remove redundant type-2 bridge support from the core PCI code; the
   PCI-CardBus code does this itself internally.  Remove the now
   entirely redundant header-class-specific support, as well as the
   secondary and subordinate bus number fields.  These are bridge
   attributes now.
 - Add support for PCI Extended Capabilities.
 - Add support for PCI Power Management.  The interface currently
   allows a driver to query and set the power state of a device.
 - Add helper functions to allow drivers to enable/disable busmastering
   and the decoding of I/O and memory ranges.
 - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some
   places.
 - Make the PCI-PCI bridge code a little more paranoid about valid
   I/O and memory decodes.
 - Add some more PCI register definitions for the command and status
   registers.  Correct another bogus definition for type-1 bridges.

1 files changed, 67 insertions, 30 deletions

diff --git a/sys/dev/pci/pcireg.h b/sys/dev/pci/pcireg.h
index 35297e4..1e98f72 100644
--- a/sys/dev/pci/pcireg.h
+++ b/sys/dev/pci/pcireg.h
@@ -52,10 +52,26 @@
 #define PCIR_COMMAND	0x04
 #define PCIM_CMD_PORTEN		0x0001
 #define PCIM_CMD_MEMEN		0x0002
-#define PCIM_CMD_MWRICEN	0x0010
 #define PCIM_CMD_BUSMASTEREN	0x0004
+#define PCIM_CMD_SPECIALEN	0x0008
+#define PCIM_CMD_MWRICEN	0x0010
 #define PCIM_CMD_PERRESPEN	0x0040
+#define PCIM_CMD_SERREN		0x0100
+#define PCIM_CMD_BACKTOBACK	0x0200
 #define PCIR_STATUS	0x06
+#define PCIM_STATUS_CAPPRESENT	0x0010
+#define PCIM_STATUS_66CAPABLE	0x0020
+#define PCIM_STATUS_BACKTOBACK	0x0080
+#define PCIM_STATUS_PERRREPORT	0x0100
+#define PCIM_STATUS_SEL_FAST	0x0000
+#define PCIM_STATUS_SEL_MEDIMUM	0x0200
+#define PCIM_STATUS_SEL_SLOW	0x0400
+#define PCIM_STATUS_SEL_MASK	0x0600
+#define PCIM_STATUS_STABORT	0x0800
+#define PCIM_STATUS_RTABORT	0x1000
+#define PCIM_STATUS_RMABORT	0x2000
+#define PCIM_STATUS_SERR	0x4000
+#define PCIM_STATUS_PERR	0x8000
 #define PCIR_REVID	0x08
 #define PCIR_PROGIF	0x09
 #define PCIR_SUBCLASS	0x0a
@@ -81,7 +97,7 @@
 
 /* config registers for header type 1 devices */
 
-#define PCIR_SECSTAT_1	0 /**/
+#define PCIR_SECSTAT_1	0x1e
 
 #define PCIR_PRIBUS_1	0x18
 #define PCIR_SECBUS_1	0x19
@@ -227,38 +243,59 @@
 
 #define PCIC_OTHER	0xff
 
+/* PCI power manangement */
+
+#define PCIR_POWER_CAP		0x2
+#define PCIM_PCAP_SPEC			0x0007
+#define PCIM_PCAP_PMEREQCLK		0x0008
+#define PCIM_PCAP_PMEREQPWR		0x0010
+#define PCIM_PCAP_DEVSPECINIT		0x0020
+#define PCIM_PCAP_DYNCLOCK		0x0040
+#define PCIM_PCAP_SECCLOCK		0x00c0
+#define PCIM_PCAP_CLOCKMASK		0x00c0
+#define PCIM_PCAP_REQFULLCLOCK		0x0100
+#define PCIM_PCAP_D1SUPP		0x0200
+#define PCIM_PCAP_D2SUPP		0x0400
+#define PCIM_PCAP_D0PME			0x1000
+#define PCIM_PCAP_D1PME			0x2000
+#define PCIM_PCAP_D2PME			0x4000
+
+#define PCIR_POWER_STATUS	0x4
+#define PCIM_PSTAT_D0			0x0000
+#define PCIM_PSTAT_D1			0x0001
+#define PCIM_PSTAT_D2			0x0002
+#define PCIM_PSTAT_D3			0x0003
+#define PCIM_PSTAT_DMASK		0x0003
+#define PCIM_PSTAT_REPENABLE		0x0010
+#define PCIM_PSTAT_PMEENABLE		0x0100
+#define PCIM_PSTAT_D0POWER		0x0000
+#define PCIM_PSTAT_D1POWER		0x0200
+#define PCIM_PSTAT_D2POWER		0x0400
+#define PCIM_PSTAT_D3POWER		0x0600
+#define PCIM_PSTAT_D0HEAT		0x0800
+#define PCIM_PSTAT_D1HEAT		0x1000
+#define PCIM_PSTAT_D2HEAT		0x1200
+#define PCIM_PSTAT_D3HEAT		0x1400
+#define PCIM_PSTAT_DATAUNKN		0x0000
+#define PCIM_PSTAT_DATADIV10		0x2000
+#define PCIM_PSTAT_DATADIV100		0x4000
+#define PCIM_PSTAT_DATADIV1000		0x6000
+#define PCIM_PSTAT_DATADIVMASK		0x6000
+#define PCIM_PSTAT_PME			0x8000
+
+#define PCIR_POWER_PMCSR	0x6
+#define PCIM_PMCSR_DCLOCK		0x10
+#define PCIM_PMCSR_B2SUPP		0x20
+#define PCIM_BMCSR_B3SUPP		0x40
+#define PCIM_BMCSR_BPCE			0x80
+
+#define PCIR_POWER_DATA		0x7
+
+#if 0
 /* some PCI vendor definitions (only used to identify ancient devices !!! */
 
 #define PCIV_INTEL	0x8086
 
 #define PCID_INTEL_SATURN	0x0483
 #define PCID_INTEL_ORION	0x84c4
-
-/* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */
-
-#if defined(_KERNEL) && !defined(KLD_MODULE)
-#include "opt_compat_oldpci.h"
 #endif
-
-#ifdef COMPAT_OLDPCI
-
-#define PCI_ID_REG		0x00
-#define PCI_COMMAND_STATUS_REG	0x04
-#define	PCI_COMMAND_IO_ENABLE		0x00000001
-#define	PCI_COMMAND_MEM_ENABLE		0x00000002
-#define PCI_CLASS_REG		0x08
-#define PCI_CLASS_MASK			0xff000000
-#define PCI_SUBCLASS_MASK		0x00ff0000
-#define	PCI_REVISION_MASK		0x000000ff
-#define PCI_CLASS_PREHISTORIC		0x00000000
-#define PCI_SUBCLASS_PREHISTORIC_VGA		0x00010000
-#define PCI_CLASS_MASS_STORAGE		0x01000000
-#define PCI_CLASS_DISPLAY		0x03000000
-#define PCI_SUBCLASS_DISPLAY_VGA		0x00000000
-#define PCI_CLASS_BRIDGE		0x06000000
-#define PCI_MAP_REG_START	0x10
-#define	PCI_MAP_REG_END		0x28
-#define	PCI_MAP_IO			0x00000001
-#define	PCI_INTERRUPT_REG	0x3c
-
-#endif /* COMPAT_OLDPCI */