diff options
| author | rwatson <rwatson@FreeBSD.org> | 2007-10-29 14:19:32 +0000 |
|---|---|---|
| committer | rwatson <rwatson@FreeBSD.org> | 2007-10-29 14:19:32 +0000 |
| commit | df4d50261927c949ecb4b8f20b8c0c587dc681ad (patch) | |
| tree | 5c43c011eb6bbd46d06a33a2943b65d985735f67 /sys/dev/nxge/include | |
| parent | a4265719055fe445116eb2743b6aacf518bb1a8d (diff) | |
| download | FreeBSD-src-df4d50261927c949ecb4b8f20b8c0c587dc681ad.zip FreeBSD-src-df4d50261927c949ecb4b8f20b8c0c587dc681ad.tar.gz | |
Merge Neterion if_nxge driver version 2.0.9.11230 with the following
changes:
01 - Enhanced LRO:
LRO feature is extended to support multi-buffer mode. Previously,
Ethernet frames received in contiguous buffers were offloaded.
Now, frames received in multiple non-contiguous buffers can be
offloaded, as well. The driver now supports LRO for jumbo frames.
02 - Locks Optimization:
The driver code was re-organized to limit the use of locks.
Moreover, lock contention was reduced by replacing wait locks
with try locks.
03 - Code Optimization:
The driver code was re-factored to eliminate some memcpy
operations. Fast path loops were optimized.
04 - Tag Creations:
Physical Buffer Tags are now optimized based upon frame size.
For better performance, Physical Memory Maps are now re-used.
05 - Configuration:
Features such as TSO, LRO, and Interrupt Mode can be configured
either at load or at run time. Rx buffer mode (mode 1 or mode 2)
can be configured at load time through kenv.
06 - Driver Statistics:
Run time statistics are enhanced to provide better visibility
into the driver performance.
07 - Bug Fixes:
The driver contains fixes for the problems discovered and
reported since last submission.
08 - MSI support:
Added Message Signaled Interrupt feature which currently uses 1
message.
09 Removed feature:
Rx 3 buffer mode feature has been removed. Driver now supports 1,
2 and 5 buffer modes of which 2 and 5 buffer modes can be used
for header separation.
10 Compiler warning:
Fixed compiler warning when compiled for 32 bit system.
11 Copyright notice:
Source files are updated with the proper copyright notice.
MFC after: 3 days
Submitted by: Alicia Pena <Alicia dot Pena at neterion dot com>,
Muhammad Shafiq <Muhammad dot Shafiq at neterion dot com>
Diffstat (limited to 'sys/dev/nxge/include')
22 files changed, 1992 insertions, 3068 deletions
diff --git a/sys/dev/nxge/include/build-version.h b/sys/dev/nxge/include/build-version.h index b9b5e00..33fb24d 100644 --- a/sys/dev/nxge/include/build-version.h +++ b/sys/dev/nxge/include/build-version.h @@ -1,6 +1,6 @@ -/* $FreeBSD$ */ #ifndef BUILD_VERSION_H #define BUILD_VERSION_H /* Do not edit! Automatically generated when released.*/ -#define GENERATED_BUILD_VERSION "10294" +/* $FreeBSD$ */ +#define GENERATED_BUILD_VERSION "11230" #endif /* BUILD_VERSION_H */ diff --git a/sys/dev/nxge/include/version.h b/sys/dev/nxge/include/version.h index 0a212f4..47d4fc1 100644 --- a/sys/dev/nxge/include/version.h +++ b/sys/dev/nxge/include/version.h @@ -26,26 +26,18 @@ * $FreeBSD$ */ -/* - * FileName : version.h - * - * Description: versioning file - * - * Created: 3 September 2004 - */ - #ifndef VERSION_H #define VERSION_H #include <dev/nxge/include/build-version.h> -#define XGE_HAL_VERSION_MAJOR "2" -#define XGE_HAL_VERSION_MINOR "5" -#define XGE_HAL_VERSION_FIX "0" -#define XGE_HAL_VERSION_BUILD GENERATED_BUILD_VERSION +#define XGE_HAL_VERSION_MAJOR "2" +#define XGE_HAL_VERSION_MINOR "0" +#define XGE_HAL_VERSION_FIX "9" +#define XGE_HAL_VERSION_BUILD GENERATED_BUILD_VERSION #define XGE_HAL_VERSION XGE_HAL_VERSION_MAJOR"."XGE_HAL_VERSION_MINOR"."\ - XGE_HAL_VERSION_FIX"."XGE_HAL_VERSION_BUILD -#define XGE_HAL_DESC XGE_DRIVER_NAME" v."XGE_HAL_VERSION + XGE_HAL_VERSION_FIX"."XGE_HAL_VERSION_BUILD +#define XGE_HAL_DESC XGE_DRIVER_NAME" v."XGE_HAL_VERSION /* Link Layer versioning */ #include <dev/nxge/xgell-version.h> diff --git a/sys/dev/nxge/include/xge-debug.h b/sys/dev/nxge/include/xge-debug.h index a4efbcb..74b9756 100644 --- a/sys/dev/nxge/include/xge-debug.h +++ b/sys/dev/nxge/include/xge-debug.h @@ -26,14 +26,6 @@ * $FreeBSD$ */ -/* - * FileName : xge-debug.h - * - * Description: debug facilities - * - * Created: 6 May 2004 - */ - #ifndef XGE_DEBUG_H #define XGE_DEBUG_H @@ -54,10 +46,11 @@ __EXTERN_BEGIN_DECLS #ifdef XGE_DEBUG_FP -#define XGE_DEBUG_FP_DEVICE 0x1 +#define XGE_DEBUG_FP_DEVICE 0x1 #define XGE_DEBUG_FP_CHANNEL 0x2 -#define XGE_DEBUG_FP_FIFO 0x4 -#define XGE_DEBUG_FP_RING 0x8 +#define XGE_DEBUG_FP_FIFO 0x4 +#define XGE_DEBUG_FP_RING 0x8 +#define XGE_DEBUG_FP_ALL 0xff #endif /** @@ -125,15 +118,6 @@ extern int *g_level; #define XGE_COMPONENT_HAL_QUEUE 0x00000040 #define XGE_COMPONENT_HAL_INTERRUPT 0x00000080 #define XGE_COMPONENT_HAL_STATS 0x00000100 -#ifdef XGEHAL_RNIC -#define XGE_COMPONENT_HAL_DMQ 0x00000200 -#define XGE_COMPONENT_HAL_UMQ 0x00000400 -#define XGE_COMPONENT_HAL_SQ 0x00000800 -#define XGE_COMPONENT_HAL_SRQ 0x00001000 -#define XGE_COMPONENT_HAL_CQRQ 0x00002000 -#define XGE_COMPONENT_HAL_POOL 0x00004000 -#define XGE_COMPONENT_HAL_BITMAP 0x00008000 -#endif /* space for CORE_XXX */ #define XGE_COMPONENT_OSDEP 0x10000000 @@ -146,9 +130,9 @@ extern int *g_level; #ifndef __GNUC__ #ifdef XGE_TRACE_INTO_CIRCULAR_ARR - #define xge_trace_aux(fmt) xge_os_vatrace(g_xge_os_tracebuf, fmt) + #define xge_trace_aux(fmt) xge_os_vatrace(g_xge_os_tracebuf, fmt) #else - #define xge_trace_aux(fmt) xge_os_vaprintf(fmt) + #define xge_trace_aux(fmt) xge_os_vaprintf(fmt) #endif /** @@ -164,24 +148,24 @@ extern int *g_level; */ #define xge_debug(module, level, fmt) { \ if (((level >= XGE_TRACE && ((module & XGE_DEBUG_TRACE_MASK) == module)) || \ - (level >= XGE_ERR && ((module & XGE_DEBUG_ERR_MASK) == module))) && \ - level >= *g_level && module & *(unsigned int *)g_module_mask) { \ - xge_trace_aux(fmt); \ + (level >= XGE_ERR && ((module & XGE_DEBUG_ERR_MASK) == module))) && \ + level >= *g_level && module & *(unsigned int *)g_module_mask) { \ + xge_trace_aux(fmt); \ } \ } #else /* __GNUC__ */ #ifdef XGE_TRACE_INTO_CIRCULAR_ARR - #define xge_trace_aux(fmt...) xge_os_trace(g_xge_os_tracebuf, fmt) + #define xge_trace_aux(fmt...) xge_os_trace(g_xge_os_tracebuf, fmt) #else - #define xge_trace_aux(fmt...) xge_os_printf(fmt) + #define xge_trace_aux(fmt...) xge_os_printf(fmt) #endif #define xge_debug(module, level, fmt...) { \ if (((level >= XGE_TRACE && ((module & XGE_DEBUG_TRACE_MASK) == module)) || \ - (level >= XGE_ERR && ((module & XGE_DEBUG_ERR_MASK) == module))) && \ - level >= *g_level && module & *(unsigned int *)g_module_mask) { \ - xge_trace_aux(fmt); \ + (level >= XGE_ERR && ((module & XGE_DEBUG_ERR_MASK) == module))) && \ + level >= *g_level && module & *(unsigned int *)g_module_mask) { \ + xge_trace_aux(fmt); \ } \ } #endif /* __GNUC__ */ @@ -353,136 +337,6 @@ static inline void xge_debug_device(xge_debug_level_e level, char *fmt, ...) {} #endif /* __GNUC__ */ #endif -#ifdef XGEHAL_RNIC - -#if (XGE_COMPONENT_HAL_DMQ & XGE_DEBUG_MODULE_MASK) -#ifndef __GNUC__ -static inline void xge_debug_dmq(xge_debug_level_e level, char *fmt, ...) { - u32 module = XGE_COMPONENT_HAL_DMQ; - xge_debug(module, level, fmt); -} -#else /* __GNUC__ */ -#define xge_debug_dmq(level, fmt...) \ - xge_debug(XGE_COMPONENT_HAL_DMQ, level, fmt) -#endif /* __GNUC__ */ -#else -#ifndef __GNUC__ -static inline void xge_debug_dmq(xge_debug_level_e level, char *fmt, ...) {} -#else /* __GNUC__ */ -#define xge_debug_dmq(level, fmt...) -#endif /* __GNUC__ */ -#endif - -#if (XGE_COMPONENT_HAL_UMQ & XGE_DEBUG_MODULE_MASK) -#ifndef __GNUC__ -static inline void xge_debug_umq(xge_debug_level_e level, char *fmt, ...) { - u32 module = XGE_COMPONENT_HAL_UMQ; - xge_debug(module, level, fmt); -} -#else /* __GNUC__ */ -#define xge_debug_umq(level, fmt...) \ - xge_debug(XGE_COMPONENT_HAL_UMQ, level, fmt) -#endif /* __GNUC__ */ -#else -#ifndef __GNUC__ -static inline void xge_debug_umq(xge_debug_level_e level, char *fmt, ...) {} -#else /* __GNUC__ */ -#define xge_debug_umq(level, fmt...) -#endif /* __GNUC__ */ -#endif - -#if (XGE_COMPONENT_HAL_SQ & XGE_DEBUG_MODULE_MASK) -#ifndef __GNUC__ -static inline void xge_debug_sq(xge_debug_level_e level, char *fmt, ...) { - u32 module = XGE_COMPONENT_HAL_SQ; - xge_debug(module, level, fmt); -} -#else /* __GNUC__ */ -#define xge_debug_sq(level, fmt...) \ - xge_debug(XGE_COMPONENT_HAL_SQ, level, fmt) -#endif /* __GNUC__ */ -#else -#ifndef __GNUC__ -static inline void xge_debug_sq(xge_debug_level_e level, char *fmt, ...) {} -#else /* __GNUC__ */ -#define xge_debug_sq(level, fmt...) -#endif /* __GNUC__ */ -#endif - -#if (XGE_COMPONENT_HAL_SRQ & XGE_DEBUG_MODULE_MASK) -#ifndef __GNUC__ -static inline void xge_debug_srq(xge_debug_level_e level, char *fmt, ...) { - u32 module = XGE_COMPONENT_HAL_SRQ; - xge_debug(module, level, fmt); -} -#else /* __GNUC__ */ -#define xge_debug_srq(level, fmt...) \ - xge_debug(XGE_COMPONENT_HAL_SRQ, level, fmt) -#endif /* __GNUC__ */ -#else -#ifndef __GNUC__ -static inline void xge_debug_srq(xge_debug_level_e level, char *fmt, ...) {} -#else /* __GNUC__ */ -#define xge_debug_srq(level, fmt...) -#endif /* __GNUC__ */ -#endif - -#if (XGE_COMPONENT_HAL_CQRQ & XGE_DEBUG_MODULE_MASK) -#ifndef __GNUC__ -static inline void xge_debug_cqrq(xge_debug_level_e level, char *fmt, ...) { - u32 module = XGE_COMPONENT_HAL_CQRQ; - xge_debug(module, level, fmt); -} -#else /* __GNUC__ */ -#define xge_debug_cqrq(level, fmt...) \ - xge_debug(XGE_COMPONENT_HAL_CQRQ, level, fmt) -#endif /* __GNUC__ */ -#else -#ifndef __GNUC__ -static inline void xge_debug_cqrq(xge_debug_level_e level, char *fmt, ...) {} -#else /* __GNUC__ */ -#define xge_debug_cqrq(level, fmt...) -#endif /* __GNUC__ */ -#endif - -#if (XGE_COMPONENT_HAL_POOL & XGE_DEBUG_MODULE_MASK) -#ifndef __GNUC__ -static inline void xge_debug_pool(xge_debug_level_e level, char *fmt, ...) { - u32 module = XGE_COMPONENT_HAL_POOL; - xge_debug(module, level, fmt); -} -#else /* __GNUC__ */ -#define xge_debug_pool(level, fmt...) \ - xge_debug(XGE_COMPONENT_HAL_POOL, level, fmt) -#endif /* __GNUC__ */ -#else -#ifndef __GNUC__ -static inline void xge_debug_pool(xge_debug_level_e level, char *fmt, ...) {} -#else /* __GNUC__ */ -#define xge_debug_pool(level, fmt...) -#endif /* __GNUC__ */ -#endif - -#if (XGE_COMPONENT_HAL_BITMAP & XGE_DEBUG_MODULE_MASK) -#ifndef __GNUC__ -static inline void xge_debug_bitmap(xge_debug_level_e level, char *fmt, ...) { - u32 module = XGE_COMPONENT_HAL_BITMAP; - xge_debug(module, level, fmt); -} -#else /* __GNUC__ */ -#define xge_debug_bitmap(level, fmt...) \ - xge_debug(XGE_COMPONENT_HAL_BITMAP, level, fmt) -#endif /* __GNUC__ */ -#else -#ifndef __GNUC__ -static inline void xge_debug_bitmap(xge_debug_level_e level, char *fmt, ...) {} -#else /* __GNUC__ */ -#define xge_debug_bitmap(level, fmt...) -#endif /* __GNUC__ */ -#endif - -#endif - #if (XGE_COMPONENT_OSDEP & XGE_DEBUG_MODULE_MASK) #ifndef __GNUC__ static inline void xge_debug_osdep(xge_debug_level_e level, char *fmt, ...) { @@ -531,13 +385,6 @@ static inline void xge_debug_fifo(xge_debug_level_e level, char *fmt, ...) {} static inline void xge_debug_ring(xge_debug_level_e level, char *fmt, ...) {} static inline void xge_debug_channel(xge_debug_level_e level, char *fmt, ...) {} static inline void xge_debug_device(xge_debug_level_e level, char *fmt, ...) {} -static inline void xge_debug_dmq(xge_debug_level_e level, char *fmt, ...) {} -static inline void xge_debug_umq(xge_debug_level_e level, char *fmt, ...) {} -static inline void xge_debug_sq(xge_debug_level_e level, char *fmt, ...) {} -static inline void xge_debug_srq(xge_debug_level_e level, char *fmt, ...) {} -static inline void xge_debug_cqrq(xge_debug_level_e level, char *fmt, ...) {} -static inline void xge_debug_pool(xge_debug_level_e level, char *fmt, ...) {} -static inline void xge_debug_bitmap(xge_debug_level_e level, char *fmt, ...) {} static inline void xge_debug_hal(xge_debug_level_e level, char *fmt, ...) {} static inline void xge_debug_osdep(xge_debug_level_e level, char *fmt, ...) {} static inline void xge_debug_ll(xge_debug_level_e level, char *fmt, ...) {} @@ -557,7 +404,7 @@ static inline void xge_debug_ll(xge_debug_level_e level, char *fmt, ...) {} * time. */ #define xge_assert(test) { \ - if (!(test)) xge_os_bug("bad cond: "#test" at %s:%d\n", \ + if (!(test)) xge_os_bug("bad cond: "#test" at %s:%d\n", \ __FILE__, __LINE__); } #else #define xge_assert(test) diff --git a/sys/dev/nxge/include/xge-defs.h b/sys/dev/nxge/include/xge-defs.h index 744a6b9..17bc907 100644 --- a/sys/dev/nxge/include/xge-defs.h +++ b/sys/dev/nxge/include/xge-defs.h @@ -26,35 +26,27 @@ * $FreeBSD$ */ -/* - * FileName : xge-defs.h - * - * Description: global definitions - * - * Created: 13 May 2004 - */ - #ifndef XGE_DEFS_H #define XGE_DEFS_H -#define XGE_PCI_VENDOR_ID 0x17D5 -#define XGE_PCI_DEVICE_ID_XENA_1 0x5731 -#define XGE_PCI_DEVICE_ID_XENA_2 0x5831 -#define XGE_PCI_DEVICE_ID_HERC_1 0x5732 -#define XGE_PCI_DEVICE_ID_HERC_2 0x5832 -#define XGE_PCI_DEVICE_ID_TITAN_1 0x5733 -#define XGE_PCI_DEVICE_ID_TITAN_2 0x5833 +#define XGE_PCI_VENDOR_ID 0x17D5 +#define XGE_PCI_DEVICE_ID_XENA_1 0x5731 +#define XGE_PCI_DEVICE_ID_XENA_2 0x5831 +#define XGE_PCI_DEVICE_ID_HERC_1 0x5732 +#define XGE_PCI_DEVICE_ID_HERC_2 0x5832 +#define XGE_PCI_DEVICE_ID_TITAN_1 0x5733 +#define XGE_PCI_DEVICE_ID_TITAN_2 0x5833 -#define XGE_DRIVER_NAME "Xge driver" -#define XGE_DRIVER_VENDOR "Neterion, Inc" -#define XGE_CHIP_FAMILY "Xframe" -#define XGE_SUPPORTED_MEDIA_0 "Fiber" +#define XGE_DRIVER_NAME "Xge driver" +#define XGE_DRIVER_VENDOR "Neterion, Inc" +#define XGE_CHIP_FAMILY "Xframe" +#define XGE_SUPPORTED_MEDIA_0 "Fiber" #include <dev/nxge/include/version.h> #if defined(__cplusplus) -#define __EXTERN_BEGIN_DECLS extern "C" { -#define __EXTERN_END_DECLS } +#define __EXTERN_BEGIN_DECLS extern "C" { +#define __EXTERN_END_DECLS } #else #define __EXTERN_BEGIN_DECLS #define __EXTERN_END_DECLS @@ -67,7 +59,7 @@ __EXTERN_BEGIN_DECLS /*---------------------------- DMA attributes ------------------------------*/ /* XGE_OS_DMA_REQUIRES_SYNC - should be defined or - NOT defined in the Makefile */ + NOT defined in the Makefile */ #define XGE_OS_DMA_CACHELINE_ALIGNED 0x1 /* Either STREAMING or CONSISTENT should be used. The combination of both or none is invalid */ @@ -77,7 +69,7 @@ __EXTERN_BEGIN_DECLS /*---------------------------- common stuffs -------------------------------*/ -#define XGE_OS_LLXFMT "%llx" +#define XGE_OS_LLXFMT "%llx" #define XGE_OS_NEWLINE "\n" #ifdef XGE_OS_MEMORY_CHECK typedef struct { @@ -87,56 +79,56 @@ typedef struct { int line; } xge_os_malloc_t; -#define XGE_OS_MALLOC_CNT_MAX 64*1024 +#define XGE_OS_MALLOC_CNT_MAX 64*1024 extern xge_os_malloc_t g_malloc_arr[XGE_OS_MALLOC_CNT_MAX]; extern int g_malloc_cnt; #define XGE_OS_MEMORY_CHECK_MALLOC(_vaddr, _size, _file, _line) { \ if (_vaddr) { \ - int i; \ - for (i=0; i<g_malloc_cnt; i++) { \ - if (g_malloc_arr[i].ptr == NULL) { \ - break; \ - } \ - } \ - if (i == g_malloc_cnt) { \ - g_malloc_cnt++; \ - if (g_malloc_cnt >= XGE_OS_MALLOC_CNT_MAX) { \ - xge_os_bug("g_malloc_cnt exceed %d", \ - XGE_OS_MALLOC_CNT_MAX); \ - } \ - } \ - g_malloc_arr[i].ptr = _vaddr; \ - g_malloc_arr[i].size = _size; \ - g_malloc_arr[i].file = _file; \ - g_malloc_arr[i].line = _line; \ - for (i=0; i<_size; i++) { \ - *((char *)_vaddr+i) = 0x5a; \ - } \ + int index_mem_chk; \ + for (index_mem_chk=0; index_mem_chk < g_malloc_cnt; index_mem_chk++) { \ + if (g_malloc_arr[index_mem_chk].ptr == NULL) { \ + break; \ + } \ + } \ + if (index_mem_chk == g_malloc_cnt) { \ + g_malloc_cnt++; \ + if (g_malloc_cnt >= XGE_OS_MALLOC_CNT_MAX) { \ + xge_os_bug("g_malloc_cnt exceed %d", \ + XGE_OS_MALLOC_CNT_MAX); \ + } \ + } \ + g_malloc_arr[index_mem_chk].ptr = _vaddr; \ + g_malloc_arr[index_mem_chk].size = _size; \ + g_malloc_arr[index_mem_chk].file = _file; \ + g_malloc_arr[index_mem_chk].line = _line; \ + for (index_mem_chk=0; index_mem_chk<_size; index_mem_chk++) { \ + *((char *)_vaddr+index_mem_chk) = 0x5a; \ + } \ } \ } #define XGE_OS_MEMORY_CHECK_FREE(_vaddr, _check_size) { \ - int i; \ - for (i=0; i<XGE_OS_MALLOC_CNT_MAX; i++) { \ - if (g_malloc_arr[i].ptr == _vaddr) { \ - g_malloc_arr[i].ptr = NULL; \ - if(_check_size && g_malloc_arr[i].size!=_check_size) { \ - xge_os_printf("OSPAL: freeing with wrong " \ - "size %d! allocated at %s:%d:"XGE_OS_LLXFMT":%d", \ - (int)_check_size, \ - g_malloc_arr[i].file, \ - g_malloc_arr[i].line, \ - (unsigned long long)(ulong_t) \ - g_malloc_arr[i].ptr, \ - g_malloc_arr[i].size); \ - } \ - break; \ - } \ + int index_mem_chk; \ + for (index_mem_chk=0; index_mem_chk < XGE_OS_MALLOC_CNT_MAX; index_mem_chk++) { \ + if (g_malloc_arr[index_mem_chk].ptr == _vaddr) { \ + g_malloc_arr[index_mem_chk].ptr = NULL; \ + if(_check_size && g_malloc_arr[index_mem_chk].size!=_check_size) { \ + xge_os_printf("OSPAL: freeing with wrong " \ + "size %d! allocated at %s:%d:"XGE_OS_LLXFMT":%d", \ + (int)_check_size, \ + g_malloc_arr[index_mem_chk].file, \ + g_malloc_arr[index_mem_chk].line, \ + (unsigned long long)(ulong_t) \ + g_malloc_arr[index_mem_chk].ptr, \ + g_malloc_arr[index_mem_chk].size); \ + } \ + break; \ + } \ } \ - if (i == XGE_OS_MALLOC_CNT_MAX) { \ - xge_os_printf("OSPAL: ptr "XGE_OS_LLXFMT" not found!", \ - (unsigned long long)(ulong_t)_vaddr); \ + if (index_mem_chk == XGE_OS_MALLOC_CNT_MAX) { \ + xge_os_printf("OSPAL: ptr "XGE_OS_LLXFMT" not found!", \ + (unsigned long long)(ulong_t)_vaddr); \ } \ } #else diff --git a/sys/dev/nxge/include/xge-list.h b/sys/dev/nxge/include/xge-list.h index c49424d..544a623 100644 --- a/sys/dev/nxge/include/xge-list.h +++ b/sys/dev/nxge/include/xge-list.h @@ -26,14 +26,6 @@ * $FreeBSD$ */ -/* - * FileName : xge-list.h - * - * Description: Generic bi-directional linked list implementation - * - * Created: 14 May 2004 - */ - #ifndef XGE_LIST_H #define XGE_LIST_H @@ -76,9 +68,9 @@ static inline void xge_list_init (xge_list_t *header) */ static inline int xge_list_is_empty(xge_list_t *header) { - xge_assert(header != NULL); + xge_assert(header != NULL); - return header->next == header; + return header->next == header; } /** @@ -96,9 +88,9 @@ static inline xge_list_t *xge_list_first_get(xge_list_t *header) xge_assert(header->prev != NULL); if(header->next == header) - return NULL; + return NULL; else - return header->next; + return header->next; } /** @@ -131,7 +123,7 @@ static inline void xge_list_remove(xge_list_t *item) * See also: xge_list_remove(), xge_list_insert_before(), xge_list_t{}. */ static inline void xge_list_insert (xge_list_t *new_item, - xge_list_t *prev_item) + xge_list_t *prev_item) { xge_assert(new_item != NULL); xge_assert(prev_item != NULL); @@ -151,7 +143,7 @@ static inline void xge_list_insert (xge_list_t *new_item, * Insert new item (new_item) before given item (next_item). */ static inline void xge_list_insert_before (xge_list_t *new_item, - xge_list_t *next_item) + xge_list_t *next_item) { xge_assert(new_item != NULL); xge_assert(next_item != NULL); @@ -165,34 +157,34 @@ static inline void xge_list_insert_before (xge_list_t *new_item, #define xge_list_for_each(_p, _h) \ for (_p = (_h)->next, xge_os_prefetch(_p->next); _p != (_h); \ - _p = _p->next, xge_os_prefetch(_p->next)) + _p = _p->next, xge_os_prefetch(_p->next)) #define xge_list_for_each_safe(_p, _n, _h) \ - for (_p = (_h)->next, _n = _p->next; _p != (_h); \ - _p = _n, _n = _p->next) + for (_p = (_h)->next, _n = _p->next; _p != (_h); \ + _p = _n, _n = _p->next) #ifdef __GNUC__ /** * xge_container_of - Given a member, return the containing structure. - * @ptr: the pointer to the member. - * @type: the type of the container struct this is embedded in. - * @member: the name of the member within the struct. + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. * * Cast a member of a structure out to the containing structure. */ -#define xge_container_of(ptr, type, member) ({ \ - __typeof( ((type *)0)->member ) *__mptr = (ptr); \ - (type *)(void *)( (char *)__mptr - ((size_t) &((type *)0)->member) );}) +#define xge_container_of(ptr, type, member) ({ \ + __typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)(void *)( (char *)__mptr - ((size_t) &((type *)0)->member) );}) #else /* type unsafe version */ #define xge_container_of(ptr, type, member) \ - ((type*)(void*)((char*)(ptr) - ((size_t) &((type *)0)->member))) + ((type*)(void*)((char*)(ptr) - ((size_t) &((type *)0)->member))) #endif /** * xge_offsetof - Offset of the member in the containing structure. - * @t: struct name. - * @m: the name of the member within the struct. + * @t: struct name. + * @m: the name of the member within the struct. * * Return the offset of the member @m in the structure @t. */ diff --git a/sys/dev/nxge/include/xge-os-pal.h b/sys/dev/nxge/include/xge-os-pal.h index 5c92fe6..166cadb 100644 --- a/sys/dev/nxge/include/xge-os-pal.h +++ b/sys/dev/nxge/include/xge-os-pal.h @@ -26,15 +26,6 @@ * $FreeBSD$ */ -/* - * FileName : xge-os-pal.h - * - * Description: top-level header file. works just like switching between - * os-depndent parts - * - * Created: 6st May 2004 - */ - #ifndef XGE_OS_PAL_H #define XGE_OS_PAL_H @@ -46,10 +37,6 @@ __EXTERN_BEGIN_DECLS /* platform specific header */ #include <dev/nxge/xge-osdep.h> -#ifdef XGEHAL_RNIC -#define IN -#define OUT -#endif #if !defined(XGE_OS_PLATFORM_64BIT) && !defined(XGE_OS_PLATFORM_32BIT) #error "either 32bit or 64bit switch must be defined!" @@ -60,20 +47,20 @@ __EXTERN_BEGIN_DECLS #endif #if defined(XGE_OS_PLATFORM_64BIT) -#define XGE_OS_MEMORY_DEADCODE_PAT 0x5a5a5a5a5a5a5a5a +#define XGE_OS_MEMORY_DEADCODE_PAT 0x5a5a5a5a5a5a5a5a #else -#define XGE_OS_MEMORY_DEADCODE_PAT 0x5a5a5a5a +#define XGE_OS_MEMORY_DEADCODE_PAT 0x5a5a5a5a #endif -#define XGE_OS_TRACE_MSGBUF_MAX 512 +#define XGE_OS_TRACE_MSGBUF_MAX 512 typedef struct xge_os_tracebuf_t { - int wrapped_once; /* circular buffer been wrapped */ - int timestamp; /* whether timestamps are enabled */ - volatile int offset; /* offset within the tracebuf */ - int size; /* total size of trace buffer */ - char msg[XGE_OS_TRACE_MSGBUF_MAX]; /* each individual buffer */ - int msgbuf_max; /* actual size of msg buffer */ - char *data; /* pointer to data buffer */ + int wrapped_once; /* circular buffer been wrapped */ + int timestamp; /* whether timestamps are enabled */ + volatile int offset; /* offset within the tracebuf */ + int size; /* total size of trace buffer */ + char msg[XGE_OS_TRACE_MSGBUF_MAX]; /* each individual buffer */ + int msgbuf_max; /* actual size of msg buffer */ + char *data; /* pointer to data buffer */ } xge_os_tracebuf_t; extern xge_os_tracebuf_t *g_xge_os_tracebuf; @@ -86,42 +73,42 @@ extern char *dmesg_start; int msgsize = xge_os_strlen(tb->msg) + 2; \ int offset = tb->offset; \ if (msgsize != 2 && msgsize < tb->msgbuf_max) { \ - int leftsize = tb->size - offset; \ - if ((msgsize + tb->msgbuf_max) > leftsize) { \ - xge_os_memzero(tb->data + offset, leftsize); \ - offset = 0; \ - tb->wrapped_once = 1; \ - } \ - xge_os_memcpy(tb->data + offset, tb->msg, msgsize-1); \ - *(tb->data + offset + msgsize-1) = '\n'; \ - *(tb->data + offset + msgsize) = 0; \ - offset += msgsize; \ - tb->offset = offset; \ - dmesg_start = tb->data + offset; \ - *tb->msg = 0; \ + int leftsize = tb->size - offset; \ + if ((msgsize + tb->msgbuf_max) > leftsize) { \ + xge_os_memzero(tb->data + offset, leftsize); \ + offset = 0; \ + tb->wrapped_once = 1; \ + } \ + xge_os_memcpy(tb->data + offset, tb->msg, msgsize-1); \ + *(tb->data + offset + msgsize-1) = '\n'; \ + *(tb->data + offset + msgsize) = 0; \ + offset += msgsize; \ + tb->offset = offset; \ + dmesg_start = tb->data + offset; \ + *tb->msg = 0; \ } \ } #define xge_os_vatrace(tb, fmt) { \ if (tb != NULL) { \ - char *_p = tb->msg; \ - if (tb->timestamp) { \ - xge_os_timestamp(tb->msg); \ - _p = tb->msg + xge_os_strlen(tb->msg); \ - } \ - xge_os_vasprintf(_p, fmt); \ - __xge_trace(tb); \ + char *_p = tb->msg; \ + if (tb->timestamp) { \ + xge_os_timestamp(tb->msg); \ + _p = tb->msg + xge_os_strlen(tb->msg); \ + } \ + xge_os_vasprintf(_p, fmt); \ + __xge_trace(tb); \ } \ } #ifdef __GNUC__ #define xge_os_trace(tb, fmt...) { \ if (tb != NULL) { \ - if (tb->timestamp) { \ - xge_os_timestamp(tb->msg); \ - } \ - xge_os_sprintf(tb->msg + xge_os_strlen(tb->msg), fmt); \ - __xge_trace(tb); \ + if (tb->timestamp) { \ + xge_os_timestamp(tb->msg); \ + } \ + xge_os_sprintf(tb->msg + xge_os_strlen(tb->msg), fmt); \ + __xge_trace(tb); \ } \ } #endif /* __GNUC__ */ diff --git a/sys/dev/nxge/include/xge-os-template.h b/sys/dev/nxge/include/xge-os-template.h deleted file mode 100644 index 4d50e6e..0000000 --- a/sys/dev/nxge/include/xge-os-template.h +++ /dev/null @@ -1,614 +0,0 @@ -/*- - * Copyright (c) 2002-2007 Neterion, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -/* - * FileName : xge-os-template.h - * - * Description: Template for creating platform-dependent "glue" code. - * - * Created: 6 May 2004 - */ - -#ifndef XGE_OS_TEMPLATE_H -#define XGE_OS_TEMPLATE_H - -#ifndef TEMPLATE -# error "should not be compiled for platforms other than TEMPLATE..." -#endif - -/* ------------------------- includes and defines ------------------------- */ - -/* - * Note: - * - * - on some operating systems like Linux & FreeBSD, there is a macro - * by using which it is possible to determine endiennes automatically - */ -#define XGE_OS_HOST_BIG_ENDIAN TEMPLATE - -#define XGE_OS_HOST_PAGE_SIZE TEMPLATE - -/* ---------------------- fixed size primitive types -----------------------*/ - -/* - * Note: - * - * - u## - means ## bits unsigned int/long - * - all names must be preserved since HAL using them. - * - ulong_t is platform specific, i.e. for 64bit - 64bit size, for - * 32bit - 32bit size - */ -#define TEMPLATE u8 -#define TEMPLATE u16 -#define TEMPLATE u32 -#define TEMPLATE u64 -#define TEMPLATE ulong_t -#define TEMPLATE ptrdiff_t -#define TEMPLATE dma_addr_t -#define TEMPLATE spinlock_t -typedef TEMPLATE pci_dev_h; -typedef TEMPLATE pci_reg_h; -typedef TEMPLATE pci_dma_h; -typedef TEMPLATE pci_irq_h; -typedef TEMPLATE pci_cfg_h; -typedef TEMPLATE pci_dma_acc_h; - -/* -------------------------- "libc" functionality -------------------------*/ - -/* - * Note: - * - * - "libc" functionality maps one-to-one to be posix-like - */ -/* Note: use typedef: xge_os_memzero(void* mem, int size); */ -#define xge_os_memzero TEMPLATE - -/* Note: the 1st argument MUST be destination, like in: - * void *memcpy(void *dest, const void *src, size_t n); - */ -#define xge_os_memcpy TEMPLATE - -/* Note: should accept format (the 1st argument) and a variable - * number of arguments thereafter.. */ -#define xge_os_printf(fmt...) TEMPLATE - -#define xge_os_vasprintf(buf, fmt...) TEMPLATE - -#define xge_os_sprintf(buf, fmt, ...) TEMPLATE - -#define xge_os_timestamp(buf) TEMPLATE - -#define xge_os_println TEMPLATE - -/* -------------------- synchronization primitives -------------------------*/ - -/* - * Note: - * - * - use spin_lock in interrupts or in threads when there is no races - * with interrupt - * - use spin_lock_irqsave in threads if there is a race with interrupt - * - use spin_lock_irqsave for nested locks - */ - -/* - * Initialize the spin lock. - */ -#define xge_os_spin_lock_init(lockp, ctxh) TEMPLATE -/* - * Initialize the spin lock (IRQ version). - */ -#define xge_os_spin_lock_init_irq(lockp, ctxh) TEMPLATE -/* - * Destroy the lock. - */ -#define xge_os_spin_lock_destroy(lockp, ctxh) TEMPLATE - -/* - * Destroy the lock (IRQ version). - */ -#define xge_os_spin_lock_destroy_irq(lockp, ctxh) TEMPLATE -/* - * Acquire the lock. - */ -#define xge_os_spin_lock(lockp) TEMPLATE -/* - * Release the lock. - */ -#define xge_os_spin_unlock(lockp) TEMPLATE -/* - * Acquire the lock(IRQ version). - */ -#define xge_os_spin_lock_irq(lockp, flags) TEMPLATE -/* - * Release the lock(IRQ version). - */ -#define xge_os_spin_unlock_irq(lockp, flags) TEMPLATE -/* - * Write memory barrier. - */ -#define xge_os_wmb() TEMPLATE -/* - * Delay (in micro seconds). - */ -#define xge_os_udelay(us) TEMPLATE -/* - * Delay (in milli seconds). - */ -#define xge_os_mdelay(ms) TEMPLATE -/* - * Compare and exchange. - */ -#define xge_os_cmpxchg(targetp, cmp, newval) TEMPLATE - - - -/* ------------------------- misc primitives -------------------------------*/ - -#define xge_os_prefetch TEMPLATE -#define xge_os_prefetchw TEMPLATE -#define xge_os_bug(fmt...) TEMPLATE - -/* -------------------------- compiler stuffs ------------------------------*/ - -#define __xge_os_attr_cacheline_aligned TEMPLATE - -/* ---------------------- memory primitives --------------------------------*/ - -/** - * xge_os_malloc - Allocate non DMA-able memory. - * @pdev: Device context. Some OSs require device context to perform - * operations on memory. - * @size: Size to allocate. - * - * Allocate @size bytes of memory. This allocation can sleep, and - * therefore, and therefore it requires process context. In other words, - * xge_os_malloc() cannot be called from the interrupt context. - * Use xge_os_free() to free the allocated block. - * - * Returns: Pointer to allocated memory, NULL - on failure. - * - * See also: xge_os_free(). - */ -static inline void *xge_os_malloc(IN pci_dev_h pdev, - IN unsigned long size) -{ TEMPLATE; } - -/** - * xge_os_free - Free non DMA-able memory. - * @pdev: Device context. Some OSs require device context to perform - * operations on memory. - * @vaddr: Address of the allocated memory block. - * @size: Some OS's require to provide size on free - * - * Free the memory area obtained via xge_os_malloc(). - * This call may also sleep, and therefore it cannot be used inside - * interrupt. - * - * See also: xge_os_malloc(). - */ -static inline void xge_os_free(IN pci_dev_h pdev, - IN const void *vaddr, - IN unsigned long size) -{ TEMPLATE; } - -/** - * xge_os_vaddr - Get Virtual address for the given physical address. - * @pdev: Device context. Some OSs require device context to perform - * operations on memory. - * @vaddr: Physical Address of the memory block. - * @size: Some OS's require to provide size - * - * Get the virtual address for physical address. - * This call may also sleep, and therefore it cannot be used inside - * interrupt. - * - * See also: xge_os_malloc(). - */ -static inline void xge_os_vaddr(IN pci_dev_h pdev, - IN const void *vaddr, - IN unsigned long size) -{ TEMPLATE; } - -/** - * xge_os_dma_malloc - Allocate DMA-able memory. - * @pdev: Device context. Used to allocate/pin/map/unmap DMA-able memory. - * @size: Size (in bytes) to allocate. - * @dma_flags: XGE_OS_DMA_CACHELINE_ALIGNED, - * XGE_OS_DMA_STREAMING, - * XGE_OS_DMA_CONSISTENT - * Note that the last two flags are mutually exclusive. - * @p_dmah: Handle used to map the memory onto the corresponding device memory - * space. See xge_os_dma_map(). The handle is an out-parameter - * returned by the function. - * @p_dma_acch: One more DMA handle used subsequently to free the - * DMA object (via xge_os_dma_free()). - * Note that this and the previous handle have - * physical meaning for Solaris; on Windows and Linux the - * corresponding value will be simply a pointer to PCI device. - * The value is returned by this function. - * - * Allocate DMA-able contiguous memory block of the specified @size. - * This memory can be subsequently freed using xge_os_dma_free(). - * Note: can be used inside interrupt context. - * - * Returns: Pointer to allocated memory(DMA-able), NULL on failure. - * - */ -static inline void *xge_os_dma_malloc(IN pci_dev_h pdev, - IN unsigned long size, - IN int dma_flags, - OUT pci_dma_h *p_dmah, - OUT pci_dma_acc_h *p_dma_acch) -{ TEMPLATE; } - -/** - * xge_os_dma_free - Free previously allocated DMA-able memory. - * @pdev: Device context. Used to allocate/pin/map/unmap DMA-able memory. - * @vaddr: Virtual address of the DMA-able memory. - * @p_dma_acch: DMA handle used to free the resource. - * @p_dmah: DMA handle used for mapping. See xge_os_dma_malloc(). - * - * Free DMA-able memory originally allocated by xge_os_dma_malloc(). - * Note: can be used inside interrupt. - * See also: xge_os_dma_malloc(). - */ -static inline void xge_os_dma_free (IN pci_dev_h pdev, - IN const void *vaddr, - IN pci_dma_acc_h *p_dma_acch, - IN pci_dma_h *p_dmah) -{ TEMPLATE; } - -/* ----------------------- io/pci/dma primitives ---------------------------*/ - -#define XGE_OS_DMA_DIR_TODEVICE TEMPLATE -#define XGE_OS_DMA_DIR_FROMDEVICE TEMPLATE -#define XGE_OS_DMA_DIR_BIDIRECTIONAL TEMPLATE - -/** - * xge_os_pci_read8 - Read one byte from device PCI configuration. - * @pdev: Device context. Some OSs require device context to perform - * PIO and/or config space IO. - * @cfgh: PCI configuration space handle. - * @where: Offset in the PCI configuration space. - * @val: Address of the result. - * - * Read byte value from the specified @regh PCI configuration space at the - * specified offset = @where. - * Returns: 0 - success, non-zero - failure. - */ -static inline int xge_os_pci_read8(IN pci_dev_h pdev, - IN pci_cfg_h cfgh, - IN int where, - IN u8 *val) -{ TEMPLATE; } - -/** - * xge_os_pci_write8 - Write one byte into device PCI configuration. - * @pdev: Device context. Some OSs require device context to perform - * PIO and/or config space IO. - * @cfgh: PCI configuration space handle. - * @where: Offset in the PCI configuration space. - * @val: Value to write. - * - * Write byte value into the specified PCI configuration space - * Returns: 0 - success, non-zero - failure. - */ -static inline int xge_os_pci_write8(IN pci_dev_h pdev, - IN pci_cfg_h cfgh, - IN int where, - IN u8 val) -{ TEMPLATE; } - -/** - * xge_os_pci_read16 - Read 16bit word from device PCI configuration. - * @pdev: Device context. Some OSs require device context to perform - * PIO and/or config space IO. - * @cfgh: PCI configuration space handle. - * @where: Offset in the PCI configuration space. - * @val: Address of the 16bit result. - * - * Read 16bit value from the specified PCI configuration space at the - * specified offset. - * Returns: 0 - success, non-zero - failure. - */ -static inline int xge_os_pci_read16(IN pci_dev_h pdev, - IN pci_cfg_h cfgh, - IN int where, - IN u16 *val) -{ TEMPLATE; } - -/** - * xge_os_pci_write16 - Write 16bit word into device PCI configuration. - * @pdev: Device context. Some OSs require device context to perform - * PIO and/or config space IO. - * @cfgh: PCI configuration space handle. - * @where: Offset in the PCI configuration space. - * @val: Value to write. - * - * Write 16bit value into the specified @offset in PCI - * configuration space. - * Returns: 0 - success, non-zero - failure. - */ -static inline int xge_os_pci_write16(IN pci_dev_h pdev, - IN pci_cfg_h cfgh, - IN int where, - IN u16 val) -{ TEMPLATE; } - -/** - * xge_os_pci_read32 - Read 32bit word from device PCI configuration. - * @pdev: Device context. Some OSs require device context to perform - * PIO and/or config space IO. - * @cfgh: PCI configuration space handle. - * @where: Offset in the PCI configuration space. - * @val: Address of 32bit result. - * - * Read 32bit value from the specified PCI configuration space at the - * specified offset. - * Returns: 0 - success, non-zero - failure. - */ -static inline int xge_os_pci_read32(IN pci_dev_h pdev, - IN pci_cfg_h cfgh, - IN int where, - IN u32 *val) -{ TEMPLATE; } - -/** - * xge_os_pci_write32 - Write 32bit word into device PCI configuration. - * @pdev: Device context. Some OSs require device context to perform - * PIO and/or config space IO. - * @cfgh: PCI configuration space handle. - * @where: Offset in the PCI configuration space. - * @val: Value to write. - * - * Write 32bit value into the specified @offset in PCI - * configuration space. - * Returns: 0 - success, non-zero - failure. - */ -static inline int xge_os_pci_write32(IN pci_dev_h pdev, - IN pci_cfg_h cfgh, - IN int where, - IN u32 val) -{ TEMPLATE; } - -/** - * xge_os_pio_mem_read8 - Read 1 byte from device memory mapped space. - * @pdev: Device context. Some OSs require device context to perform - * PIO and/or config space IO.. - * @regh: PCI configuration space handle. - * @addr: Address in device memory space. - * - * Returns: 1 byte value read from the specified (mapped) memory space address. - */ -static inline u8 xge_os_pio_mem_read8(IN pci_dev_h pdev, - IN pci_reg_h regh, - IN void *addr) -{ TEMPLATE; } - -/** - * xge_os_pio_mem_write64 - Write 1 byte into device memory mapped - * space. - * @pdev: Device context. Some OSs require device context to perform - * PIO and/or config space IO.. - * @regh: PCI configuration space handle. - * @val: Value to write. - * @addr: Address in device memory space. - * - * Write byte value into the specified (mapped) device memory space. - */ -static inline void xge_os_pio_mem_write8(IN pci_dev_h pdev, - IN pci_reg_h regh, - IN u8 val, - IN void *addr) -{ TEMPLATE; } - -/** - * xge_os_pio_mem_read16 - Read 16bit from device memory mapped space. - * @pdev: Device context. Some OSs require device context to perform - * PIO. - * @regh: PCI configuration space handle. - * @addr: Address in device memory space. - * - * Returns: 16bit value read from the specified (mapped) memory space address. - */ -static inline u16 xge_os_pio_mem_read16(IN pci_dev_h pdev, - IN pci_reg_h regh, - IN void *addr) -{ -TEMPLATE; } - -/** - * xge_os_pio_mem_write16 - Write 16bit into device memory mapped space. - * @pdev: Device context. Some OSs require device context to perform - * PIO. - * @regh: PCI configuration space handle. - * @val: Value to write. - * @addr: Address in device memory space. - * - * Write 16bit value into the specified (mapped) device memory space. - */ -static inline void xge_os_pio_mem_write16(IN pci_dev_h pdev, - IN pci_reg_h regh, - IN u16 val, - IN void *addr) -{ TEMPLATE; } - -/** - * xge_os_pio_mem_read32 - Read 32bit from device memory mapped space. - * @pdev: Device context. Some OSs require device context to perform - * PIO. - * @regh: PCI configuration space handle. - * @addr: Address in device memory space. - * - * Returns: 32bit value read from the specified (mapped) memory space address. - */ -static inline u32 xge_os_pio_mem_read32(IN pci_dev_h pdev, - IN pci_reg_h regh, - IN void *addr) -{ TEMPLATE; } - -/** - * xge_os_pio_mem_write32 - Write 32bit into device memory space. - * @pdev: Device context. Some OSs require device context to perform - * PIO. - * @regh: PCI configuration space handle. - * @val: Value to write. - * @addr: Address in device memory space. - * - * Write 32bit value into the specified (mapped) device memory space. - */ -static inline void xge_os_pio_mem_write32(IN pci_dev_h pdev, - IN pci_reg_h regh, - IN u32 val, - IN void *addr) -{ TEMPLATE; } - -/** - * xge_os_pio_mem_read64 - Read 64bit from device memory mapped space. - * @pdev: Device context. Some OSs require device context to perform - * PIO. - * @regh: PCI configuration space handle. - * @addr: Address in device memory space. - * - * Returns: 64bit value read from the specified (mapped) memory space address. - */ -static inline u64 xge_os_pio_mem_read64(IN pci_dev_h pdev, - IN pci_reg_h regh, - IN void *addr) -{ TEMPLATE; } - -/** - * xge_os_pio_mem_write64 - Write 64bit into device memory space. - * @pdev: Device context. Some OSs require device context to perform - * PIO. - * @regh: PCI configuration space handle. - * @val: Value to write. - * @addr: Address in device memory space. - * - * Write 64bit value into the specified (mapped) device memory space. - */ -static inline void xge_os_pio_mem_write64(IN pci_dev_h pdev, - IN pci_reg_h regh, - IN u64 val, - IN void *addr) -{ TEMPLATE; } - -/** - * xge_os_flush_bridge - Flush the bridge. - * @pdev: Device context. Some OSs require device context to perform - * PIO. - * @regh: PCI configuration space handle. - * @addr: Address in device memory space. - * - * Flush the bridge. - */ -static inline void xge_os_flush_bridge(IN pci_dev_h pdev, - IN pci_reg_h regh, - IN void *addr) -{ TEMPLATE; } - -/** - * xge_os_dma_map - Map DMA-able memory block to, or from, or - * to-and-from device. - * @pdev: Device context. Used to allocate/pin/map/unmap DMA-able memory. - * @dmah: DMA handle used to map the memory block. Obtained via - * xge_os_dma_malloc(). - * @vaddr: Virtual address of the DMA-able memory. - * @size: Size (in bytes) to be mapped. - * @dir: Direction of this operation (XGE_OS_DMA_DIR_TODEVICE, etc.) - * @dma_flags: XGE_OS_DMA_CACHELINE_ALIGNED, - * XGE_OS_DMA_STREAMING, - * XGE_OS_DMA_CONSISTENT - * Note that the last two flags are mutually exclusive. - * - * Map a single memory block. - * - * Returns: DMA address of the memory block, - * XGE_OS_INVALID_DMA_ADDR on failure. - * - * See also: xge_os_dma_malloc(), xge_os_dma_unmap(), - * xge_os_dma_sync(). - */ -static inline dma_addr_t xge_os_dma_map(IN pci_dev_h pdev, - IN pci_dma_h dmah, - IN void *vaddr, - IN size_t size, - IN int dir, - IN int dma_flags) -{ TEMPLATE; } - -/** - * xge_os_dma_unmap - Unmap DMA-able memory. - * @pdev: Device context. Used to allocate/pin/map/unmap DMA-able memory. - * @dmah: DMA handle used to map the memory block. Obtained via - * xge_os_dma_malloc(). - * @dma_addr: DMA address of the block. Obtained via xge_os_dma_map(). - * @size: Size (in bytes) to be unmapped. - * @dir: Direction of this operation (XGE_OS_DMA_DIR_TODEVICE, etc.) - * - * Unmap a single DMA-able memory block that was previously mapped - * using xge_os_dma_map(). - * See also: xge_os_dma_malloc(), xge_os_dma_map(). - */ -static inline void xge_os_dma_unmap(IN pci_dev_h pdev, - IN pci_dma_h dmah, - IN dma_addr_t dma_addr, - IN size_t size, - IN int dir) -{ TEMPLATE; } - -/** - * xge_os_dma_sync - Synchronize mapped memory. - * @pdev: Device context. Used to allocate/pin/map/unmap DMA-able memory. - * @dmah: DMA handle used to map the memory block. Obtained via - * xge_os_dma_malloc(). - * @dma_addr: DMA address of the block. Obtained via xge_os_dma_map(). - * @dma_offset: Offset from start of the blocke. Used by Solaris only. - * @length: Size of the block. - * @dir: Direction of this operation (XGE_OS_DMA_DIR_TODEVICE, etc.) - * - * Make physical and CPU memory consistent for a single - * streaming mode DMA translation. - * This API compiles to NOP on cache-coherent platforms. - * On non cache-coherent platforms, depending on the direction - * of the "sync" operation, this API will effectively - * either invalidate CPU cache (that might contain old data), - * or flush CPU cache to update physical memory. - * See also: xge_os_dma_malloc(), xge_os_dma_map(), - * xge_os_dma_unmap(). - */ -static inline void xge_os_dma_sync(IN pci_dev_h pdev, - IN pci_dma_h dmah, - IN dma_addr_t dma_addr, - IN u64 dma_offset, - IN size_t length, - IN int dir) -{ TEMPLATE; } - -#endif /* XGE_OS_TEMPLATE_H */ diff --git a/sys/dev/nxge/include/xge-queue.h b/sys/dev/nxge/include/xge-queue.h index 6745888..c38ffb8 100644 --- a/sys/dev/nxge/include/xge-queue.h +++ b/sys/dev/nxge/include/xge-queue.h @@ -26,14 +26,6 @@ * $FreeBSD$ */ -/* - * FileName : xge-queue.h - * - * Description: serialized event queue - * - * Created: 7 June 2004 - */ - #ifndef XGE_QUEUE_H #define XGE_QUEUE_H @@ -44,8 +36,8 @@ __EXTERN_BEGIN_DECLS -#define XGE_QUEUE_BUF_SIZE 0x1000 -#define XGE_DEFAULT_EVENT_MAX_DATA_SIZE 16 +#define XGE_QUEUE_BUF_SIZE 0x1000 +#define XGE_DEFAULT_EVENT_MAX_DATA_SIZE 16 /** * enum xge_queue_status_e - Enumerates return codes of the xge_queue @@ -61,11 +53,11 @@ __EXTERN_BEGIN_DECLS * and xge_queue_produce() APIs. */ typedef enum xge_queue_status_e { - XGE_QUEUE_OK = 0, - XGE_QUEUE_IS_FULL = 1, - XGE_QUEUE_IS_EMPTY = 2, - XGE_QUEUE_OUT_OF_MEMORY = 3, - XGE_QUEUE_NOT_ENOUGH_SPACE = 4 + XGE_QUEUE_OK = 0, + XGE_QUEUE_IS_FULL = 1, + XGE_QUEUE_IS_EMPTY = 2, + XGE_QUEUE_OUT_OF_MEMORY = 3, + XGE_QUEUE_NOT_ENOUGH_SPACE = 4 } xge_queue_status_e; typedef void* xge_queue_h; @@ -86,11 +78,11 @@ typedef void* xge_queue_h; * See also: xge_queue_t{}. */ typedef struct xge_queue_item_t { - xge_list_t item; - xge_hal_event_e event_type; - int data_size; - int is_critical; - void *context; + xge_list_t item; + xge_hal_event_e event_type; + int data_size; + int is_critical; + void *context; } xge_queue_item_t; /** @@ -114,7 +106,7 @@ typedef void (*xge_queued_f) (void *data, int event_type); * produce/consume operations. * @lock: Lock for queue operations(syncronization purpose). * @pages_initial:Number of pages to be initially allocated at the time - * of queue creation. + * of queue creation. * @pages_max: Max number of pages that can be allocated in the queue. * @pages_current: Number of pages currently allocated * @list_head: Points to the list of queue elements that are produced, but yet @@ -135,26 +127,26 @@ typedef void (*xge_queued_f) (void *data, int event_type); * See also: xge_queue_item_t{}. */ typedef struct xge_queue_t { - void *start_ptr; - void *end_ptr; - void *head_ptr; - void *tail_ptr; - spinlock_t lock; - unsigned int pages_initial; - unsigned int pages_max; - unsigned int pages_current; - xge_list_t list_head; - pci_dev_h pdev; - pci_irq_h irqh; - xge_queued_f queued_func; - void *queued_data; - int has_critical_event; + void *start_ptr; + void *end_ptr; + void *head_ptr; + void *tail_ptr; + spinlock_t lock; + unsigned int pages_initial; + unsigned int pages_max; + unsigned int pages_current; + xge_list_t list_head; + pci_dev_h pdev; + pci_irq_h irqh; + xge_queued_f queued_func; + void *queued_data; + int has_critical_event; } xge_queue_t; /* ========================== PUBLIC API ================================= */ xge_queue_h xge_queue_create(pci_dev_h pdev, pci_irq_h irqh, int pages_initial, - int pages_max, xge_queued_f queued_func, void *queued_data); + int pages_max, xge_queued_f queued_func, void *queued_data); void xge_queue_destroy(xge_queue_h queueh); @@ -162,7 +154,7 @@ void* xge_queue_item_data(xge_queue_item_t *item); xge_queue_status_e xge_queue_produce(xge_queue_h queueh, int event_type, void *context, - int is_critical, const int data_size, void *data); + int is_critical, const int data_size, void *data); static inline xge_queue_status_e xge_queue_produce_context(xge_queue_h queueh, int event_type, void *context) { @@ -170,7 +162,7 @@ xge_queue_produce_context(xge_queue_h queueh, int event_type, void *context) { } xge_queue_status_e xge_queue_consume(xge_queue_h queueh, int data_max_size, - xge_queue_item_t *item); + xge_queue_item_t *item); void xge_queue_flush(xge_queue_h queueh); diff --git a/sys/dev/nxge/include/xgehal-channel.h b/sys/dev/nxge/include/xgehal-channel.h index 8d82530..d786649 100644 --- a/sys/dev/nxge/include/xgehal-channel.h +++ b/sys/dev/nxge/include/xgehal-channel.h @@ -26,14 +26,6 @@ * $FreeBSD$ */ -/* - * FileName : xgehal-channel.h - * - * Description: HAL channel object functionality - * - * Created: 19 May 2004 - */ - #ifndef XGE_HAL_CHANNEL_H #define XGE_HAL_CHANNEL_H @@ -80,9 +72,9 @@ typedef enum xge_hal_channel_type_e { * Channel opening flags. Reserved for future usage. */ typedef enum xge_hal_channel_flag_e { - XGE_HAL_CHANNEL_FLAG_NONE = 0x0, - XGE_HAL_CHANNEL_FLAG_USE_TX_LOCK = 0x1, - XGE_HAL_CHANNEL_FLAG_FREE_RXD = 0x2 + XGE_HAL_CHANNEL_FLAG_NONE = 0x0, + XGE_HAL_CHANNEL_FLAG_USE_TX_LOCK = 0x1, + XGE_HAL_CHANNEL_FLAG_FREE_RXD = 0x2 } xge_hal_channel_flag_e; /** @@ -101,10 +93,10 @@ typedef enum xge_hal_channel_flag_e { * See also: xge_hal_channel_dtr_term_f{}. */ typedef enum xge_hal_dtr_state_e { - XGE_HAL_DTR_STATE_NONE = 0, - XGE_HAL_DTR_STATE_AVAIL = 1, - XGE_HAL_DTR_STATE_POSTED = 2, - XGE_HAL_DTR_STATE_FREED = 3 + XGE_HAL_DTR_STATE_NONE = 0, + XGE_HAL_DTR_STATE_AVAIL = 1, + XGE_HAL_DTR_STATE_POSTED = 2, + XGE_HAL_DTR_STATE_FREED = 3 } xge_hal_dtr_state_e; /** @@ -120,8 +112,8 @@ typedef enum xge_hal_dtr_state_e { * the memory (including DMA-able memory) used for channel operation. */ typedef enum xge_hal_channel_reopen_e { - XGE_HAL_CHANNEL_RESET_ONLY = 1, - XGE_HAL_CHANNEL_OC_NORMAL = 2 + XGE_HAL_CHANNEL_RESET_ONLY = 1, + XGE_HAL_CHANNEL_OC_NORMAL = 2 } xge_hal_channel_reopen_e; /** @@ -168,8 +160,8 @@ typedef enum xge_hal_channel_reopen_e { * xge_hal_ring_dtr_next_completed(), xge_hal_channel_dtr_term_f{}. */ typedef xge_hal_status_e (*xge_hal_channel_callback_f) - (xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, - u8 t_code, void *userdata); + (xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, + u8 t_code, void *userdata); /** * function xge_hal_channel_dtr_init_f - Initialize descriptor callback. @@ -192,11 +184,11 @@ typedef xge_hal_status_e (*xge_hal_channel_callback_f) * See also: xge_hal_channel_attr_t{}, xge_hal_channel_dtr_term_f{}. */ typedef xge_hal_status_e (*xge_hal_channel_dtr_init_f) - (xge_hal_channel_h channelh, - xge_hal_dtr_h dtrh, - int index, - void *userdata, - xge_hal_channel_reopen_e reopen); + (xge_hal_channel_h channelh, + xge_hal_dtr_h dtrh, + int index, + void *userdata, + xge_hal_channel_reopen_e reopen); /** * function xge_hal_channel_dtr_term_f - Terminate descriptor callback. @@ -220,10 +212,10 @@ typedef xge_hal_status_e (*xge_hal_channel_dtr_init_f) * See also: xge_hal_channel_attr_t{}, xge_hal_channel_dtr_init_f{}. */ typedef void (*xge_hal_channel_dtr_term_f) (xge_hal_channel_h channelh, - xge_hal_dtr_h dtrh, - xge_hal_dtr_state_e state, - void *userdata, - xge_hal_channel_reopen_e reopen); + xge_hal_dtr_h dtrh, + xge_hal_dtr_state_e state, + void *userdata, + xge_hal_channel_reopen_e reopen); /** @@ -257,18 +249,15 @@ typedef void (*xge_hal_channel_dtr_term_f) (xge_hal_channel_h channelh, * Usage: See ex_open{}. */ typedef struct xge_hal_channel_attr_t { - xge_hal_channel_type_e type; -#ifdef XGEHAL_RNIC - u32 vp_id; -#endif - int post_qid; - int compl_qid; - xge_hal_channel_callback_f callback; - xge_hal_channel_dtr_init_f dtr_init; - xge_hal_channel_dtr_term_f dtr_term; - void *userdata; - int per_dtr_space; - xge_hal_channel_flag_e flags; + xge_hal_channel_type_e type; + int post_qid; + int compl_qid; + xge_hal_channel_callback_f callback; + xge_hal_channel_dtr_init_f dtr_init; + xge_hal_channel_dtr_term_f dtr_term; + void *userdata; + int per_dtr_space; + xge_hal_channel_flag_e flags; } xge_hal_channel_attr_t; /* @@ -353,73 +342,70 @@ typedef struct xge_hal_channel_attr_t { */ typedef struct { /* complete/free section */ - xge_list_t item; - xge_hal_channel_callback_f callback; - void **free_arr; - int length; - int free_length; + xge_list_t item; + xge_hal_channel_callback_f callback; + void **free_arr; + int length; + int free_length; #if defined(XGE_HAL_RX_MULTI_FREE_IRQ) || defined(XGE_HAL_TX_MULTI_FREE_IRQ) || \ - defined(XGE_HAL_RX_MULTI_FREE) || defined(XGE_HAL_TX_MULTI_FREE) - spinlock_t free_lock; + defined(XGE_HAL_RX_MULTI_FREE) || defined(XGE_HAL_TX_MULTI_FREE) + spinlock_t free_lock; #endif - int compl_index; - unsigned int usage_cnt; - unsigned int poll_bytes; - int unused0; + int compl_index; + unsigned int usage_cnt; + unsigned int poll_bytes; /* reserve/post data path section */ + int terminating; #ifdef __XGE_WIN__ - int __xge_os_attr_cacheline_aligned - post_index; + int __xge_os_attr_cacheline_aligned + post_index; #else - int post_index - __xge_os_attr_cacheline_aligned; + int post_index + __xge_os_attr_cacheline_aligned; #endif - spinlock_t reserve_lock; - spinlock_t post_lock; + spinlock_t reserve_lock; + spinlock_t post_lock; - void **reserve_arr; - int reserve_length; - int reserve_threshold; - int reserve_top; + void **reserve_arr; + int reserve_length; + int reserve_threshold; + int reserve_top; int unused1; /* common section */ - xge_hal_device_h devh; + xge_hal_device_h devh; pci_dev_h pdev; - pci_reg_h regh0; - pci_reg_h regh1; - void *userdata; - void **work_arr; - void **saved_arr; - void **orig_arr; - xge_hal_stats_channel_info_t stats; + pci_reg_h regh0; + pci_reg_h regh1; + void *userdata; + void **work_arr; + void **saved_arr; + void **orig_arr; + xge_hal_stats_channel_info_t stats; /* slow section */ - xge_hal_channel_type_e type; -#ifdef XGEHAL_RNIC - u32 vp_id; -#endif - int post_qid; - int compl_qid; - xge_hal_channel_flag_e flags; - int reserve_initial; - int reserve_max; - int is_open; - int per_dtr_space; - xge_hal_channel_dtr_term_f dtr_term; - xge_hal_channel_dtr_init_f dtr_init; + xge_hal_channel_type_e type; + int post_qid; + int compl_qid; + xge_hal_channel_flag_e flags; + int reserve_initial; + int reserve_max; + int is_open; + int per_dtr_space; + xge_hal_channel_dtr_term_f dtr_term; + xge_hal_channel_dtr_init_f dtr_init; /* MSI stuff */ - u32 msi_msg; - u8 rti; - u8 tti; + u32 msi_msg; + u8 rti; + u8 tti; u16 unused2; /* MSI-X stuff */ - u64 msix_address; - u32 msix_data; - int msix_idx; - volatile int in_interrupt; - unsigned int magic; + u64 msix_address; + u32 msix_data; + int msix_idx; + volatile int in_interrupt; + unsigned int magic; #ifdef __XGE_WIN__ } __xge_os_attr_cacheline_aligned xge_hal_channel_t ; #else @@ -430,17 +416,14 @@ typedef struct { xge_hal_status_e __hal_channel_initialize(xge_hal_channel_h channelh, - xge_hal_channel_attr_t *attr, void **reserve_arr, - int reserve_initial, int reserve_max, int reserve_threshold); + xge_hal_channel_attr_t *attr, void **reserve_arr, + int reserve_initial, int reserve_max, int reserve_threshold); void __hal_channel_terminate(xge_hal_channel_h channelh); xge_hal_channel_t* __hal_channel_allocate(xge_hal_device_h devh, int post_qid, -#ifdef XGEHAL_RNIC - u32 vp_id, -#endif - xge_hal_channel_type_e type); + xge_hal_channel_type_e type); void __hal_channel_free(xge_hal_channel_t *channel); @@ -468,7 +451,7 @@ __hal_channel_dtr_dealloc(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void __hal_channel_dtr_restore(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, - int offset); + int offset); /* ========================== CHANNEL PUBLIC API ========================= */ @@ -483,7 +466,7 @@ xge_hal_channel_id(xge_hal_channel_h channelh); __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int xge_hal_check_alignment(dma_addr_t dma_pointer, int size, int alignment, - int copy_size); + int copy_size); #else /* XGE_FASTPATH_EXTERN */ #define __HAL_STATIC_CHANNEL static @@ -493,14 +476,14 @@ xge_hal_check_alignment(dma_addr_t dma_pointer, int size, int alignment, xge_hal_status_e xge_hal_channel_open(xge_hal_device_h hldev, xge_hal_channel_attr_t *attr, - xge_hal_channel_h *channel, - xge_hal_channel_reopen_e reopen); + xge_hal_channel_h *channel, + xge_hal_channel_reopen_e reopen); void xge_hal_channel_close(xge_hal_channel_h channelh, - xge_hal_channel_reopen_e reopen); + xge_hal_channel_reopen_e reopen); void xge_hal_channel_abort(xge_hal_channel_h channelh, - xge_hal_channel_reopen_e reopen); + xge_hal_channel_reopen_e reopen); __EXTERN_END_DECLS diff --git a/sys/dev/nxge/include/xgehal-config.h b/sys/dev/nxge/include/xgehal-config.h index c7bde29..c320b4a 100644 --- a/sys/dev/nxge/include/xgehal-config.h +++ b/sys/dev/nxge/include/xgehal-config.h @@ -26,14 +26,6 @@ * $FreeBSD$ */ -/* - * FileName : xgehal-config.h - * - * Description: Xframe configuration. - * - * Created: 14 May 2004 - */ - #ifndef XGE_HAL_CONFIG_H #define XGE_HAL_CONFIG_H @@ -43,14 +35,10 @@ __EXTERN_BEGIN_DECLS -#define XGE_HAL_DEFAULT_USE_HARDCODE -1 +#define XGE_HAL_DEFAULT_USE_HARDCODE -1 -#ifdef XGEHAL_RNIC -#define XGE_HAL_MAX_VIRTUAL_PATHS 17 -#else -#define XGE_HAL_MAX_VIRTUAL_PATHS 8 -#endif -#define XGE_HAL_MAX_INTR_PER_VP 4 +#define XGE_HAL_MAX_VIRTUAL_PATHS 8 +#define XGE_HAL_MAX_INTR_PER_VP 4 /** @@ -91,51 +79,51 @@ __EXTERN_BEGIN_DECLS */ typedef struct xge_hal_tti_config_t { - int enabled; -#define XGE_HAL_TTI_ENABLE 1 -#define XGE_HAL_TTI_DISABLE 0 + int enabled; +#define XGE_HAL_TTI_ENABLE 1 +#define XGE_HAL_TTI_DISABLE 0 /* Line utilization interrupts */ - int urange_a; -#define XGE_HAL_MIN_TX_URANGE_A 0 -#define XGE_HAL_MAX_TX_URANGE_A 100 + int urange_a; +#define XGE_HAL_MIN_TX_URANGE_A 0 +#define XGE_HAL_MAX_TX_URANGE_A 100 - int ufc_a; -#define XGE_HAL_MIN_TX_UFC_A 0 -#define XGE_HAL_MAX_TX_UFC_A 65535 + int ufc_a; +#define XGE_HAL_MIN_TX_UFC_A 0 +#define XGE_HAL_MAX_TX_UFC_A 65535 - int urange_b; -#define XGE_HAL_MIN_TX_URANGE_B 0 -#define XGE_HAL_MAX_TX_URANGE_B 100 + int urange_b; +#define XGE_HAL_MIN_TX_URANGE_B 0 +#define XGE_HAL_MAX_TX_URANGE_B 100 - int ufc_b; -#define XGE_HAL_MIN_TX_UFC_B 0 -#define XGE_HAL_MAX_TX_UFC_B 65535 + int ufc_b; +#define XGE_HAL_MIN_TX_UFC_B 0 +#define XGE_HAL_MAX_TX_UFC_B 65535 - int urange_c; -#define XGE_HAL_MIN_TX_URANGE_C 0 -#define XGE_HAL_MAX_TX_URANGE_C 100 + int urange_c; +#define XGE_HAL_MIN_TX_URANGE_C 0 +#define XGE_HAL_MAX_TX_URANGE_C 100 - int ufc_c; -#define XGE_HAL_MIN_TX_UFC_C 0 -#define XGE_HAL_MAX_TX_UFC_C 65535 + int ufc_c; +#define XGE_HAL_MIN_TX_UFC_C 0 +#define XGE_HAL_MAX_TX_UFC_C 65535 - int ufc_d; -#define XGE_HAL_MIN_TX_UFC_D 0 -#define XGE_HAL_MAX_TX_UFC_D 65535 + int ufc_d; +#define XGE_HAL_MIN_TX_UFC_D 0 +#define XGE_HAL_MAX_TX_UFC_D 65535 - int timer_val_us; -#define XGE_HAL_MIN_TX_TIMER_VAL 0 -#define XGE_HAL_MAX_TX_TIMER_VAL 65535 + int timer_val_us; +#define XGE_HAL_MIN_TX_TIMER_VAL 0 +#define XGE_HAL_MAX_TX_TIMER_VAL 65535 - int timer_ac_en; -#define XGE_HAL_MIN_TX_TIMER_AC_EN 0 -#define XGE_HAL_MAX_TX_TIMER_AC_EN 1 + int timer_ac_en; +#define XGE_HAL_MIN_TX_TIMER_AC_EN 0 +#define XGE_HAL_MAX_TX_TIMER_AC_EN 1 - int timer_ci_en; -#define XGE_HAL_MIN_TX_TIMER_CI_EN 0 -#define XGE_HAL_MAX_TX_TIMER_CI_EN 1 + int timer_ci_en; +#define XGE_HAL_MIN_TX_TIMER_CI_EN 0 +#define XGE_HAL_MAX_TX_TIMER_CI_EN 1 } xge_hal_tti_config_t; @@ -171,41 +159,41 @@ typedef struct xge_hal_tti_config_t { */ typedef struct xge_hal_rti_config_t { - int urange_a; -#define XGE_HAL_MIN_RX_URANGE_A 0 -#define XGE_HAL_MAX_RX_URANGE_A 127 + int urange_a; +#define XGE_HAL_MIN_RX_URANGE_A 0 +#define XGE_HAL_MAX_RX_URANGE_A 127 - int ufc_a; -#define XGE_HAL_MIN_RX_UFC_A 0 -#define XGE_HAL_MAX_RX_UFC_A 65535 + int ufc_a; +#define XGE_HAL_MIN_RX_UFC_A 0 +#define XGE_HAL_MAX_RX_UFC_A 65535 - int urange_b; -#define XGE_HAL_MIN_RX_URANGE_B 0 -#define XGE_HAL_MAX_RX_URANGE_B 127 + int urange_b; +#define XGE_HAL_MIN_RX_URANGE_B 0 +#define XGE_HAL_MAX_RX_URANGE_B 127 - int ufc_b; -#define XGE_HAL_MIN_RX_UFC_B 0 -#define XGE_HAL_MAX_RX_UFC_B 65535 + int ufc_b; +#define XGE_HAL_MIN_RX_UFC_B 0 +#define XGE_HAL_MAX_RX_UFC_B 65535 - int urange_c; -#define XGE_HAL_MIN_RX_URANGE_C 0 -#define XGE_HAL_MAX_RX_URANGE_C 127 + int urange_c; +#define XGE_HAL_MIN_RX_URANGE_C 0 +#define XGE_HAL_MAX_RX_URANGE_C 127 - int ufc_c; -#define XGE_HAL_MIN_RX_UFC_C 0 -#define XGE_HAL_MAX_RX_UFC_C 65535 + int ufc_c; +#define XGE_HAL_MIN_RX_UFC_C 0 +#define XGE_HAL_MAX_RX_UFC_C 65535 - int ufc_d; -#define XGE_HAL_MIN_RX_UFC_D 0 -#define XGE_HAL_MAX_RX_UFC_D 65535 + int ufc_d; +#define XGE_HAL_MIN_RX_UFC_D 0 +#define XGE_HAL_MAX_RX_UFC_D 65535 - int timer_ac_en; -#define XGE_HAL_MIN_RX_TIMER_AC_EN 0 -#define XGE_HAL_MAX_RX_TIMER_AC_EN 1 + int timer_ac_en; +#define XGE_HAL_MIN_RX_TIMER_AC_EN 0 +#define XGE_HAL_MAX_RX_TIMER_AC_EN 1 - int timer_val_us; -#define XGE_HAL_MIN_RX_TIMER_VAL 0 -#define XGE_HAL_MAX_RX_TIMER_VAL 65535 + int timer_val_us; +#define XGE_HAL_MIN_RX_TIMER_VAL 0 +#define XGE_HAL_MAX_RX_TIMER_VAL 65535 } xge_hal_rti_config_t; @@ -234,36 +222,36 @@ typedef struct xge_hal_rti_config_t { * See also: xge_hal_fifo_config_t{} */ typedef struct xge_hal_fifo_queue_t { - int max; - int initial; -#define XGE_HAL_MIN_FIFO_QUEUE_LENGTH 2 -#define XGE_HAL_MAX_FIFO_QUEUE_LENGTH 8192 + int max; + int initial; +#define XGE_HAL_MIN_FIFO_QUEUE_LENGTH 2 +#define XGE_HAL_MAX_FIFO_QUEUE_LENGTH 8192 - int intr; -#define XGE_HAL_MIN_FIFO_QUEUE_INTR 0 -#define XGE_HAL_MAX_FIFO_QUEUE_INTR 1 + int intr; +#define XGE_HAL_MIN_FIFO_QUEUE_INTR 0 +#define XGE_HAL_MAX_FIFO_QUEUE_INTR 1 - int intr_vector; -#define XGE_HAL_MIN_FIFO_QUEUE_INTR_VECTOR 0 -#define XGE_HAL_MAX_FIFO_QUEUE_INTR_VECTOR 64 + int intr_vector; +#define XGE_HAL_MIN_FIFO_QUEUE_INTR_VECTOR 0 +#define XGE_HAL_MAX_FIFO_QUEUE_INTR_VECTOR 64 - int no_snoop_bits; -#define XGE_HAL_MIN_FIFO_QUEUE_NO_SNOOP_DISABLED 0 -#define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_TXD 1 -#define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_BUFFER 2 -#define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_ALL 3 + int no_snoop_bits; +#define XGE_HAL_MIN_FIFO_QUEUE_NO_SNOOP_DISABLED 0 +#define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_TXD 1 +#define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_BUFFER 2 +#define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_ALL 3 - int priority; -#define XGE_HAL_MIN_FIFO_PRIORITY 0 -#define XGE_HAL_MAX_FIFO_PRIORITY 63 + int priority; +#define XGE_HAL_MIN_FIFO_PRIORITY 0 +#define XGE_HAL_MAX_FIFO_PRIORITY 63 - int configured; -#define XGE_HAL_MIN_FIFO_CONFIGURED 0 -#define XGE_HAL_MAX_FIFO_CONFIGURED 1 + int configured; +#define XGE_HAL_MIN_FIFO_CONFIGURED 0 +#define XGE_HAL_MAX_FIFO_CONFIGURED 1 -#define XGE_HAL_MAX_FIFO_TTI_NUM 7 -#define XGE_HAL_MAX_FIFO_TTI_RING_0 56 - xge_hal_tti_config_t tti[XGE_HAL_MAX_FIFO_TTI_NUM]; +#define XGE_HAL_MAX_FIFO_TTI_NUM 7 +#define XGE_HAL_MAX_FIFO_TTI_RING_0 56 + xge_hal_tti_config_t tti[XGE_HAL_MAX_FIFO_TTI_NUM]; } xge_hal_fifo_queue_t; @@ -293,30 +281,30 @@ typedef struct xge_hal_fifo_queue_t { * See also: xge_hal_ring_queue_t{}. */ typedef struct xge_hal_fifo_config_t { - int max_frags; -#define XGE_HAL_MIN_FIFO_FRAGS 1 -#define XGE_HAL_MAX_FIFO_FRAGS 256 + int max_frags; +#define XGE_HAL_MIN_FIFO_FRAGS 1 +#define XGE_HAL_MAX_FIFO_FRAGS 256 - int reserve_threshold; -#define XGE_HAL_MIN_FIFO_RESERVE_THRESHOLD 0 -#define XGE_HAL_MAX_FIFO_RESERVE_THRESHOLD 8192 + int reserve_threshold; +#define XGE_HAL_MIN_FIFO_RESERVE_THRESHOLD 0 +#define XGE_HAL_MAX_FIFO_RESERVE_THRESHOLD 8192 - int memblock_size; -#define XGE_HAL_MIN_FIFO_MEMBLOCK_SIZE 4096 -#define XGE_HAL_MAX_FIFO_MEMBLOCK_SIZE 131072 + int memblock_size; +#define XGE_HAL_MIN_FIFO_MEMBLOCK_SIZE 4096 +#define XGE_HAL_MAX_FIFO_MEMBLOCK_SIZE 131072 - int alignment_size; -#define XGE_HAL_MIN_ALIGNMENT_SIZE 0 -#define XGE_HAL_MAX_ALIGNMENT_SIZE 65536 + int alignment_size; +#define XGE_HAL_MIN_ALIGNMENT_SIZE 0 +#define XGE_HAL_MAX_ALIGNMENT_SIZE 65536 - int max_aligned_frags; + int max_aligned_frags; /* range: (1, @max_frags) */ -#define XGE_HAL_MIN_FIFO_NUM 1 -#define XGE_HAL_MAX_FIFO_NUM_HERC 8 -#define XGE_HAL_MAX_FIFO_NUM_TITAN (XGE_HAL_MAX_VIRTUAL_PATHS - 1) -#define XGE_HAL_MAX_FIFO_NUM (XGE_HAL_MAX_VIRTUAL_PATHS) - xge_hal_fifo_queue_t queue[XGE_HAL_MAX_FIFO_NUM]; +#define XGE_HAL_MIN_FIFO_NUM 1 +#define XGE_HAL_MAX_FIFO_NUM_HERC 8 +#define XGE_HAL_MAX_FIFO_NUM_TITAN (XGE_HAL_MAX_VIRTUAL_PATHS - 1) +#define XGE_HAL_MAX_FIFO_NUM (XGE_HAL_MAX_VIRTUAL_PATHS) + xge_hal_fifo_queue_t queue[XGE_HAL_MAX_FIFO_NUM]; } xge_hal_fifo_config_t; /** @@ -326,9 +314,9 @@ typedef struct xge_hal_fifo_config_t { * @src: Port is Source (default Destination) */ typedef struct xge_hal_rts_port_t { - int num; - int udp; - int src; + int num; + int udp; + int src; } xge_hal_rts_port_t; /** @@ -371,7 +359,7 @@ typedef struct xge_hal_rts_port_t { * Rx descriptors. Any subset of 8 available rings can be * "configured". * @rts_mac_en: 1 - To enable Receive MAC address steering. - * 0 - To disable Receive MAC address steering. + * 0 - To disable Receive MAC address steering. * @rth_en: TBD * @rts_port_en: TBD * @rts_ports: TBD @@ -384,68 +372,68 @@ typedef struct xge_hal_rts_port_t { * See also: xge_hal_fifo_config_t{}. */ typedef struct xge_hal_ring_queue_t { - int max; - int initial; -#define XGE_HAL_MIN_RING_QUEUE_BLOCKS 1 -#define XGE_HAL_MAX_RING_QUEUE_BLOCKS 64 + int max; + int initial; +#define XGE_HAL_MIN_RING_QUEUE_BLOCKS 1 +#define XGE_HAL_MAX_RING_QUEUE_BLOCKS 64 - int buffer_mode; -#define XGE_HAL_RING_QUEUE_BUFFER_MODE_1 1 -#define XGE_HAL_RING_QUEUE_BUFFER_MODE_2 2 -#define XGE_HAL_RING_QUEUE_BUFFER_MODE_3 3 -#define XGE_HAL_RING_QUEUE_BUFFER_MODE_5 5 + int buffer_mode; +#define XGE_HAL_RING_QUEUE_BUFFER_MODE_1 1 +#define XGE_HAL_RING_QUEUE_BUFFER_MODE_2 2 +#define XGE_HAL_RING_QUEUE_BUFFER_MODE_3 3 +#define XGE_HAL_RING_QUEUE_BUFFER_MODE_5 5 - int dram_size_mb; -#define XGE_HAL_MIN_RING_QUEUE_SIZE 0 -#define XGE_HAL_MAX_RING_QUEUE_SIZE_XENA 64 -#define XGE_HAL_MAX_RING_QUEUE_SIZE_HERC 32 + int dram_size_mb; +#define XGE_HAL_MIN_RING_QUEUE_SIZE 0 +#define XGE_HAL_MAX_RING_QUEUE_SIZE_XENA 64 +#define XGE_HAL_MAX_RING_QUEUE_SIZE_HERC 32 - int intr_vector; -#define XGE_HAL_MIN_RING_QUEUE_INTR_VECTOR 0 -#define XGE_HAL_MAX_RING_QUEUE_INTR_VECTOR 64 + int intr_vector; +#define XGE_HAL_MIN_RING_QUEUE_INTR_VECTOR 0 +#define XGE_HAL_MAX_RING_QUEUE_INTR_VECTOR 64 - int backoff_interval_us; -#define XGE_HAL_MIN_BACKOFF_INTERVAL_US 1 -#define XGE_HAL_MAX_BACKOFF_INTERVAL_US 125000 + int backoff_interval_us; +#define XGE_HAL_MIN_BACKOFF_INTERVAL_US 1 +#define XGE_HAL_MAX_BACKOFF_INTERVAL_US 125000 - int max_frm_len; -#define XGE_HAL_MIN_MAX_FRM_LEN -1 -#define XGE_HAL_MAX_MAX_FRM_LEN 9622 + int max_frm_len; +#define XGE_HAL_MIN_MAX_FRM_LEN -1 +#define XGE_HAL_MAX_MAX_FRM_LEN 9622 - int priority; -#define XGE_HAL_MIN_RING_PRIORITY 0 -#define XGE_HAL_MAX_RING_PRIORITY 7 + int priority; +#define XGE_HAL_MIN_RING_PRIORITY 0 +#define XGE_HAL_MAX_RING_PRIORITY 7 - int no_snoop_bits; -#define XGE_HAL_MIN_RING_QUEUE_NO_SNOOP_DISABLED 0 -#define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_RXD 1 -#define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_BUFFER 2 -#define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_ALL 3 + int no_snoop_bits; +#define XGE_HAL_MIN_RING_QUEUE_NO_SNOOP_DISABLED 0 +#define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_RXD 1 +#define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_BUFFER 2 +#define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_ALL 3 - int indicate_max_pkts; -#define XGE_HAL_MIN_RING_INDICATE_MAX_PKTS 1 -#define XGE_HAL_MAX_RING_INDICATE_MAX_PKTS 65536 + int indicate_max_pkts; +#define XGE_HAL_MIN_RING_INDICATE_MAX_PKTS 1 +#define XGE_HAL_MAX_RING_INDICATE_MAX_PKTS 65536 - int configured; -#define XGE_HAL_MIN_RING_CONFIGURED 0 -#define XGE_HAL_MAX_RING_CONFIGURED 1 + int configured; +#define XGE_HAL_MIN_RING_CONFIGURED 0 +#define XGE_HAL_MAX_RING_CONFIGURED 1 - int rts_mac_en; -#define XGE_HAL_MIN_RING_RTS_MAC_EN 0 -#define XGE_HAL_MAX_RING_RTS_MAC_EN 1 + int rts_mac_en; +#define XGE_HAL_MIN_RING_RTS_MAC_EN 0 +#define XGE_HAL_MAX_RING_RTS_MAC_EN 1 - int rth_en; -#define XGE_HAL_MIN_RING_RTH_EN 0 -#define XGE_HAL_MAX_RING_RTH_EN 1 + int rth_en; +#define XGE_HAL_MIN_RING_RTH_EN 0 +#define XGE_HAL_MAX_RING_RTH_EN 1 - int rts_port_en; -#define XGE_HAL_MIN_RING_RTS_PORT_EN 0 -#define XGE_HAL_MAX_RING_RTS_PORT_EN 1 + int rts_port_en; +#define XGE_HAL_MIN_RING_RTS_PORT_EN 0 +#define XGE_HAL_MAX_RING_RTS_PORT_EN 1 -#define XGE_HAL_MAX_STEERABLE_PORTS 32 - xge_hal_rts_port_t rts_ports[XGE_HAL_MAX_STEERABLE_PORTS]; +#define XGE_HAL_MAX_STEERABLE_PORTS 32 + xge_hal_rts_port_t rts_ports[XGE_HAL_MAX_STEERABLE_PORTS]; - xge_hal_rti_config_t rti; + xge_hal_rti_config_t rti; } xge_hal_ring_queue_t; @@ -465,23 +453,23 @@ typedef struct xge_hal_ring_queue_t { */ typedef struct xge_hal_ring_config_t { - int memblock_size; -#define XGE_HAL_MIN_RING_MEMBLOCK_SIZE 4096 -#define XGE_HAL_MAX_RING_MEMBLOCK_SIZE 131072 + int memblock_size; +#define XGE_HAL_MIN_RING_MEMBLOCK_SIZE 4096 +#define XGE_HAL_MAX_RING_MEMBLOCK_SIZE 131072 - int scatter_mode; -#define XGE_HAL_RING_QUEUE_SCATTER_MODE_A 0 -#define XGE_HAL_RING_QUEUE_SCATTER_MODE_B 1 + int scatter_mode; +#define XGE_HAL_RING_QUEUE_SCATTER_MODE_A 0 +#define XGE_HAL_RING_QUEUE_SCATTER_MODE_B 1 - int strip_vlan_tag; -#define XGE_HAL_RING_DONOT_STRIP_VLAN_TAG 0 -#define XGE_HAL_RING_STRIP_VLAN_TAG 1 + int strip_vlan_tag; +#define XGE_HAL_RING_DONOT_STRIP_VLAN_TAG 0 +#define XGE_HAL_RING_STRIP_VLAN_TAG 1 -#define XGE_HAL_MIN_RING_NUM 1 -#define XGE_HAL_MAX_RING_NUM_HERC 8 -#define XGE_HAL_MAX_RING_NUM_TITAN (XGE_HAL_MAX_VIRTUAL_PATHS - 1) -#define XGE_HAL_MAX_RING_NUM (XGE_HAL_MAX_VIRTUAL_PATHS) - xge_hal_ring_queue_t queue[XGE_HAL_MAX_RING_NUM]; +#define XGE_HAL_MIN_RING_NUM 1 +#define XGE_HAL_MAX_RING_NUM_HERC 8 +#define XGE_HAL_MAX_RING_NUM_TITAN (XGE_HAL_MAX_VIRTUAL_PATHS - 1) +#define XGE_HAL_MAX_RING_NUM (XGE_HAL_MAX_VIRTUAL_PATHS) + xge_hal_ring_queue_t queue[XGE_HAL_MAX_RING_NUM]; } xge_hal_ring_config_t; @@ -520,103 +508,50 @@ typedef struct xge_hal_ring_config_t { * corresponding include file. */ typedef struct xge_hal_mac_config_t { - int media; -#define XGE_HAL_MIN_MEDIA 0 -#define XGE_HAL_MEDIA_SR 0 -#define XGE_HAL_MEDIA_SW 1 -#define XGE_HAL_MEDIA_LR 2 -#define XGE_HAL_MEDIA_LW 3 -#define XGE_HAL_MEDIA_ER 4 -#define XGE_HAL_MEDIA_EW 5 -#define XGE_HAL_MAX_MEDIA 5 - - int tmac_util_period; -#define XGE_HAL_MIN_TMAC_UTIL_PERIOD 0 -#define XGE_HAL_MAX_TMAC_UTIL_PERIOD 15 - - int rmac_util_period; -#define XGE_HAL_MIN_RMAC_UTIL_PERIOD 0 -#define XGE_HAL_MAX_RMAC_UTIL_PERIOD 15 - - int rmac_bcast_en; -#define XGE_HAL_MIN_RMAC_BCAST_EN 0 -#define XGE_HAL_MAX_RMAC_BCAST_EN 1 - - int rmac_pause_gen_en; -#define XGE_HAL_MIN_RMAC_PAUSE_GEN_EN 0 -#define XGE_HAL_MAX_RMAC_PAUSE_GEN_EN 1 - - int rmac_pause_rcv_en; -#define XGE_HAL_MIN_RMAC_PAUSE_RCV_EN 0 -#define XGE_HAL_MAX_RMAC_PAUSE_RCV_EN 1 - - int rmac_pause_time; -#define XGE_HAL_MIN_RMAC_HIGH_PTIME 16 -#define XGE_HAL_MAX_RMAC_HIGH_PTIME 65535 - - int mc_pause_threshold_q0q3; -#define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q0Q3 0 -#define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q0Q3 254 - - int mc_pause_threshold_q4q7; -#define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q4Q7 0 -#define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q4Q7 254 + int media; +#define XGE_HAL_MIN_MEDIA 0 +#define XGE_HAL_MEDIA_SR 0 +#define XGE_HAL_MEDIA_SW 1 +#define XGE_HAL_MEDIA_LR 2 +#define XGE_HAL_MEDIA_LW 3 +#define XGE_HAL_MEDIA_ER 4 +#define XGE_HAL_MEDIA_EW 5 +#define XGE_HAL_MAX_MEDIA 5 + + int tmac_util_period; +#define XGE_HAL_MIN_TMAC_UTIL_PERIOD 0 +#define XGE_HAL_MAX_TMAC_UTIL_PERIOD 15 + + int rmac_util_period; +#define XGE_HAL_MIN_RMAC_UTIL_PERIOD 0 +#define XGE_HAL_MAX_RMAC_UTIL_PERIOD 15 + + int rmac_bcast_en; +#define XGE_HAL_MIN_RMAC_BCAST_EN 0 +#define XGE_HAL_MAX_RMAC_BCAST_EN 1 + + int rmac_pause_gen_en; +#define XGE_HAL_MIN_RMAC_PAUSE_GEN_EN 0 +#define XGE_HAL_MAX_RMAC_PAUSE_GEN_EN 1 + + int rmac_pause_rcv_en; +#define XGE_HAL_MIN_RMAC_PAUSE_RCV_EN 0 +#define XGE_HAL_MAX_RMAC_PAUSE_RCV_EN 1 + + int rmac_pause_time; +#define XGE_HAL_MIN_RMAC_HIGH_PTIME 16 +#define XGE_HAL_MAX_RMAC_HIGH_PTIME 65535 + + int mc_pause_threshold_q0q3; +#define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q0Q3 0 +#define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q0Q3 254 + + int mc_pause_threshold_q4q7; +#define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q4Q7 0 +#define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q4Q7 254 } xge_hal_mac_config_t; -#ifdef XGEHAL_RNIC - -/* - * struct xge_hal_vp_config_t - Configuration of virtual path - * @vp_id: Virtual Path Id - * @vp_valid: Flag specifies if the configuration is valid - * @bitmap_intr_num: Interrupt Number associated with the bitmap - * @nce_oid_start: The start of the NCE ID range - * @nce_oid_end: The end of the NCE ID range - * @session_oid_start: The start of the Session ID range - * @session_oid_end: The end of the Session ID range - * @srq_oid_start: The start of the HSRQ ID range - * @srq_oid_end: The end of the SRQ ID range - * @cqrq_oid_start: The start of the CQRQ range - * @cqrq_oid_end: The end of the CQRQ range - * @umq_length: Length of up message queue - * @umq_int_ctrl: Interrupt control for up Message queue - * @umq_gen_compl: Generate completion for up message queue - * @dmq_length: Length of down message queue - * @dmq_int_ctrl: Interrupt control for down Message queue - * @dmq_gen_compl: Generate completion for up message queue - * - * This structure is used by the driver to pass the configuration parameters to - * configure Virtual Path. - */ -typedef struct xge_hal_vp_config_t{ - u32 vp_id; - u32 vp_valid; -#define XGE_HAL_VP_CONFIG_INVALID 0 -#define XGE_HAL_VP_CONFIG_VALID 1 - - int bitmap_intr_num; -#define XGE_HAL_BITMAP_INTR_NUM_MIN 0 -#define XGE_HAL_BITMAP_INTR_NUM_MAX 3 - - u32 nce_oid_start; - u32 nce_oid_end; - u32 session_oid_start; - u32 session_oid_end; - u32 srq_oid_start; - u32 srq_oid_end; - u32 cqrq_oid_start; - u32 cqrq_oid_end; - u32 umq_length; - u32 umq_int_ctrl; - u32 umq_gen_compl; - u32 dmq_length; - u32 dmq_int_ctrl; - u32 dmq_gen_compl; -}xge_hal_vp_config_t; - -#endif - /** * struct xge_hal_device_config_t - Device configuration. * @mtu: Current mtu size. @@ -668,9 +603,9 @@ typedef struct xge_hal_vp_config_t{ * @rth_bucket_size: RTH bucket width (in bits). For valid range please see * xge_hal_device_config_t{} in the driver sources. * @rth_spdm_en: Enable Receive Traffic Hashing(RTH) using SPDM(Socket Pair - * Direct Match). + * Direct Match). * @rth_spdm_use_l4: Set to 1, if the L4 ports are used in the calculation of - * hash value in the RTH SPDM based steering. + * hash value in the RTH SPDM based steering. * @rxufca_intr_thres: (TODO) * @rxufca_lo_lim: (TODO) * @rxufca_hi_lim: (TODO) @@ -686,7 +621,7 @@ typedef struct xge_hal_vp_config_t{ * stable in order for the adapter to declare "LINK UP". * The enumerated settings (see Xframe-II UG) are: * 0 ........... instantaneous - * 1 ........... 500 �s + * 1 ........... 500 �s * 2 ........... 1 ms * 3 ........... 64 ms * 4 ........... 256 ms @@ -716,9 +651,9 @@ typedef struct xge_hal_vp_config_t{ * automatic adapter refill operations. * @refill_threshold_low:This field provides a hysteresis lower bound for * automatic adapter refill operations. - * @eol_policy:This field sets the policy for handling the end of list condition.
- * 2'b00 - When EOL is reached,poll until last block wrapper size is no longer 0.
- * 2'b01 - Send UMQ message when EOL is reached.
+ * @eol_policy:This field sets the policy for handling the end of list condition. + * 2'b00 - When EOL is reached,poll until last block wrapper size is no longer 0. + * 2'b01 - Send UMQ message when EOL is reached. * 2'b1x - Poll until the poll_count_max is reached and if still EOL,send UMQ message * @eol_poll_count_max:sets the maximum number of times the queue manager will poll for * a non-zero block wrapper before giving up and sending a UMQ message @@ -746,205 +681,170 @@ typedef struct xge_hal_vp_config_t{ * xge_hal_mac_config_t{}. */ typedef struct xge_hal_device_config_t { - int mtu; -#define XGE_HAL_MIN_INITIAL_MTU XGE_HAL_MIN_MTU -#define XGE_HAL_MAX_INITIAL_MTU XGE_HAL_MAX_MTU - - int isr_polling_cnt; -#define XGE_HAL_MIN_ISR_POLLING_CNT 0 -#define XGE_HAL_MAX_ISR_POLLING_CNT 65536 - - int latency_timer; -#define XGE_HAL_USE_BIOS_DEFAULT_LATENCY -1 -#define XGE_HAL_MIN_LATENCY_TIMER 8 -#define XGE_HAL_MAX_LATENCY_TIMER 255 - - int napi_weight; -#define XGE_HAL_DEF_NAPI_WEIGHT 64 - - int max_splits_trans; -#define XGE_HAL_USE_BIOS_DEFAULT_SPLITS -1 -#define XGE_HAL_ONE_SPLIT_TRANSACTION 0 -#define XGE_HAL_TWO_SPLIT_TRANSACTION 1 -#define XGE_HAL_THREE_SPLIT_TRANSACTION 2 -#define XGE_HAL_FOUR_SPLIT_TRANSACTION 3 -#define XGE_HAL_EIGHT_SPLIT_TRANSACTION 4 -#define XGE_HAL_TWELVE_SPLIT_TRANSACTION 5 -#define XGE_HAL_SIXTEEN_SPLIT_TRANSACTION 6 -#define XGE_HAL_THIRTYTWO_SPLIT_TRANSACTION 7 - - int mmrb_count; -#define XGE_HAL_DEFAULT_BIOS_MMRB_COUNT -1 -#define XGE_HAL_MIN_MMRB_COUNT 0 /* 512b */ -#define XGE_HAL_MAX_MMRB_COUNT 3 /* 4k */ - - int shared_splits; -#define XGE_HAL_MIN_SHARED_SPLITS 0 -#define XGE_HAL_MAX_SHARED_SPLITS 31 - - int stats_refresh_time_sec; -#define XGE_HAL_STATS_REFRESH_DISABLE 0 -#define XGE_HAL_MIN_STATS_REFRESH_TIME 1 -#define XGE_HAL_MAX_STATS_REFRESH_TIME 300 - - int pci_freq_mherz; -#define XGE_HAL_PCI_FREQ_MHERZ_33 33 -#define XGE_HAL_PCI_FREQ_MHERZ_66 66 -#define XGE_HAL_PCI_FREQ_MHERZ_100 100 -#define XGE_HAL_PCI_FREQ_MHERZ_133 133 -#define XGE_HAL_PCI_FREQ_MHERZ_266 266 - - int intr_mode; -#define XGE_HAL_INTR_MODE_IRQLINE 0 -#define XGE_HAL_INTR_MODE_MSI 1 -#define XGE_HAL_INTR_MODE_MSIX 2 - - int sched_timer_us; -#define XGE_HAL_SCHED_TIMER_DISABLED 0 -#define XGE_HAL_SCHED_TIMER_MIN 0 -#define XGE_HAL_SCHED_TIMER_MAX 0xFFFFF - - int sched_timer_one_shot; -#define XGE_HAL_SCHED_TIMER_ON_SHOT_DISABLE 0 -#define XGE_HAL_SCHED_TIMER_ON_SHOT_ENABLE 1 - - xge_hal_ring_config_t ring; - xge_hal_mac_config_t mac; - xge_hal_fifo_config_t fifo; - - int dump_on_serr; -#define XGE_HAL_DUMP_ON_SERR_DISABLE 0 -#define XGE_HAL_DUMP_ON_SERR_ENABLE 1 - - int dump_on_eccerr; -#define XGE_HAL_DUMP_ON_ECCERR_DISABLE 0 -#define XGE_HAL_DUMP_ON_ECCERR_ENABLE 1 - - int dump_on_parityerr; -#define XGE_HAL_DUMP_ON_PARITYERR_DISABLE 0 -#define XGE_HAL_DUMP_ON_PARITYERR_ENABLE 1 - - int rth_en; -#define XGE_HAL_RTH_DISABLE 0 -#define XGE_HAL_RTH_ENABLE 1 - - int rth_bucket_size; -#define XGE_HAL_MIN_RTH_BUCKET_SIZE 1 -#define XGE_HAL_MAX_RTH_BUCKET_SIZE 8 - - int rth_spdm_en; -#define XGE_HAL_RTH_SPDM_DISABLE 0 -#define XGE_HAL_RTH_SPDM_ENABLE 1 - - int rth_spdm_use_l4; -#define XGE_HAL_RTH_SPDM_USE_L4 1 - - int rxufca_intr_thres; -#define XGE_HAL_RXUFCA_INTR_THRES_MIN 1 -#define XGE_HAL_RXUFCA_INTR_THRES_MAX 4096 - - int rxufca_lo_lim; -#define XGE_HAL_RXUFCA_LO_LIM_MIN 1 -#define XGE_HAL_RXUFCA_LO_LIM_MAX 16 - - int rxufca_hi_lim; -#define XGE_HAL_RXUFCA_HI_LIM_MIN 1 -#define XGE_HAL_RXUFCA_HI_LIM_MAX 256 - - int rxufca_lbolt_period; -#define XGE_HAL_RXUFCA_LBOLT_PERIOD_MIN 1 -#define XGE_HAL_RXUFCA_LBOLT_PERIOD_MAX 1024 - - int link_valid_cnt; -#define XGE_HAL_LINK_VALID_CNT_MIN 0 -#define XGE_HAL_LINK_VALID_CNT_MAX 127 - - int link_retry_cnt; -#define XGE_HAL_LINK_RETRY_CNT_MIN 0 -#define XGE_HAL_LINK_RETRY_CNT_MAX 127 - - int link_stability_period; -#define XGE_HAL_DEFAULT_LINK_STABILITY_PERIOD 2 /* 1ms */ -#define XGE_HAL_MIN_LINK_STABILITY_PERIOD 0 /* instantaneous */ -#define XGE_HAL_MAX_LINK_STABILITY_PERIOD 7 /* 2s */ - - int device_poll_millis; -#define XGE_HAL_DEFAULT_DEVICE_POLL_MILLIS 1000 -#define XGE_HAL_MIN_DEVICE_POLL_MILLIS 1 -#define XGE_HAL_MAX_DEVICE_POLL_MILLIS 100000 - - int no_isr_events; -#define XGE_HAL_NO_ISR_EVENTS_MIN 0 -#define XGE_HAL_NO_ISR_EVENTS_MAX 1 - - int lro_sg_size; -#define XGE_HAL_LRO_DEFAULT_SG_SIZE 10 -#define XGE_HAL_LRO_MIN_SG_SIZE 1 -#define XGE_HAL_LRO_MAX_SG_SIZE 64 - - int lro_frm_len; -#define XGE_HAL_LRO_DEFAULT_FRM_LEN 65536 -#define XGE_HAL_LRO_MIN_FRM_LEN 4096 -#define XGE_HAL_LRO_MAX_FRM_LEN 65536 - - int bimodal_interrupts; -#define XGE_HAL_BIMODAL_INTR_MIN -1 -#define XGE_HAL_BIMODAL_INTR_MAX 1 + int mtu; +#define XGE_HAL_MIN_INITIAL_MTU XGE_HAL_MIN_MTU +#define XGE_HAL_MAX_INITIAL_MTU XGE_HAL_MAX_MTU + + int isr_polling_cnt; +#define XGE_HAL_MIN_ISR_POLLING_CNT 0 +#define XGE_HAL_MAX_ISR_POLLING_CNT 65536 + + int latency_timer; +#define XGE_HAL_USE_BIOS_DEFAULT_LATENCY -1 +#define XGE_HAL_MIN_LATENCY_TIMER 8 +#define XGE_HAL_MAX_LATENCY_TIMER 255 + + int napi_weight; +#define XGE_HAL_DEF_NAPI_WEIGHT 64 + + int max_splits_trans; +#define XGE_HAL_USE_BIOS_DEFAULT_SPLITS -1 +#define XGE_HAL_ONE_SPLIT_TRANSACTION 0 +#define XGE_HAL_TWO_SPLIT_TRANSACTION 1 +#define XGE_HAL_THREE_SPLIT_TRANSACTION 2 +#define XGE_HAL_FOUR_SPLIT_TRANSACTION 3 +#define XGE_HAL_EIGHT_SPLIT_TRANSACTION 4 +#define XGE_HAL_TWELVE_SPLIT_TRANSACTION 5 +#define XGE_HAL_SIXTEEN_SPLIT_TRANSACTION 6 +#define XGE_HAL_THIRTYTWO_SPLIT_TRANSACTION 7 + + int mmrb_count; +#define XGE_HAL_DEFAULT_BIOS_MMRB_COUNT -1 +#define XGE_HAL_MIN_MMRB_COUNT 0 /* 512b */ +#define XGE_HAL_MAX_MMRB_COUNT 3 /* 4k */ + + int shared_splits; +#define XGE_HAL_MIN_SHARED_SPLITS 0 +#define XGE_HAL_MAX_SHARED_SPLITS 31 + + int stats_refresh_time_sec; +#define XGE_HAL_STATS_REFRESH_DISABLE 0 +#define XGE_HAL_MIN_STATS_REFRESH_TIME 1 +#define XGE_HAL_MAX_STATS_REFRESH_TIME 300 + + int pci_freq_mherz; +#define XGE_HAL_PCI_FREQ_MHERZ_33 33 +#define XGE_HAL_PCI_FREQ_MHERZ_66 66 +#define XGE_HAL_PCI_FREQ_MHERZ_100 100 +#define XGE_HAL_PCI_FREQ_MHERZ_133 133 +#define XGE_HAL_PCI_FREQ_MHERZ_266 266 + + int intr_mode; +#define XGE_HAL_INTR_MODE_IRQLINE 0 +#define XGE_HAL_INTR_MODE_MSI 1 +#define XGE_HAL_INTR_MODE_MSIX 2 + + int sched_timer_us; +#define XGE_HAL_SCHED_TIMER_DISABLED 0 +#define XGE_HAL_SCHED_TIMER_MIN 0 +#define XGE_HAL_SCHED_TIMER_MAX 0xFFFFF + + int sched_timer_one_shot; +#define XGE_HAL_SCHED_TIMER_ON_SHOT_DISABLE 0 +#define XGE_HAL_SCHED_TIMER_ON_SHOT_ENABLE 1 + + xge_hal_ring_config_t ring; + xge_hal_mac_config_t mac; + xge_hal_fifo_config_t fifo; + + int dump_on_serr; +#define XGE_HAL_DUMP_ON_SERR_DISABLE 0 +#define XGE_HAL_DUMP_ON_SERR_ENABLE 1 + + int dump_on_eccerr; +#define XGE_HAL_DUMP_ON_ECCERR_DISABLE 0 +#define XGE_HAL_DUMP_ON_ECCERR_ENABLE 1 + + int dump_on_parityerr; +#define XGE_HAL_DUMP_ON_PARITYERR_DISABLE 0 +#define XGE_HAL_DUMP_ON_PARITYERR_ENABLE 1 + + int rth_en; +#define XGE_HAL_RTH_DISABLE 0 +#define XGE_HAL_RTH_ENABLE 1 + + int rth_bucket_size; +#define XGE_HAL_MIN_RTH_BUCKET_SIZE 1 +#define XGE_HAL_MAX_RTH_BUCKET_SIZE 8 + + int rth_spdm_en; +#define XGE_HAL_RTH_SPDM_DISABLE 0 +#define XGE_HAL_RTH_SPDM_ENABLE 1 + + int rth_spdm_use_l4; +#define XGE_HAL_RTH_SPDM_USE_L4 1 + + int rxufca_intr_thres; +#define XGE_HAL_RXUFCA_INTR_THRES_MIN 1 +#define XGE_HAL_RXUFCA_INTR_THRES_MAX 4096 + + int rxufca_lo_lim; +#define XGE_HAL_RXUFCA_LO_LIM_MIN 1 +#define XGE_HAL_RXUFCA_LO_LIM_MAX 16 + + int rxufca_hi_lim; +#define XGE_HAL_RXUFCA_HI_LIM_MIN 1 +#define XGE_HAL_RXUFCA_HI_LIM_MAX 256 + + int rxufca_lbolt_period; +#define XGE_HAL_RXUFCA_LBOLT_PERIOD_MIN 1 +#define XGE_HAL_RXUFCA_LBOLT_PERIOD_MAX 1024 + + int link_valid_cnt; +#define XGE_HAL_LINK_VALID_CNT_MIN 0 +#define XGE_HAL_LINK_VALID_CNT_MAX 127 + + int link_retry_cnt; +#define XGE_HAL_LINK_RETRY_CNT_MIN 0 +#define XGE_HAL_LINK_RETRY_CNT_MAX 127 + + int link_stability_period; +#define XGE_HAL_DEFAULT_LINK_STABILITY_PERIOD 2 /* 1ms */ +#define XGE_HAL_MIN_LINK_STABILITY_PERIOD 0 /* instantaneous */ +#define XGE_HAL_MAX_LINK_STABILITY_PERIOD 7 /* 2s */ + + int device_poll_millis; +#define XGE_HAL_DEFAULT_DEVICE_POLL_MILLIS 1000 +#define XGE_HAL_MIN_DEVICE_POLL_MILLIS 1 +#define XGE_HAL_MAX_DEVICE_POLL_MILLIS 100000 + + int no_isr_events; +#define XGE_HAL_NO_ISR_EVENTS_MIN 0 +#define XGE_HAL_NO_ISR_EVENTS_MAX 1 + + int lro_sg_size; +#define XGE_HAL_LRO_DEFAULT_SG_SIZE 10 +#define XGE_HAL_LRO_MIN_SG_SIZE 1 +#define XGE_HAL_LRO_MAX_SG_SIZE 64 + + int lro_frm_len; +#define XGE_HAL_LRO_DEFAULT_FRM_LEN 65536 +#define XGE_HAL_LRO_MIN_FRM_LEN 4096 +#define XGE_HAL_LRO_MAX_FRM_LEN 65536 + + int bimodal_interrupts; +#define XGE_HAL_BIMODAL_INTR_MIN -1 +#define XGE_HAL_BIMODAL_INTR_MAX 1 + + int bimodal_timer_lo_us; +#define XGE_HAL_BIMODAL_TIMER_LO_US_MIN 1 +#define XGE_HAL_BIMODAL_TIMER_LO_US_MAX 127 + + int bimodal_timer_hi_us; +#define XGE_HAL_BIMODAL_TIMER_HI_US_MIN 128 +#define XGE_HAL_BIMODAL_TIMER_HI_US_MAX 65535 - int bimodal_timer_lo_us; -#define XGE_HAL_BIMODAL_TIMER_LO_US_MIN 1 -#define XGE_HAL_BIMODAL_TIMER_LO_US_MAX 127 + int rts_mac_en; +#define XGE_HAL_RTS_MAC_DISABLE 0 +#define XGE_HAL_RTS_MAC_ENABLE 1 - int bimodal_timer_hi_us; -#define XGE_HAL_BIMODAL_TIMER_HI_US_MIN 128 -#define XGE_HAL_BIMODAL_TIMER_HI_US_MAX 65535 + int rts_qos_en; +#define XGE_HAL_RTS_QOS_DISABLE 0 +#define XGE_HAL_RTS_QOS_ENABLE 1 - int rts_mac_en; -#define XGE_HAL_RTS_MAC_DISABLE 0 -#define XGE_HAL_RTS_MAC_ENABLE 1 - - int rts_qos_en; -#define XGE_HAL_RTS_QOS_DISABLE 0 -#define XGE_HAL_RTS_QOS_ENABLE 1 - - int rts_port_en; -#define XGE_HAL_RTS_PORT_DISABLE 0 -#define XGE_HAL_RTS_PORT_ENABLE 1 - -#ifdef XGEHAL_RNIC - - xge_hal_vp_config_t vp_config[XGE_HAL_MAX_VIRTUAL_PATHS]; - - int max_cqe_groups; -#define XGE_HAL_MAX_CQE_GROUPS_MIN 1 -#define XGE_HAL_MAX_CQE_GROUPS_MAX 16 - - int max_num_wqe_od_groups; -#define XGE_HAL_MAX_NUM_OD_GROUPS_MIN 1 -#define XGE_HAL_MAX_NUM_OD_GROUPS_MAX 16 - - int no_wqe_threshold; -#define XGE_HAL_NO_WQE_THRESHOLD_MIN 1 -#define XGE_HAL_NO_WQE_THRESHOLD_MAX 16 - - int refill_threshold_high; -#define XGE_HAL_REFILL_THRESHOLD_HIGH_MIN 1 -#define XGE_HAL_REFILL_THRESHOLD_HIGH_MAX 16 - - int refill_threshold_low; -#define XGE_HAL_REFILL_THRESHOLD_LOW_MIN 1 -#define XGE_HAL_REFILL_THRESHOLD_LOW_MAX 16 - - int ack_blk_limit; -#define XGE_HAL_ACK_BLOCK_LIMIT_MIN 1 -#define XGE_HAL_ACK_BLOCK_LIMIT_MAX 16 - - int poll_or_doorbell; -#define XGE_HAL_POLL_OR_DOORBELL_POLL 1 -#define XGE_HAL_POLL_OR_DOORBELL_DOORBELL 0 - - -#endif + int rts_port_en; +#define XGE_HAL_RTS_PORT_DISABLE 0 +#define XGE_HAL_RTS_PORT_ENABLE 1 } xge_hal_device_config_t; @@ -971,23 +871,23 @@ typedef struct xge_hal_device_config_t { * See also: xge_hal_device_poll() */ typedef struct xge_hal_driver_config_t { - int queue_size_initial; -#define XGE_HAL_MIN_QUEUE_SIZE_INITIAL 1 -#define XGE_HAL_MAX_QUEUE_SIZE_INITIAL 16 + int queue_size_initial; +#define XGE_HAL_MIN_QUEUE_SIZE_INITIAL 1 +#define XGE_HAL_MAX_QUEUE_SIZE_INITIAL 16 - int queue_size_max; -#define XGE_HAL_MIN_QUEUE_SIZE_MAX 1 -#define XGE_HAL_MAX_QUEUE_SIZE_MAX 16 + int queue_size_max; +#define XGE_HAL_MIN_QUEUE_SIZE_MAX 1 +#define XGE_HAL_MAX_QUEUE_SIZE_MAX 16 #ifdef XGE_TRACE_INTO_CIRCULAR_ARR - int tracebuf_size; -#define XGE_HAL_MIN_CIRCULAR_ARR 4096 -#define XGE_HAL_MAX_CIRCULAR_ARR 1048576 -#define XGE_HAL_DEF_CIRCULAR_ARR XGE_OS_HOST_PAGE_SIZE - - int tracebuf_timestamp_en; -#define XGE_HAL_MIN_TIMESTAMP_EN 0 -#define XGE_HAL_MAX_TIMESTAMP_EN 1 + int tracebuf_size; +#define XGE_HAL_MIN_CIRCULAR_ARR 4096 +#define XGE_HAL_MAX_CIRCULAR_ARR 1048576 +#define XGE_HAL_DEF_CIRCULAR_ARR XGE_OS_HOST_PAGE_SIZE + + int tracebuf_timestamp_en; +#define XGE_HAL_MIN_TIMESTAMP_EN 0 +#define XGE_HAL_MAX_TIMESTAMP_EN 1 #endif } xge_hal_driver_config_t; diff --git a/sys/dev/nxge/include/xgehal-device.h b/sys/dev/nxge/include/xgehal-device.h index 22bc792..31d99b4 100644 --- a/sys/dev/nxge/include/xgehal-device.h +++ b/sys/dev/nxge/include/xgehal-device.h @@ -26,14 +26,6 @@ * $FreeBSD$ */ -/* - * FileName : xgehal-device.h - * - * Description: HAL device object functionality - * - * Created: 14 May 2004 - */ - #ifndef XGE_HAL_DEVICE_H #define XGE_HAL_DEVICE_H @@ -45,18 +37,6 @@ #include <dev/nxge/include/xgehal-channel.h> #include <dev/nxge/include/xgehal-stats.h> #include <dev/nxge/include/xgehal-ring.h> -#ifdef XGEHAL_RNIC -#include "xgehal-common-regs.h" -#include "xgehal-pcicfg-mgmt-regs.h" -#include "xgehal-mrpcim-regs.h" -#include "xgehal-srpcim-regs.h" -#include "xgehal-vpath-regs.h" -#include "xgehal-bitmap.h" -#include "xgehal-virtualpath.h" -#include "xgehal-lbwrapper.h" -#include "xgehal-blockpool.h" -#include "xgehal-regpool.h" -#endif __EXTERN_BEGIN_DECLS @@ -65,18 +45,18 @@ __EXTERN_BEGIN_DECLS #define XGE_HAL_CARD_HERC_VPD_ADDR 0x80 #define XGE_HAL_VPD_READ_COMPLETE 0x80 #define XGE_HAL_VPD_BUFFER_SIZE 128 -#define XGE_HAL_DEVICE_XMSI_WAIT_MAX_MILLIS 500 -#define XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS 500 -#define XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS 500 -#define XGE_HAL_DEVICE_FAULT_WAIT_MAX_MILLIS 50 -#define XGE_HAL_DEVICE_RESET_WAIT_MAX_MILLIS 250 -#define XGE_HAL_DEVICE_SPDM_READY_WAIT_MAX_MILLIS 250 /* TODO */ - -#define XGE_HAL_MAGIC 0x12345678 -#define XGE_HAL_DEAD 0xDEADDEAD +#define XGE_HAL_DEVICE_XMSI_WAIT_MAX_MILLIS 500 +#define XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS 500 +#define XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS 500 +#define XGE_HAL_DEVICE_FAULT_WAIT_MAX_MILLIS 50 +#define XGE_HAL_DEVICE_RESET_WAIT_MAX_MILLIS 250 +#define XGE_HAL_DEVICE_SPDM_READY_WAIT_MAX_MILLIS 250 /* TODO */ + +#define XGE_HAL_MAGIC 0x12345678 +#define XGE_HAL_DEAD 0xDEADDEAD #define XGE_HAL_DUMP_BUF_SIZE 0x4000 -#define XGE_HAL_LRO_MAX_BUCKETS 32 +#define XGE_HAL_LRO_MAX_BUCKETS 32 /** * enum xge_hal_card_e - Xframe adapter type. @@ -92,10 +72,10 @@ __EXTERN_BEGIN_DECLS * See also: xge_hal_device_check_id(). */ typedef enum xge_hal_card_e { - XGE_HAL_CARD_UNKNOWN = 0, - XGE_HAL_CARD_XENA = 1, - XGE_HAL_CARD_HERC = 2, - XGE_HAL_CARD_TITAN = 3, + XGE_HAL_CARD_UNKNOWN = 0, + XGE_HAL_CARD_XENA = 1, + XGE_HAL_CARD_HERC = 2, + XGE_HAL_CARD_TITAN = 3, } xge_hal_card_e; /** @@ -113,15 +93,15 @@ typedef enum xge_hal_card_e { * mapped memories. Also, includes a pointer to OS-specific PCI device object. */ typedef struct xge_hal_device_attr_t { - pci_reg_h regh0; - pci_reg_h regh1; - pci_reg_h regh2; - char *bar0; - char *bar1; - char *bar2; - pci_irq_h irqh; - pci_cfg_h cfgh; - pci_dev_h pdev; + pci_reg_h regh0; + pci_reg_h regh1; + pci_reg_h regh2; + char *bar0; + char *bar1; + char *bar2; + pci_irq_h irqh; + pci_cfg_h cfgh; + pci_dev_h pdev; } xge_hal_device_attr_t; /** @@ -140,96 +120,96 @@ typedef enum xge_hal_device_link_state_e { /** * enum xge_hal_pci_mode_e - PIC bus speed and mode specific enumeration. - * @XGE_HAL_PCI_33MHZ_MODE: 33 MHZ pci mode. - * @XGE_HAL_PCI_66MHZ_MODE: 66 MHZ pci mode. - * @XGE_HAL_PCIX_M1_66MHZ_MODE: PCIX M1 66MHZ mode. - * @XGE_HAL_PCIX_M1_100MHZ_MODE: PCIX M1 100MHZ mode. - * @XGE_HAL_PCIX_M1_133MHZ_MODE: PCIX M1 133MHZ mode. - * @XGE_HAL_PCIX_M2_66MHZ_MODE: PCIX M2 66MHZ mode. - * @XGE_HAL_PCIX_M2_100MHZ_MODE: PCIX M2 100MHZ mode. - * @XGE_HAL_PCIX_M2_133MHZ_MODE: PCIX M3 133MHZ mode. - * @XGE_HAL_PCIX_M1_RESERVED: PCIX M1 reserved mode. - * @XGE_HAL_PCIX_M1_66MHZ_NS: PCIX M1 66MHZ mode not supported. - * @XGE_HAL_PCIX_M1_100MHZ_NS: PCIX M1 100MHZ mode not supported. - * @XGE_HAL_PCIX_M1_133MHZ_NS: PCIX M1 133MHZ not supported. - * @XGE_HAL_PCIX_M2_RESERVED: PCIX M2 reserved. - * @XGE_HAL_PCIX_533_RESERVED: PCIX 533 reserved. - * @XGE_HAL_PCI_BASIC_MODE: PCI basic mode, XENA specific value. - * @XGE_HAL_PCIX_BASIC_MODE: PCIX basic mode, XENA specific value. - * @XGE_HAL_PCI_INVALID_MODE: Invalid PCI or PCIX mode. + * @XGE_HAL_PCI_33MHZ_MODE: 33 MHZ pci mode. + * @XGE_HAL_PCI_66MHZ_MODE: 66 MHZ pci mode. + * @XGE_HAL_PCIX_M1_66MHZ_MODE: PCIX M1 66MHZ mode. + * @XGE_HAL_PCIX_M1_100MHZ_MODE: PCIX M1 100MHZ mode. + * @XGE_HAL_PCIX_M1_133MHZ_MODE: PCIX M1 133MHZ mode. + * @XGE_HAL_PCIX_M2_66MHZ_MODE: PCIX M2 66MHZ mode. + * @XGE_HAL_PCIX_M2_100MHZ_MODE: PCIX M2 100MHZ mode. + * @XGE_HAL_PCIX_M2_133MHZ_MODE: PCIX M3 133MHZ mode. + * @XGE_HAL_PCIX_M1_RESERVED: PCIX M1 reserved mode. + * @XGE_HAL_PCIX_M1_66MHZ_NS: PCIX M1 66MHZ mode not supported. + * @XGE_HAL_PCIX_M1_100MHZ_NS: PCIX M1 100MHZ mode not supported. + * @XGE_HAL_PCIX_M1_133MHZ_NS: PCIX M1 133MHZ not supported. + * @XGE_HAL_PCIX_M2_RESERVED: PCIX M2 reserved. + * @XGE_HAL_PCIX_533_RESERVED: PCIX 533 reserved. + * @XGE_HAL_PCI_BASIC_MODE: PCI basic mode, XENA specific value. + * @XGE_HAL_PCIX_BASIC_MODE: PCIX basic mode, XENA specific value. + * @XGE_HAL_PCI_INVALID_MODE: Invalid PCI or PCIX mode. * */ typedef enum xge_hal_pci_mode_e { - XGE_HAL_PCI_33MHZ_MODE = 0x0, - XGE_HAL_PCI_66MHZ_MODE = 0x1, - XGE_HAL_PCIX_M1_66MHZ_MODE = 0x2, - XGE_HAL_PCIX_M1_100MHZ_MODE = 0x3, - XGE_HAL_PCIX_M1_133MHZ_MODE = 0x4, - XGE_HAL_PCIX_M2_66MHZ_MODE = 0x5, - XGE_HAL_PCIX_M2_100MHZ_MODE = 0x6, - XGE_HAL_PCIX_M2_133MHZ_MODE = 0x7, - XGE_HAL_PCIX_M1_RESERVED = 0x8, - XGE_HAL_PCIX_M1_66MHZ_NS = 0xA, - XGE_HAL_PCIX_M1_100MHZ_NS = 0xB, - XGE_HAL_PCIX_M1_133MHZ_NS = 0xC, - XGE_HAL_PCIX_M2_RESERVED = 0xD, - XGE_HAL_PCIX_533_RESERVED = 0xE, - XGE_HAL_PCI_BASIC_MODE = 0x10, - XGE_HAL_PCIX_BASIC_MODE = 0x11, - XGE_HAL_PCI_INVALID_MODE = 0x12, + XGE_HAL_PCI_33MHZ_MODE = 0x0, + XGE_HAL_PCI_66MHZ_MODE = 0x1, + XGE_HAL_PCIX_M1_66MHZ_MODE = 0x2, + XGE_HAL_PCIX_M1_100MHZ_MODE = 0x3, + XGE_HAL_PCIX_M1_133MHZ_MODE = 0x4, + XGE_HAL_PCIX_M2_66MHZ_MODE = 0x5, + XGE_HAL_PCIX_M2_100MHZ_MODE = 0x6, + XGE_HAL_PCIX_M2_133MHZ_MODE = 0x7, + XGE_HAL_PCIX_M1_RESERVED = 0x8, + XGE_HAL_PCIX_M1_66MHZ_NS = 0xA, + XGE_HAL_PCIX_M1_100MHZ_NS = 0xB, + XGE_HAL_PCIX_M1_133MHZ_NS = 0xC, + XGE_HAL_PCIX_M2_RESERVED = 0xD, + XGE_HAL_PCIX_533_RESERVED = 0xE, + XGE_HAL_PCI_BASIC_MODE = 0x10, + XGE_HAL_PCIX_BASIC_MODE = 0x11, + XGE_HAL_PCI_INVALID_MODE = 0x12, } xge_hal_pci_mode_e; /** * enum xge_hal_pci_bus_frequency_e - PCI bus frequency enumeration. - * @XGE_HAL_PCI_BUS_FREQUENCY_33MHZ: PCI bus frequency 33MHZ - * @XGE_HAL_PCI_BUS_FREQUENCY_66MHZ: PCI bus frequency 66MHZ - * @XGE_HAL_PCI_BUS_FREQUENCY_100MHZ: PCI bus frequency 100MHZ - * @XGE_HAL_PCI_BUS_FREQUENCY_133MHZ: PCI bus frequency 133MHZ - * @XGE_HAL_PCI_BUS_FREQUENCY_200MHZ: PCI bus frequency 200MHZ - * @XGE_HAL_PCI_BUS_FREQUENCY_250MHZ: PCI bus frequency 250MHZ - * @XGE_HAL_PCI_BUS_FREQUENCY_266MHZ: PCI bus frequency 266MHZ - * @XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN: Unrecognized PCI bus frequency value. + * @XGE_HAL_PCI_BUS_FREQUENCY_33MHZ: PCI bus frequency 33MHZ + * @XGE_HAL_PCI_BUS_FREQUENCY_66MHZ: PCI bus frequency 66MHZ + * @XGE_HAL_PCI_BUS_FREQUENCY_100MHZ: PCI bus frequency 100MHZ + * @XGE_HAL_PCI_BUS_FREQUENCY_133MHZ: PCI bus frequency 133MHZ + * @XGE_HAL_PCI_BUS_FREQUENCY_200MHZ: PCI bus frequency 200MHZ + * @XGE_HAL_PCI_BUS_FREQUENCY_250MHZ: PCI bus frequency 250MHZ + * @XGE_HAL_PCI_BUS_FREQUENCY_266MHZ: PCI bus frequency 266MHZ + * @XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN: Unrecognized PCI bus frequency value. * */ typedef enum xge_hal_pci_bus_frequency_e { - XGE_HAL_PCI_BUS_FREQUENCY_33MHZ = 33, - XGE_HAL_PCI_BUS_FREQUENCY_66MHZ = 66, - XGE_HAL_PCI_BUS_FREQUENCY_100MHZ = 100, - XGE_HAL_PCI_BUS_FREQUENCY_133MHZ = 133, - XGE_HAL_PCI_BUS_FREQUENCY_200MHZ = 200, - XGE_HAL_PCI_BUS_FREQUENCY_250MHZ = 250, - XGE_HAL_PCI_BUS_FREQUENCY_266MHZ = 266, - XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN = 0 + XGE_HAL_PCI_BUS_FREQUENCY_33MHZ = 33, + XGE_HAL_PCI_BUS_FREQUENCY_66MHZ = 66, + XGE_HAL_PCI_BUS_FREQUENCY_100MHZ = 100, + XGE_HAL_PCI_BUS_FREQUENCY_133MHZ = 133, + XGE_HAL_PCI_BUS_FREQUENCY_200MHZ = 200, + XGE_HAL_PCI_BUS_FREQUENCY_250MHZ = 250, + XGE_HAL_PCI_BUS_FREQUENCY_266MHZ = 266, + XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN = 0 } xge_hal_pci_bus_frequency_e; /** * enum xge_hal_pci_bus_width_e - PCI bus width enumeration. - * @XGE_HAL_PCI_BUS_WIDTH_64BIT: 64 bit bus width. - * @XGE_HAL_PCI_BUS_WIDTH_32BIT: 32 bit bus width. + * @XGE_HAL_PCI_BUS_WIDTH_64BIT: 64 bit bus width. + * @XGE_HAL_PCI_BUS_WIDTH_32BIT: 32 bit bus width. * @XGE_HAL_PCI_BUS_WIDTH_UNKNOWN: unknown bus width. * */ typedef enum xge_hal_pci_bus_width_e { - XGE_HAL_PCI_BUS_WIDTH_64BIT = 0, - XGE_HAL_PCI_BUS_WIDTH_32BIT = 1, - XGE_HAL_PCI_BUS_WIDTH_UNKNOWN = 2, + XGE_HAL_PCI_BUS_WIDTH_64BIT = 0, + XGE_HAL_PCI_BUS_WIDTH_32BIT = 1, + XGE_HAL_PCI_BUS_WIDTH_UNKNOWN = 2, } xge_hal_pci_bus_width_e; #if defined (XGE_HAL_CONFIG_LRO) -#define IP_TOTAL_LENGTH_OFFSET 2 -#define IP_FAST_PATH_HDR_MASK 0x45 -#define TCP_FAST_PATH_HDR_MASK1 0x50 -#define TCP_FAST_PATH_HDR_MASK2 0x10 -#define TCP_FAST_PATH_HDR_MASK3 0x18 -#define IP_SOURCE_ADDRESS_OFFSET 12 -#define IP_DESTINATION_ADDRESS_OFFSET 16 -#define TCP_DESTINATION_PORT_OFFSET 2 -#define TCP_SOURCE_PORT_OFFSET 0 -#define TCP_DATA_OFFSET_OFFSET 12 -#define TCP_WINDOW_OFFSET 14 -#define TCP_SEQUENCE_NUMBER_OFFSET 4 -#define TCP_ACKNOWLEDGEMENT_NUMBER_OFFSET 8 +#define IP_TOTAL_LENGTH_OFFSET 2 +#define IP_FAST_PATH_HDR_MASK 0x45 +#define TCP_FAST_PATH_HDR_MASK1 0x50 +#define TCP_FAST_PATH_HDR_MASK2 0x10 +#define TCP_FAST_PATH_HDR_MASK3 0x18 +#define IP_SOURCE_ADDRESS_OFFSET 12 +#define IP_DESTINATION_ADDRESS_OFFSET 16 +#define TCP_DESTINATION_PORT_OFFSET 2 +#define TCP_SOURCE_PORT_OFFSET 0 +#define TCP_DATA_OFFSET_OFFSET 12 +#define TCP_WINDOW_OFFSET 14 +#define TCP_SEQUENCE_NUMBER_OFFSET 4 +#define TCP_ACKNOWLEDGEMENT_NUMBER_OFFSET 8 typedef struct tcplro { u16 source; @@ -263,43 +243,43 @@ typedef struct iplro { typedef struct lro { /* non-linear: contains scatter-gather list of xframe-mapped received buffers */ - OS_NETSTACK_BUF os_buf; - OS_NETSTACK_BUF os_buf_end; + OS_NETSTACK_BUF os_buf; + OS_NETSTACK_BUF os_buf_end; /* link layer header of the first frame; remains intack throughout the processing */ - u8 *ll_hdr; + u8 *ll_hdr; /* IP header - gets _collapsed_ */ - iplro_t *ip_hdr; + iplro_t *ip_hdr; /* transport header - gets _collapsed_ */ - tcplro_t *tcp_hdr; + tcplro_t *tcp_hdr; /* Next tcp sequence number */ - u32 tcp_next_seq_num; + u32 tcp_next_seq_num; /* Current tcp seq & ack */ - u32 tcp_seq_num; - u32 tcp_ack_num; + u32 tcp_seq_num; + u32 tcp_ack_num; /* total number of accumulated (so far) frames */ - int sg_num; + int sg_num; /* total data length */ - int total_length; + int total_length; /* receive side hash value, available from Hercules */ - u32 rth_value; + u32 rth_value; /* In use */ - u8 in_use; + u8 in_use; /* Total length of the fragments clubbed with the inital frame */ - u32 frags_len; + u32 frags_len; /* LRO frame contains time stamp, if (ts_off != -1) */ - int ts_off; - + int ts_off; + } lro_t; #endif @@ -323,9 +303,9 @@ typedef struct xge_hal_spdm_entry_t { #if defined(XGE_HAL_CONFIG_LRO) typedef struct { - lro_t lro_pool[XGE_HAL_LRO_MAX_BUCKETS]; - int lro_next_idx; - lro_t *lro_recent; + lro_t lro_pool[XGE_HAL_LRO_MAX_BUCKETS]; + int lro_next_idx; + lro_t *lro_recent; } xge_hal_lro_desc_t; #endif /* @@ -334,8 +314,8 @@ typedef struct { * Represents vpd capabilty structure */ typedef struct xge_hal_vpd_data_t { - u8 product_name[XGE_HAL_VPD_LENGTH]; - u8 serial_num[XGE_HAL_VPD_LENGTH]; + u8 product_name[XGE_HAL_VPD_LENGTH]; + u8 serial_num[XGE_HAL_VPD_LENGTH]; } xge_hal_vpd_data_t; /* @@ -344,82 +324,75 @@ typedef struct xge_hal_vpd_data_t { * HAL device object. Represents Xframe. */ typedef struct { - unsigned int magic; - pci_reg_h regh0; - pci_reg_h regh1; - pci_reg_h regh2; - char *bar0; - char *isrbar0; - char *bar1; - char *bar2; - pci_irq_h irqh; - pci_cfg_h cfgh; - pci_dev_h pdev; - xge_hal_pci_config_t pci_config_space; - xge_hal_pci_config_t pci_config_space_bios; - xge_hal_device_config_t config; - xge_list_t free_channels; - xge_list_t fifo_channels; - xge_list_t ring_channels; -#ifdef XGEHAL_RNIC - __hal_bitmap_entry_t bitmap_table[XGE_HAL_MAX_BITMAP_BITS]; - __hal_virtualpath_t virtual_paths[XGE_HAL_MAX_VIRTUAL_PATHS]; - __hal_blockpool_t block_pool; - __hal_regpool_t reg_pool; -#endif - volatile int is_initialized; - volatile int terminating; - xge_hal_stats_t stats; - macaddr_t macaddr[1]; - xge_queue_h queueh; - volatile int mcast_refcnt; - int is_promisc; - volatile xge_hal_device_link_state_e link_state; - void *upper_layer_info; - xge_hal_device_attr_t orig_attr; - u16 device_id; - u8 revision; - int msi_enabled; - int hw_is_initialized; - u64 inject_serr; - u64 inject_ecc; - u8 inject_bad_tcode; - int inject_bad_tcode_for_chan_type; - int reset_needed_after_close; - int tti_enabled; - xge_hal_tti_config_t bimodal_tti[XGE_HAL_MAX_RING_NUM]; - int bimodal_timer_val_us; - int bimodal_urange_a_en; - int bimodal_intr_cnt; - char *spdm_mem_base; - u16 spdm_max_entries; - xge_hal_spdm_entry_t **spdm_table; - spinlock_t spdm_lock; - u32 msi_mask; + unsigned int magic; + pci_reg_h regh0; + pci_reg_h regh1; + pci_reg_h regh2; + char *bar0; + char *isrbar0; + char *bar1; + char *bar2; + pci_irq_h irqh; + pci_cfg_h cfgh; + pci_dev_h pdev; + xge_hal_pci_config_t pci_config_space; + xge_hal_pci_config_t pci_config_space_bios; + xge_hal_device_config_t config; + xge_list_t free_channels; + xge_list_t fifo_channels; + xge_list_t ring_channels; + volatile int is_initialized; + volatile int terminating; + xge_hal_stats_t stats; + macaddr_t macaddr[1]; + xge_queue_h queueh; + volatile int mcast_refcnt; + int is_promisc; + volatile xge_hal_device_link_state_e link_state; + void *upper_layer_info; + xge_hal_device_attr_t orig_attr; + u16 device_id; + u8 revision; + int msi_enabled; + int hw_is_initialized; + u64 inject_serr; + u64 inject_ecc; + u8 inject_bad_tcode; + int inject_bad_tcode_for_chan_type; + int reset_needed_after_close; + int tti_enabled; + xge_hal_tti_config_t bimodal_tti[XGE_HAL_MAX_RING_NUM]; + int bimodal_timer_val_us; + int bimodal_urange_a_en; + int bimodal_intr_cnt; + char *spdm_mem_base; + u16 spdm_max_entries; + xge_hal_spdm_entry_t **spdm_table; + spinlock_t spdm_lock; #if defined(XGE_HAL_CONFIG_LRO) - xge_hal_lro_desc_t lro_desc[XGE_HAL_MAX_RING_NUM]; + xge_hal_lro_desc_t lro_desc[XGE_HAL_MAX_RING_NUM]; #endif - spinlock_t xena_post_lock; + spinlock_t xena_post_lock; /* bimodal workload stats */ - int irq_workload_rxd[XGE_HAL_MAX_RING_NUM]; - int irq_workload_rxcnt[XGE_HAL_MAX_RING_NUM]; - int irq_workload_rxlen[XGE_HAL_MAX_RING_NUM]; - int irq_workload_txd[XGE_HAL_MAX_FIFO_NUM]; - int irq_workload_txcnt[XGE_HAL_MAX_FIFO_NUM]; - int irq_workload_txlen[XGE_HAL_MAX_FIFO_NUM]; - - int mtu_first_time_set; - u64 rxufca_lbolt; - u64 rxufca_lbolt_time; - u64 rxufca_intr_thres; + int irq_workload_rxd[XGE_HAL_MAX_RING_NUM]; + int irq_workload_rxcnt[XGE_HAL_MAX_RING_NUM]; + int irq_workload_rxlen[XGE_HAL_MAX_RING_NUM]; + int irq_workload_txd[XGE_HAL_MAX_FIFO_NUM]; + int irq_workload_txcnt[XGE_HAL_MAX_FIFO_NUM]; + int irq_workload_txlen[XGE_HAL_MAX_FIFO_NUM]; + + int mtu_first_time_set; + u64 rxufca_lbolt; + u64 rxufca_lbolt_time; + u64 rxufca_intr_thres; char* dump_buf; - xge_hal_pci_mode_e pci_mode; + xge_hal_pci_mode_e pci_mode; xge_hal_pci_bus_frequency_e bus_frequency; - xge_hal_pci_bus_width_e bus_width; + xge_hal_pci_bus_width_e bus_width; xge_hal_vpd_data_t vpd_data; - volatile int in_poll; - u64 msix_vector_table[XGE_HAL_MAX_MSIX_MESSAGES_WITH_ADDR]; + volatile int in_poll; + u64 msix_vector_table[XGE_HAL_MAX_MSIX_MESSAGES_WITH_ADDR]; } xge_hal_device_t; @@ -445,13 +418,13 @@ __hal_device_handle_pic(xge_hal_device_t *hldev, u64 reason); xge_hal_status_e __hal_read_spdm_entry_line(xge_hal_device_t *hldev, u8 spdm_line, - u16 spdm_entry, u64 *spdm_line_val); + u16 spdm_entry, u64 *spdm_line_val); void __hal_pio_mem_write32_upper(pci_dev_h pdev, pci_reg_h regh, u32 val, - void *addr); + void *addr); void __hal_pio_mem_write32_lower(pci_dev_h pdev, pci_reg_h regh, u32 val, - void *addr); + void *addr); void __hal_device_get_vpd_data(xge_hal_device_t *hldev); xge_hal_status_e @@ -483,7 +456,7 @@ __hal_device_handle_mc(xge_hal_device_t *hldev, u64 reason); xge_hal_status_e __hal_device_register_poll(xge_hal_device_t *hldev, u64 *reg, int op, u64 mask, - int max_millis); + int max_millis); xge_hal_status_e __hal_device_rts_mac_configure(xge_hal_device_t *hldev); @@ -501,20 +474,20 @@ __hal_device_msi_intr_endis(xge_hal_device_t *hldev, int flag); void __hal_device_msix_intr_endis(xge_hal_device_t *hldev, - xge_hal_channel_t *channel, int flag); + xge_hal_channel_t *channel, int flag); /* =========================== PUBLIC API ================================= */ unsigned int __hal_fix_time_ival_herc(xge_hal_device_t *hldev, - unsigned int time_ival); + unsigned int time_ival); xge_hal_status_e xge_hal_rts_rth_itable_set(xge_hal_device_t *hldev, u8 *itable, - u32 itable_size); + u32 itable_size); void xge_hal_rts_rth_set(xge_hal_device_t *hldev, u8 def_q, u64 hash_type, - u16 bucket_size); + u16 bucket_size); void xge_hal_rts_rth_init(xge_hal_device_t *hldev); @@ -539,6 +512,7 @@ xge_hal_device_rts_mac_disable(xge_hal_device_h devh, int index); int xge_hal_reinitialize_hw(xge_hal_device_t * hldev); +xge_hal_status_e xge_hal_fix_rldram_ecc_error(xge_hal_device_t * hldev); /** * xge_hal_device_rti_reconfigure * @hldev: Hal Device @@ -602,7 +576,7 @@ xge_hal_device_in_poll(xge_hal_device_h devh) static inline void xge_hal_device_inject_ecc(xge_hal_device_h devh, u64 err_reg) { - ((xge_hal_device_t*)devh)->inject_ecc = err_reg; + ((xge_hal_device_t*)devh)->inject_ecc = err_reg; } @@ -622,7 +596,7 @@ xge_hal_device_inject_ecc(xge_hal_device_h devh, u64 err_reg) static inline void xge_hal_device_inject_serr(xge_hal_device_h devh, u64 err_reg) { - ((xge_hal_device_t*)devh)->inject_serr = err_reg; + ((xge_hal_device_t*)devh)->inject_serr = err_reg; } @@ -645,11 +619,11 @@ xge_hal_device_inject_serr(xge_hal_device_h devh, u64 err_reg) static inline void xge_hal_device_inject_bad_tcode(xge_hal_device_h devh, int chan_type, u8 t_code) { - ((xge_hal_device_t*)devh)->inject_bad_tcode_for_chan_type = chan_type; - ((xge_hal_device_t*)devh)->inject_bad_tcode = t_code; + ((xge_hal_device_t*)devh)->inject_bad_tcode_for_chan_type = chan_type; + ((xge_hal_device_t*)devh)->inject_bad_tcode = t_code; } -void xge_hal_device_msi_enable(xge_hal_device_h devh); +void xge_hal_device_msi_enable(xge_hal_device_h devh); /* * xge_hal_device_msi_mode - Is MSI enabled? @@ -753,7 +727,7 @@ static inline xge_hal_status_e xge_hal_device_mtu_check(xge_hal_device_t *hldev, int new_mtu) { if ((new_mtu < XGE_HAL_MIN_MTU) || (new_mtu > XGE_HAL_MAX_MTU)) { - return XGE_HAL_ERR_INVALID_MTU_SIZE; + return XGE_HAL_ERR_INVALID_MTU_SIZE; } return XGE_HAL_OK; @@ -766,20 +740,20 @@ void xge_hal_device_bcast_disable(xge_hal_device_h devh); void xge_hal_device_terminating(xge_hal_device_h devh); xge_hal_status_e xge_hal_device_initialize(xge_hal_device_t *hldev, - xge_hal_device_attr_t *attr, xge_hal_device_config_t *config); + xge_hal_device_attr_t *attr, xge_hal_device_config_t *config); void xge_hal_device_terminate(xge_hal_device_t *hldev); xge_hal_status_e xge_hal_device_reset(xge_hal_device_t *hldev); xge_hal_status_e xge_hal_device_macaddr_get(xge_hal_device_t *hldev, - int index, macaddr_t *macaddr); + int index, macaddr_t *macaddr); xge_hal_status_e xge_hal_device_macaddr_set(xge_hal_device_t *hldev, - int index, macaddr_t macaddr); + int index, macaddr_t macaddr); xge_hal_status_e xge_hal_device_macaddr_clear(xge_hal_device_t *hldev, - int index); + int index); int xge_hal_device_macaddr_find(xge_hal_device_t *hldev, macaddr_t wanted); @@ -804,14 +778,14 @@ xge_hal_status_e xge_hal_device_disable(xge_hal_device_t *hldev); xge_hal_status_e xge_hal_device_enable(xge_hal_device_t *hldev); xge_hal_status_e xge_hal_device_handle_tcode(xge_hal_channel_h channelh, - xge_hal_dtr_h dtrh, - u8 t_code); + xge_hal_dtr_h dtrh, + u8 t_code); xge_hal_status_e xge_hal_device_link_state(xge_hal_device_h devh, - xge_hal_device_link_state_e *ls); + xge_hal_device_link_state_e *ls); void xge_hal_device_sched_timer(xge_hal_device_h devh, int interval_us, - int one_shot); + int one_shot); void xge_hal_device_poll(xge_hal_device_h devh); @@ -821,18 +795,18 @@ int xge_hal_device_is_slot_freeze(xge_hal_device_h devh); xge_hal_status_e xge_hal_device_pci_info_get(xge_hal_device_h devh, xge_hal_pci_mode_e *pci_mode, - xge_hal_pci_bus_frequency_e *bus_frequency, - xge_hal_pci_bus_width_e *bus_width); + xge_hal_pci_bus_frequency_e *bus_frequency, + xge_hal_pci_bus_width_e *bus_width); xge_hal_status_e xge_hal_spdm_entry_add(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip, - xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp, - u8 is_tcp, u8 is_ipv4, u8 tgt_queue); + xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp, + u8 is_tcp, u8 is_ipv4, u8 tgt_queue); xge_hal_status_e xge_hal_spdm_entry_remove(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip, - xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp, - u8 is_tcp, u8 is_ipv4); + xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp, + u8 is_tcp, u8 is_ipv4); xge_hal_status_e xge_hal_device_rts_section_enable(xge_hal_device_h devh, int index); @@ -850,7 +824,7 @@ u64 __hal_serial_mem_read64(xge_hal_device_t *hldev, u64 *reg); /* Some function protoypes for MSI implementation. */ xge_hal_status_e xge_hal_channel_msi_set (xge_hal_channel_h channelh, int msi, - u32 msg_val); + u32 msg_val); void xge_hal_mask_msi(xge_hal_device_t *hldev); @@ -869,6 +843,9 @@ xge_hal_unmask_msix(xge_hal_device_h devh, int msi_id); #if defined(XGE_HAL_CONFIG_LRO) xge_hal_status_e xge_hal_lro_init(u32 lro_scale, xge_hal_device_t *hldev); + +void +xge_hal_lro_terminate(u32 lro_scale, xge_hal_device_t *hldev); #endif #if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_DEVICE) @@ -910,7 +887,7 @@ xge_hal_device_isrbar0_set(xge_hal_device_t *hldev, char *isrbar0); __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void xge_hal_device_bar1_set(xge_hal_device_t *hldev, xge_hal_channel_h channelh, - char *bar1); + char *bar1); __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void xge_hal_device_mask_tx(xge_hal_device_t *hldev); @@ -972,44 +949,41 @@ __hal_tcp_lro_capable(iplro_t *ip, tcplro_t *tcp, lro_t *lro, int *ts_off); __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e __hal_lro_capable(u8 *buffer, iplro_t **ip, tcplro_t **tcp, - xge_hal_dtr_info_t *ext_info); + xge_hal_dtr_info_t *ext_info); __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e __hal_get_lro_session(u8 *eth_hdr, iplro_t *ip, tcplro_t *tcp, lro_t **lro, - xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev, - xge_hal_lro_desc_t *ring_lro, lro_t **lro_end3); + xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev, + xge_hal_lro_desc_t *ring_lro, lro_t **lro_end3); __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e __hal_lro_under_optimal_thresh(iplro_t *ip, tcplro_t *tcp, lro_t *lro, - xge_hal_device_t *hldev); + xge_hal_device_t *hldev); __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e __hal_collapse_ip_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro, - xge_hal_device_t *hldev); + xge_hal_device_t *hldev); __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e __hal_collapse_tcp_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro, - xge_hal_device_t *hldev); + xge_hal_device_t *hldev); __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e __hal_append_lro(iplro_t *ip, tcplro_t **tcp, u32 *seg_len, lro_t *lro, - xge_hal_device_t *hldev); + xge_hal_device_t *hldev); __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e xge_hal_lro_process_rx(int ring, u8 *eth_hdr, u8 *ip_hdr, tcplro_t **tcp, - u32 *seglen, lro_t **p_lro, - xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev, - lro_t **lro_end3); + u32 *seglen, lro_t **p_lro, + xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev, + lro_t **lro_end3); __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e xge_hal_accumulate_large_rx(u8 *buffer, tcplro_t **tcp, u32 *seglen, - lro_t **lro, xge_hal_dtr_info_t *ext_info, - xge_hal_device_t *hldev, lro_t **lro_end3); + lro_t **lro, xge_hal_dtr_info_t *ext_info, + xge_hal_device_t *hldev, lro_t **lro_end3); -void -xge_hal_lro_terminate(u32 lro_scale, xge_hal_device_t *hldev); - -__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t * +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t * xge_hal_lro_next_session (xge_hal_device_t *hldev, int ring); __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t * @@ -1017,11 +991,11 @@ xge_hal_lro_get_next_session(xge_hal_device_t *hldev); __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void __hal_open_lro_session (u8 *buffer, iplro_t *ip, tcplro_t *tcp, lro_t **lro, - xge_hal_device_t *hldev, xge_hal_lro_desc_t *ring_lro, - int slot, u32 tcp_seg_len, int ts_off); + xge_hal_device_t *hldev, xge_hal_lro_desc_t *ring_lro, + int slot, u32 tcp_seg_len, int ts_off); __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int -__hal_lro_get_free_slot (xge_hal_lro_desc_t *ring_lro); +__hal_lro_get_free_slot (xge_hal_lro_desc_t *ring_lro); #endif #else /* XGE_FASTPATH_EXTERN */ diff --git a/sys/dev/nxge/include/xgehal-driver.h b/sys/dev/nxge/include/xgehal-driver.h index e669368..507031b 100644 --- a/sys/dev/nxge/include/xgehal-driver.h +++ b/sys/dev/nxge/include/xgehal-driver.h @@ -26,14 +26,6 @@ * $FreeBSD$ */ -/* - * FileName : xgehal-driver.h - * - * Description: HAL driver object functionality - * - * Created: 14 May 2004 - */ - #ifndef XGE_HAL_DRIVER_H #define XGE_HAL_DRIVER_H @@ -47,7 +39,7 @@ __EXTERN_BEGIN_DECLS /* maximum number of events consumed in a syncle poll() cycle */ -#define XGE_HAL_DRIVER_QUEUE_CONSUME_MAX 5 +#define XGE_HAL_DRIVER_QUEUE_CONSUME_MAX 5 /** @@ -112,7 +104,7 @@ typedef void (*xge_uld_link_down_f) (void *userdata); * xge_hal_device_private_set(), xge_hal_driver_initialize(). */ typedef void (*xge_uld_crit_err_f) (void *userdata, xge_hal_event_e type, - u64 ext_data); + u64 ext_data); /** * function xge_uld_event_queued_f - Event-enqueued notification @@ -216,15 +208,15 @@ typedef void (*xge_uld_xpak_alarm_log_f) (xge_hal_device_h devh, xge_hal_xpak_al * See also: xge_hal_driver_initialize(). */ typedef struct xge_hal_uld_cbs_t { - xge_uld_link_up_f link_up; - xge_uld_link_down_f link_down; - xge_uld_crit_err_f crit_err; - xge_uld_event_f event; - xge_uld_event_queued_f event_queued; + xge_uld_link_up_f link_up; + xge_uld_link_down_f link_down; + xge_uld_crit_err_f crit_err; + xge_uld_event_f event; + xge_uld_event_queued_f event_queued; xge_uld_before_device_poll_f before_device_poll; - xge_uld_after_device_poll_f after_device_poll; - xge_uld_sched_timer_cb_f sched_timer; - xge_uld_xpak_alarm_log_f xpak_alarm_log; + xge_uld_after_device_poll_f after_device_poll; + xge_uld_sched_timer_cb_f sched_timer; + xge_uld_xpak_alarm_log_f xpak_alarm_log; } xge_hal_uld_cbs_t; /** @@ -238,19 +230,19 @@ typedef struct xge_hal_uld_cbs_t { * @uld_callbacks: Upper-layer driver callbacks. See xge_hal_uld_cbs_t{}. * @debug_module_mask: 32bit mask that defines which components of the * driver are to be traced. The trace-able components are: - * XGE_COMPONENT_HAL_CONFIG 0x1 - * XGE_COMPONENT_HAL_FIFO 0x2 - * XGE_COMPONENT_HAL_RING 0x4 - * XGE_COMPONENT_HAL_CHANNEL 0x8 - * XGE_COMPONENT_HAL_DEVICE 0x10 - * XGE_COMPONENT_HAL_MM 0x20 - * XGE_COMPONENT_HAL_QUEUE 0x40 - * XGE_COMPONENT_HAL_STATS 0x100 - * XGE_COMPONENT_OSDEP 0x1000 - * XGE_COMPONENT_LL 0x2000 - * XGE_COMPONENT_TOE 0x4000 - * XGE_COMPONENT_RDMA 0x8000 - * XGE_COMPONENT_ALL 0xffffffff + * XGE_COMPONENT_HAL_CONFIG 0x1 + * XGE_COMPONENT_HAL_FIFO 0x2 + * XGE_COMPONENT_HAL_RING 0x4 + * XGE_COMPONENT_HAL_CHANNEL 0x8 + * XGE_COMPONENT_HAL_DEVICE 0x10 + * XGE_COMPONENT_HAL_MM 0x20 + * XGE_COMPONENT_HAL_QUEUE 0x40 + * XGE_COMPONENT_HAL_STATS 0x100 + * XGE_COMPONENT_OSDEP 0x1000 + * XGE_COMPONENT_LL 0x2000 + * XGE_COMPONENT_TOE 0x4000 + * XGE_COMPONENT_RDMA 0x8000 + * XGE_COMPONENT_ALL 0xffffffff * The @debug_module_mask allows to switch off and on tracing at runtime. * In addition, the traces for the same trace-able components can be * compiled out, based on the same mask provided via Makefile. @@ -259,18 +251,18 @@ typedef struct xge_hal_uld_cbs_t { * HAL (driver) object. There is a single instance of this structure per HAL. */ typedef struct xge_hal_driver_t { - xge_hal_driver_config_t config; + xge_hal_driver_config_t config; int is_initialized; xge_hal_uld_cbs_t uld_callbacks; - u32 debug_module_mask; - int debug_level; + u32 debug_module_mask; + int debug_level; } xge_hal_driver_t; extern xge_hal_driver_t *g_xge_hal_driver; static inline int xge_hal_driver_is_initialized(void) { - return g_xge_hal_driver->is_initialized; + return g_xge_hal_driver->is_initialized; } static inline int @@ -283,7 +275,7 @@ static inline void xge_hal_driver_debug_module_mask_set(u32 new_mask) { #if (defined(XGE_DEBUG_TRACE_MASK) && XGE_DEBUG_TRACE_MASK > 0) || \ - (defined(XGE_DEBUG_ERR_MASK) && XGE_DEBUG_ERR_MASK > 0) + (defined(XGE_DEBUG_ERR_MASK) && XGE_DEBUG_ERR_MASK > 0) g_xge_hal_driver->debug_module_mask = new_mask; g_module_mask = (unsigned long *)&g_xge_hal_driver->debug_module_mask; #endif @@ -296,14 +288,14 @@ static inline void xge_hal_driver_debug_level_set(int new_level) { #if (defined(XGE_DEBUG_TRACE_MASK) && XGE_DEBUG_TRACE_MASK > 0) || \ - (defined(XGE_DEBUG_ERR_MASK) && XGE_DEBUG_ERR_MASK > 0) + (defined(XGE_DEBUG_ERR_MASK) && XGE_DEBUG_ERR_MASK > 0) g_xge_hal_driver->debug_level = new_level; g_level = &g_xge_hal_driver->debug_level; #endif } xge_hal_status_e xge_hal_driver_initialize(xge_hal_driver_config_t *config, - xge_hal_uld_cbs_t *uld_callbacks); + xge_hal_uld_cbs_t *uld_callbacks); void xge_hal_driver_terminate(void); diff --git a/sys/dev/nxge/include/xgehal-event.h b/sys/dev/nxge/include/xgehal-event.h index 7d560d2..1613aae 100644 --- a/sys/dev/nxge/include/xgehal-event.h +++ b/sys/dev/nxge/include/xgehal-event.h @@ -26,14 +26,6 @@ * $FreeBSD$ */ -/* - * FileName : xgehal-event.h - * - * Description: event types - * - * Created: 7 June 2004 - */ - #ifndef XGE_HAL_EVENT_H #define XGE_HAL_EVENT_H @@ -41,8 +33,8 @@ __EXTERN_BEGIN_DECLS -#define XGE_HAL_EVENT_BASE 0 -#define XGE_LL_EVENT_BASE 100 +#define XGE_HAL_EVENT_BASE 0 +#define XGE_LL_EVENT_BASE 100 /** * enum xge_hal_event_e - Enumerates slow-path HAL events. @@ -69,15 +61,15 @@ __EXTERN_BEGIN_DECLS * xge_uld_link_down_f{}. */ typedef enum xge_hal_event_e { - XGE_HAL_EVENT_UNKNOWN = 0, + XGE_HAL_EVENT_UNKNOWN = 0, /* HAL events */ - XGE_HAL_EVENT_SERR = XGE_HAL_EVENT_BASE + 1, - XGE_HAL_EVENT_LINK_IS_UP = XGE_HAL_EVENT_BASE + 2, - XGE_HAL_EVENT_LINK_IS_DOWN = XGE_HAL_EVENT_BASE + 3, - XGE_HAL_EVENT_ECCERR = XGE_HAL_EVENT_BASE + 4, - XGE_HAL_EVENT_PARITYERR = XGE_HAL_EVENT_BASE + 5, - XGE_HAL_EVENT_TARGETABORT = XGE_HAL_EVENT_BASE + 6, - XGE_HAL_EVENT_SLOT_FREEZE = XGE_HAL_EVENT_BASE + 7, + XGE_HAL_EVENT_SERR = XGE_HAL_EVENT_BASE + 1, + XGE_HAL_EVENT_LINK_IS_UP = XGE_HAL_EVENT_BASE + 2, + XGE_HAL_EVENT_LINK_IS_DOWN = XGE_HAL_EVENT_BASE + 3, + XGE_HAL_EVENT_ECCERR = XGE_HAL_EVENT_BASE + 4, + XGE_HAL_EVENT_PARITYERR = XGE_HAL_EVENT_BASE + 5, + XGE_HAL_EVENT_TARGETABORT = XGE_HAL_EVENT_BASE + 6, + XGE_HAL_EVENT_SLOT_FREEZE = XGE_HAL_EVENT_BASE + 7, } xge_hal_event_e; __EXTERN_END_DECLS diff --git a/sys/dev/nxge/include/xgehal-fifo.h b/sys/dev/nxge/include/xgehal-fifo.h index 6de6048..5f082d6 100644 --- a/sys/dev/nxge/include/xgehal-fifo.h +++ b/sys/dev/nxge/include/xgehal-fifo.h @@ -26,14 +26,6 @@ * $FreeBSD$ */ -/* - * FileName : xgehal-fifo.h - * - * Description: Tx fifo object functionality - * - * Created: 19 May 2004 - */ - #ifndef XGE_HAL_FIFO_H #define XGE_HAL_FIFO_H @@ -44,11 +36,11 @@ __EXTERN_BEGIN_DECLS /* HW fifo configuration */ -#define XGE_HAL_FIFO_INT_PER_LIST_THRESHOLD 65 -#define XGE_HAL_FIFO_MAX_WRR 5 -#define XGE_HAL_FIFO_MAX_PARTITION 4 -#define XGE_HAL_FIFO_MAX_WRR_STATE 36 -#define XGE_HAL_FIFO_HW_PAIR_OFFSET 0x20000 +#define XGE_HAL_FIFO_INT_PER_LIST_THRESHOLD 65 +#define XGE_HAL_FIFO_MAX_WRR 5 +#define XGE_HAL_FIFO_MAX_PARTITION 4 +#define XGE_HAL_FIFO_MAX_WRR_STATE 36 +#define XGE_HAL_FIFO_HW_PAIR_OFFSET 0x20000 /* HW FIFO Weight Calender */ #define XGE_HAL_FIFO_WRR_0 0x0706050407030602ULL @@ -77,14 +69,14 @@ typedef struct { /* Bad TxDL transfer codes */ -#define XGE_HAL_TXD_T_CODE_OK 0x0 -#define XGE_HAL_TXD_T_CODE_UNUSED_1 0x1 -#define XGE_HAL_TXD_T_CODE_ABORT_BUFFER 0x2 -#define XGE_HAL_TXD_T_CODE_ABORT_DTOR 0x3 -#define XGE_HAL_TXD_T_CODE_UNUSED_5 0x5 -#define XGE_HAL_TXD_T_CODE_PARITY 0x7 -#define XGE_HAL_TXD_T_CODE_LOSS_OF_LINK 0xA -#define XGE_HAL_TXD_T_CODE_GENERAL_ERR 0xF +#define XGE_HAL_TXD_T_CODE_OK 0x0 +#define XGE_HAL_TXD_T_CODE_UNUSED_1 0x1 +#define XGE_HAL_TXD_T_CODE_ABORT_BUFFER 0x2 +#define XGE_HAL_TXD_T_CODE_ABORT_DTOR 0x3 +#define XGE_HAL_TXD_T_CODE_UNUSED_5 0x5 +#define XGE_HAL_TXD_T_CODE_PARITY 0x7 +#define XGE_HAL_TXD_T_CODE_LOSS_OF_LINK 0xA +#define XGE_HAL_TXD_T_CODE_GENERAL_ERR 0xF /** @@ -105,16 +97,16 @@ typedef struct { typedef struct xge_hal_fifo_txd_t { u64 control_1; #define XGE_HAL_TXD_LIST_OWN_XENA BIT(7) -#define XGE_HAL_TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15)) +#define XGE_HAL_TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15)) #define XGE_HAL_GET_TXD_T_CODE(val) ((val & XGE_HAL_TXD_T_CODE)>>48) #define XGE_HAL_SET_TXD_T_CODE(x, val) (x |= (((u64)val & 0xF) << 48)) #define XGE_HAL_TXD_GATHER_CODE (BIT(22) | BIT(23)) #define XGE_HAL_TXD_GATHER_CODE_FIRST BIT(22) #define XGE_HAL_TXD_GATHER_CODE_LAST BIT(23) -#define XGE_HAL_TXD_NO_LSO 0 -#define XGE_HAL_TXD_UDF_COF 1 -#define XGE_HAL_TXD_TCP_LSO 2 -#define XGE_HAL_TXD_UDP_LSO 3 +#define XGE_HAL_TXD_NO_LSO 0 +#define XGE_HAL_TXD_UDF_COF 1 +#define XGE_HAL_TXD_TCP_LSO 2 +#define XGE_HAL_TXD_UDP_LSO 3 #define XGE_HAL_TXD_LSO_COF_CTRL(val) vBIT(val,30,2) #define XGE_HAL_TXD_TCP_LSO_MSS(val) vBIT(val,34,14) #define XGE_HAL_TXD_BUFFER0_SIZE(val) vBIT(val,48,16) @@ -165,17 +157,17 @@ typedef xge_hal_fifo_txd_t* xge_hal_fifo_txdl_t; * Note: The structure is cache line aligned. */ typedef struct xge_hal_fifo_t { - xge_hal_channel_t channel; - spinlock_t *post_lock_ptr; - xge_hal_fifo_hw_pair_t *hw_pair; - xge_hal_fifo_config_t *config; - int no_snoop_bits; - int txdl_per_memblock; - u64 interrupt_type; - int txdl_size; - int priv_size; - xge_hal_mempool_t *mempool; - int align_size; + xge_hal_channel_t channel; + spinlock_t *post_lock_ptr; + xge_hal_fifo_hw_pair_t *hw_pair; + xge_hal_fifo_config_t *config; + int no_snoop_bits; + int txdl_per_memblock; + u64 interrupt_type; + int txdl_size; + int priv_size; + xge_hal_mempool_t *mempool; + int align_size; } __xge_os_attr_cacheline_aligned xge_hal_fifo_t; /** @@ -228,30 +220,30 @@ typedef struct xge_hal_fifo_t { * See also: xge_hal_ring_rxd_priv_t{}. */ typedef struct xge_hal_fifo_txdl_priv_t { - dma_addr_t dma_addr; - pci_dma_h dma_handle; - ptrdiff_t dma_offset; - int frags; - char *align_vaddr_start; - char *align_vaddr; - dma_addr_t align_dma_addr; - pci_dma_h align_dma_handle; - pci_dma_acc_h align_dma_acch; - ptrdiff_t align_dma_offset; - int align_used_frags; - int alloc_frags; - int dang_frags; - unsigned int bytes_sent; - int unused; - xge_hal_fifo_txd_t *dang_txdl; - struct xge_hal_fifo_txdl_priv_t *next_txdl_priv; - xge_hal_fifo_txd_t *first_txdp; - void *memblock; + dma_addr_t dma_addr; + pci_dma_h dma_handle; + ptrdiff_t dma_offset; + int frags; + char *align_vaddr_start; + char *align_vaddr; + dma_addr_t align_dma_addr; + pci_dma_h align_dma_handle; + pci_dma_acc_h align_dma_acch; + ptrdiff_t align_dma_offset; + int align_used_frags; + int alloc_frags; + int dang_frags; + unsigned int bytes_sent; + int unused; + xge_hal_fifo_txd_t *dang_txdl; + struct xge_hal_fifo_txdl_priv_t *next_txdl_priv; + xge_hal_fifo_txd_t *first_txdp; + void *memblock; #ifdef XGE_DEBUG_ASSERT - xge_hal_mempool_dma_t *dma_object; + xge_hal_mempool_dma_t *dma_object; #endif #ifdef XGE_OS_MEMORY_CHECK - int allocated; + int allocated; #endif } xge_hal_fifo_txdl_priv_t; @@ -268,7 +260,7 @@ xge_hal_fifo_get_max_frags_cnt(xge_hal_channel_h channelh) /* ========================= FIFO PRIVATE API ============================= */ xge_hal_status_e __hal_fifo_open(xge_hal_channel_h channelh, - xge_hal_channel_attr_t *attr); + xge_hal_channel_attr_t *attr); void __hal_fifo_close(xge_hal_channel_h channelh); @@ -289,16 +281,20 @@ __hal_fifo_txdl_priv(xge_hal_dtr_h dtrh); __HAL_STATIC_FIFO __HAL_INLINE_FIFO void __hal_fifo_dtr_post_single(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, - u64 ctrl_1); + u64 ctrl_1); __HAL_STATIC_FIFO __HAL_INLINE_FIFO void __hal_fifo_txdl_restore_many(xge_hal_channel_h channelh, - xge_hal_fifo_txd_t *txdp, int txdl_count); + xge_hal_fifo_txd_t *txdp, int txdl_count); /* ========================= FIFO PUBLIC API ============================== */ __HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e xge_hal_fifo_dtr_reserve(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh); +__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e +xge_hal_fifo_dtr_reserve_many(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh, + const int frags); + __HAL_STATIC_FIFO __HAL_INLINE_FIFO void* xge_hal_fifo_dtr_private(xge_hal_dtr_h dtrh); @@ -307,38 +303,38 @@ xge_hal_fifo_dtr_buffer_cnt(xge_hal_dtr_h dtrh); __HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e xge_hal_fifo_dtr_reserve_sp(xge_hal_channel_h channel, int dtr_sp_size, - xge_hal_dtr_h dtr_sp); + xge_hal_dtr_h dtr_sp); __HAL_STATIC_FIFO __HAL_INLINE_FIFO void -xge_hal_fifo_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); +xge_hal_fifo_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); __HAL_STATIC_FIFO __HAL_INLINE_FIFO void xge_hal_fifo_dtr_post_many(xge_hal_channel_h channelh, int num, - xge_hal_dtr_h dtrs[]); + xge_hal_dtr_h dtrs[]); __HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e xge_hal_fifo_dtr_next_completed(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh, - u8 *t_code); + u8 *t_code); __HAL_STATIC_FIFO __HAL_INLINE_FIFO void -xge_hal_fifo_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtr); +xge_hal_fifo_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtr); __HAL_STATIC_FIFO __HAL_INLINE_FIFO void xge_hal_fifo_dtr_buffer_set(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, - int frag_idx, dma_addr_t dma_pointer, int size); + int frag_idx, dma_addr_t dma_pointer, int size); __HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e xge_hal_fifo_dtr_buffer_set_aligned(xge_hal_channel_h channelh, - xge_hal_dtr_h dtrh, int frag_idx, void *vaddr, - dma_addr_t dma_pointer, int size, int misaligned_size); + xge_hal_dtr_h dtrh, int frag_idx, void *vaddr, + dma_addr_t dma_pointer, int size, int misaligned_size); __HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e xge_hal_fifo_dtr_buffer_append(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, - void *vaddr, int size); + void *vaddr, int size); __HAL_STATIC_FIFO __HAL_INLINE_FIFO void xge_hal_fifo_dtr_buffer_finalize(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, - int frag_idx); + int frag_idx); __HAL_STATIC_FIFO __HAL_INLINE_FIFO void xge_hal_fifo_dtr_mss_set(xge_hal_dtr_h dtrh, int mss); @@ -347,7 +343,7 @@ __HAL_STATIC_FIFO __HAL_INLINE_FIFO void xge_hal_fifo_dtr_cksum_set_bits(xge_hal_dtr_h dtrh, u64 cksum_bits); __HAL_STATIC_FIFO __HAL_INLINE_FIFO void -xge_hal_fifo_dtr_vlan_set(xge_hal_dtr_h dtrh, u16 vlan_tag); +xge_hal_fifo_dtr_vlan_set(xge_hal_dtr_h dtrh, u16 vlan_tag); __HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e xge_hal_fifo_is_next_dtr_completed(xge_hal_channel_h channelh); diff --git a/sys/dev/nxge/include/xgehal-mgmt.h b/sys/dev/nxge/include/xgehal-mgmt.h index 061320e..93e60a2 100644 --- a/sys/dev/nxge/include/xgehal-mgmt.h +++ b/sys/dev/nxge/include/xgehal-mgmt.h @@ -26,14 +26,6 @@ * $FreeBSD$ */ -/* - * FileName : xgehal-mgmt.h - * - * Description: management API - * - * Created: 1 September 2004 - */ - #ifndef XGE_HAL_MGMT_H #define XGE_HAL_MGMT_H @@ -68,88 +60,88 @@ __EXTERN_BEGIN_DECLS * @transponder_temperature: TODO */ typedef struct xge_hal_mgmt_about_info_t { - u16 vendor; - u16 device; - u16 subsys_vendor; - u16 subsys_device; - u8 board_rev; - char vendor_name[16]; - char chip_name[16]; - char media[16]; - char hal_major[4]; - char hal_minor[4]; - char hal_fix[4]; - char hal_build[16]; - char ll_major[4]; - char ll_minor[4]; - char ll_fix[4]; - char ll_build[16]; - u32 transponder_temperature; + u16 vendor; + u16 device; + u16 subsys_vendor; + u16 subsys_device; + u8 board_rev; + char vendor_name[16]; + char chip_name[16]; + char media[16]; + char hal_major[4]; + char hal_minor[4]; + char hal_fix[4]; + char hal_build[16]; + char ll_major[4]; + char ll_minor[4]; + char ll_fix[4]; + char ll_build[16]; + u32 transponder_temperature; } xge_hal_mgmt_about_info_t; -typedef xge_hal_stats_hw_info_t xge_hal_mgmt_hw_stats_t; -typedef xge_hal_stats_pcim_info_t xge_hal_mgmt_pcim_stats_t; -typedef xge_hal_stats_sw_err_t xge_hal_mgmt_sw_stats_t; -typedef xge_hal_stats_device_info_t xge_hal_mgmt_device_stats_t; -typedef xge_hal_stats_channel_info_t xge_hal_mgmt_channel_stats_t; -typedef xge_hal_device_config_t xge_hal_mgmt_device_config_t; -typedef xge_hal_driver_config_t xge_hal_mgmt_driver_config_t; -typedef xge_hal_pci_config_t xge_hal_mgmt_pci_config_t; +typedef xge_hal_stats_hw_info_t xge_hal_mgmt_hw_stats_t; +typedef xge_hal_stats_pcim_info_t xge_hal_mgmt_pcim_stats_t; +typedef xge_hal_stats_sw_err_t xge_hal_mgmt_sw_stats_t; +typedef xge_hal_stats_device_info_t xge_hal_mgmt_device_stats_t; +typedef xge_hal_stats_channel_info_t xge_hal_mgmt_channel_stats_t; +typedef xge_hal_device_config_t xge_hal_mgmt_device_config_t; +typedef xge_hal_driver_config_t xge_hal_mgmt_driver_config_t; +typedef xge_hal_pci_config_t xge_hal_mgmt_pci_config_t; xge_hal_status_e xge_hal_mgmt_about(xge_hal_device_h devh, xge_hal_mgmt_about_info_t *about_info, - int size); + int size); xge_hal_status_e xge_hal_mgmt_hw_stats(xge_hal_device_h devh, xge_hal_mgmt_hw_stats_t *hw_stats, - int size); + int size); xge_hal_status_e xge_hal_mgmt_hw_stats_off(xge_hal_device_h devh, int off, int size, char *out); xge_hal_status_e xge_hal_mgmt_pcim_stats(xge_hal_device_h devh, - xge_hal_mgmt_pcim_stats_t *pcim_stats, int size); + xge_hal_mgmt_pcim_stats_t *pcim_stats, int size); xge_hal_status_e xge_hal_mgmt_pcim_stats_off(xge_hal_device_h devh, int off, int size, - char *out); + char *out); xge_hal_status_e xge_hal_mgmt_sw_stats(xge_hal_device_h devh, xge_hal_mgmt_sw_stats_t *hw_stats, - int size); + int size); xge_hal_status_e xge_hal_mgmt_device_stats(xge_hal_device_h devh, - xge_hal_mgmt_device_stats_t *device_stats, int size); + xge_hal_mgmt_device_stats_t *device_stats, int size); xge_hal_status_e xge_hal_mgmt_channel_stats(xge_hal_channel_h channelh, - xge_hal_mgmt_channel_stats_t *channel_stats, int size); + xge_hal_mgmt_channel_stats_t *channel_stats, int size); xge_hal_status_e xge_hal_mgmt_reg_read(xge_hal_device_h devh, int bar_id, unsigned int offset, - u64 *value); + u64 *value); xge_hal_status_e -xge_hal_mgmt_reg_write(xge_hal_device_h devh, int bar_id, unsigned int offset, - u64 value); +xge_hal_mgmt_reg_write(xge_hal_device_h devh, int bar_id, unsigned int offset, + u64 value); xge_hal_status_e xge_hal_mgmt_pcireg_read(xge_hal_device_h devh, unsigned int offset, - int bits, u32 *value); + int bits, u32 *value); xge_hal_status_e xge_hal_mgmt_device_config(xge_hal_device_h devh, - xge_hal_mgmt_device_config_t *dev_config, int size); + xge_hal_mgmt_device_config_t *dev_config, int size); xge_hal_status_e xge_hal_mgmt_driver_config(xge_hal_mgmt_driver_config_t *drv_config, - int size); + int size); xge_hal_status_e xge_hal_mgmt_pci_config(xge_hal_device_h devh, - xge_hal_mgmt_pci_config_t *pci_config, int size); + xge_hal_mgmt_pci_config_t *pci_config, int size); xge_hal_status_e xge_hal_pma_loopback( xge_hal_device_h devh, int enable ); @@ -199,7 +191,7 @@ __hal_chk_xpak_counter(xge_hal_device_t *hldev, int type, u32 value); #ifdef XGE_TRACE_INTO_CIRCULAR_ARR xge_hal_status_e xge_hal_mgmt_trace_read(char *buffer, unsigned buf_size, unsigned *offset, - unsigned *read_length); + unsigned *read_length); #endif void @@ -215,8 +207,8 @@ xge_hal_flick_link_led(xge_hal_device_h devh); * given its Sub system ID. */ #define CARDS_WITH_FAULTY_LINK_INDICATORS(subid) \ - ((((subid >= 0x600B) && (subid <= 0x600D)) || \ - ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) + ((((subid >= 0x600B) && (subid <= 0x600D)) || \ + ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) #define CHECKBIT(value, nbit) (value & (1 << nbit)) #ifdef XGE_HAL_USE_MGMT_AUX diff --git a/sys/dev/nxge/include/xgehal-mgmtaux.h b/sys/dev/nxge/include/xgehal-mgmtaux.h index 6d4922e..93a9865 100644 --- a/sys/dev/nxge/include/xgehal-mgmtaux.h +++ b/sys/dev/nxge/include/xgehal-mgmtaux.h @@ -26,14 +26,6 @@ * $FreeBSD$ */ -/* - * FileName : xgehal-mgmtaux.h - * - * Description: management auxiliary API - * - * Created: 1 September 2004 - */ - #ifndef XGE_HAL_MGMTAUX_H #define XGE_HAL_MGMTAUX_H @@ -41,54 +33,54 @@ __EXTERN_BEGIN_DECLS -#define XGE_HAL_AUX_SEPA ' ' +#define XGE_HAL_AUX_SEPA ' ' xge_hal_status_e xge_hal_aux_about_read(xge_hal_device_h devh, int bufsize, - char *retbuf, int *retsize); + char *retbuf, int *retsize); -xge_hal_status_e xge_hal_aux_stats_tmac_read(xge_hal_device_h devh, int bufsize, - char *retbuf, int *retsize); +xge_hal_status_e xge_hal_aux_stats_tmac_read(xge_hal_device_h devh, int bufsize, + char *retbuf, int *retsize); -xge_hal_status_e xge_hal_aux_stats_rmac_read(xge_hal_device_h devh, int bufsize, - char *retbuf, int *retsize); +xge_hal_status_e xge_hal_aux_stats_rmac_read(xge_hal_device_h devh, int bufsize, + char *retbuf, int *retsize); xge_hal_status_e xge_hal_aux_stats_sw_dev_read(xge_hal_device_h devh, - int bufsize, char *retbuf, int *retsize); + int bufsize, char *retbuf, int *retsize); xge_hal_status_e xge_hal_aux_stats_pci_read(xge_hal_device_h devh, int bufsize, - char *retbuf, int *retsize); + char *retbuf, int *retsize); xge_hal_status_e xge_hal_aux_stats_hal_read(xge_hal_device_h devh, int bufsize, - char *retbuf, int *retsize); + char *retbuf, int *retsize); -xge_hal_status_e xge_hal_aux_bar0_read(xge_hal_device_h devh, - unsigned int offset, int bufsize, char *retbuf, - int *retsize); +xge_hal_status_e xge_hal_aux_bar0_read(xge_hal_device_h devh, + unsigned int offset, int bufsize, char *retbuf, + int *retsize); xge_hal_status_e xge_hal_aux_bar0_write(xge_hal_device_h devh, - unsigned int offset, u64 value); + unsigned int offset, u64 value); xge_hal_status_e xge_hal_aux_bar1_read(xge_hal_device_h devh, - unsigned int offset, int bufsize, char *retbuf, - int *retsize); + unsigned int offset, int bufsize, char *retbuf, + int *retsize); -xge_hal_status_e xge_hal_aux_pci_config_read(xge_hal_device_h devh, int bufsize, - char *retbuf, int *retsize); +xge_hal_status_e xge_hal_aux_pci_config_read(xge_hal_device_h devh, int bufsize, + char *retbuf, int *retsize); xge_hal_status_e xge_hal_aux_stats_herc_enchanced(xge_hal_device_h devh, - int bufsize, char *retbuf, int *retsize); + int bufsize, char *retbuf, int *retsize); xge_hal_status_e xge_hal_aux_channel_read(xge_hal_device_h devh, int bufsize, - char *retbuf, int *retsize); + char *retbuf, int *retsize); xge_hal_status_e xge_hal_aux_device_dump(xge_hal_device_h devh); xge_hal_status_e xge_hal_aux_driver_config_read(int bufsize, char *retbuf, - int *retsize); + int *retsize); xge_hal_status_e xge_hal_aux_device_config_read(xge_hal_device_h devh, - int bufsize, char *retbuf, int *retsize); + int bufsize, char *retbuf, int *retsize); __EXTERN_END_DECLS diff --git a/sys/dev/nxge/include/xgehal-mm.h b/sys/dev/nxge/include/xgehal-mm.h index 5a8f836..7b43de4 100644 --- a/sys/dev/nxge/include/xgehal-mm.h +++ b/sys/dev/nxge/include/xgehal-mm.h @@ -26,14 +26,6 @@ * $FreeBSD$ */ -/* - * FileName : xgehal-mm.h - * - * Description: memory pool object - * - * Created: 28 May 2004 - */ - #ifndef XGE_HAL_MM_H #define XGE_HAL_MM_H @@ -51,9 +43,9 @@ typedef void* xge_hal_mempool_h; caller. */ typedef struct xge_hal_mempool_dma_t { - dma_addr_t addr; - pci_dma_h handle; - pci_dma_acc_h acc_handle; + dma_addr_t addr; + pci_dma_h handle; + pci_dma_acc_h acc_handle; } xge_hal_mempool_dma_t; /* @@ -67,32 +59,32 @@ typedef struct xge_hal_mempool_dma_t { * Memory pool allocation/deallocation callback. */ typedef xge_hal_status_e (*xge_hal_mempool_item_f) (xge_hal_mempool_h mempoolh, - void *memblock, int memblock_index, - xge_hal_mempool_dma_t *dma_object, void *item, - int index, int is_last, void *userdata); + void *memblock, int memblock_index, + xge_hal_mempool_dma_t *dma_object, void *item, + int index, int is_last, void *userdata); /* * struct xge_hal_mempool_t - Memory pool. */ typedef struct xge_hal_mempool_t { - xge_hal_mempool_item_f item_func_alloc; - xge_hal_mempool_item_f item_func_free; - void *userdata; - void **memblocks_arr; - void **memblocks_priv_arr; - xge_hal_mempool_dma_t *memblocks_dma_arr; - pci_dev_h pdev; - int memblock_size; - int memblocks_max; - int memblocks_allocated; - int item_size; - int items_max; - int items_initial; - int items_current; - int items_per_memblock; - void **items_arr; - void **shadow_items_arr; - int items_priv_size; + xge_hal_mempool_item_f item_func_alloc; + xge_hal_mempool_item_f item_func_free; + void *userdata; + void **memblocks_arr; + void **memblocks_priv_arr; + xge_hal_mempool_dma_t *memblocks_dma_arr; + pci_dev_h pdev; + int memblock_size; + int memblocks_max; + int memblocks_allocated; + int item_size; + int items_max; + int items_initial; + int items_current; + int items_per_memblock; + void **items_arr; + void **shadow_items_arr; + int items_priv_size; } xge_hal_mempool_t; /* @@ -110,7 +102,7 @@ __hal_mempool_item(xge_hal_mempool_t *mempool, int index) */ static inline void* __hal_mempool_item_priv(xge_hal_mempool_t *mempool, int memblock_idx, - void *item, int *memblock_item_idx) + void *item, int *memblock_item_idx) { ptrdiff_t offset; void *memblock = mempool->memblocks_arr[memblock_idx]; @@ -124,7 +116,7 @@ __hal_mempool_item_priv(xge_hal_mempool_t *mempool, int memblock_idx, xge_assert((*memblock_item_idx) < mempool->items_per_memblock); return (char*)mempool->memblocks_priv_arr[memblock_idx] + - (*memblock_item_idx) * mempool->items_priv_size; + (*memblock_item_idx) * mempool->items_priv_size; } /* @@ -159,12 +151,12 @@ __hal_mempool_memblock_dma(xge_hal_mempool_t *mempool, int memblock_idx) } xge_hal_status_e __hal_mempool_grow(xge_hal_mempool_t *mempool, - int num_allocate, int *num_allocated); + int num_allocate, int *num_allocated); xge_hal_mempool_t* __hal_mempool_create(pci_dev_h pdev, int memblock_size, - int item_size, int private_size, int items_initial, - int items_max, xge_hal_mempool_item_f item_func_alloc, - xge_hal_mempool_item_f item_func_free, void *userdata); + int item_size, int private_size, int items_initial, + int items_max, xge_hal_mempool_item_f item_func_alloc, + xge_hal_mempool_item_f item_func_free, void *userdata); void __hal_mempool_destroy(xge_hal_mempool_t *mempool); diff --git a/sys/dev/nxge/include/xgehal-regs.h b/sys/dev/nxge/include/xgehal-regs.h index 89a2c4a..a20e083 100644 --- a/sys/dev/nxge/include/xgehal-regs.h +++ b/sys/dev/nxge/include/xgehal-regs.h @@ -26,17 +26,11 @@ * $FreeBSD$ */ -/* - * FileName : xgehal-regs.h - * - * Description: Xframe mem-mapped register space - * - * Created: 14 May 2004 - */ - #ifndef XGE_HAL_REGS_H #define XGE_HAL_REGS_H +__EXTERN_BEGIN_DECLS + typedef struct { /* General Control-Status Registers */ @@ -53,14 +47,14 @@ typedef struct { #define XGE_HAL_GEN_INTR_RXXGXS BIT(36) #define XGE_HAL_GEN_INTR_RXTRAFFIC BIT(40) #define XGE_HAL_GEN_ERROR_INTR (XGE_HAL_GEN_INTR_TXPIC | \ - XGE_HAL_GEN_INTR_RXPIC | \ - XGE_HAL_GEN_INTR_TXDMA | \ - XGE_HAL_GEN_INTR_RXDMA | \ - XGE_HAL_GEN_INTR_TXMAC | \ - XGE_HAL_GEN_INTR_RXMAC | \ - XGE_HAL_GEN_INTR_TXXGXS | \ - XGE_HAL_GEN_INTR_RXXGXS | \ - XGE_HAL_GEN_INTR_MC) + XGE_HAL_GEN_INTR_RXPIC | \ + XGE_HAL_GEN_INTR_TXDMA | \ + XGE_HAL_GEN_INTR_RXDMA | \ + XGE_HAL_GEN_INTR_TXMAC | \ + XGE_HAL_GEN_INTR_RXMAC | \ + XGE_HAL_GEN_INTR_TXXGXS | \ + XGE_HAL_GEN_INTR_RXXGXS | \ + XGE_HAL_GEN_INTR_MC) u64 general_int_mask; @@ -74,17 +68,17 @@ typedef struct { #define XGE_HAL_SW_RESET_EOI vBIT(0xA5,16,8) #define XGE_HAL_SW_RESET_XGXS vBIT(0xA5,24,8) #define XGE_HAL_SW_RESET_ALL (XGE_HAL_SW_RESET_XENA | \ - XGE_HAL_SW_RESET_FLASH | \ - XGE_HAL_SW_RESET_EOI | \ - XGE_HAL_SW_RESET_XGXS) + XGE_HAL_SW_RESET_FLASH | \ + XGE_HAL_SW_RESET_EOI | \ + XGE_HAL_SW_RESET_XGXS) /* The SW_RESET register must read this value after a successful reset. */ #if defined(XGE_OS_HOST_BIG_ENDIAN) && !defined(XGE_OS_PIO_LITTLE_ENDIAN) -#define XGE_HAL_SW_RESET_RAW_VAL_XENA 0xA500000000ULL -#define XGE_HAL_SW_RESET_RAW_VAL_HERC 0xA5A500000000ULL +#define XGE_HAL_SW_RESET_RAW_VAL_XENA 0xA500000000ULL +#define XGE_HAL_SW_RESET_RAW_VAL_HERC 0xA5A500000000ULL #else -#define XGE_HAL_SW_RESET_RAW_VAL_XENA 0xA5000000ULL -#define XGE_HAL_SW_RESET_RAW_VAL_HERC 0xA5A50000ULL +#define XGE_HAL_SW_RESET_RAW_VAL_XENA 0xA5000000ULL +#define XGE_HAL_SW_RESET_RAW_VAL_HERC 0xA5A50000ULL #endif @@ -115,22 +109,22 @@ typedef struct { #define XGE_HAL_ADAPTER_ECC_EN BIT(55) u64 serr_source; -#define XGE_HAL_SERR_SOURCE_PIC BIT(0) +#define XGE_HAL_SERR_SOURCE_PIC BIT(0) #define XGE_HAL_SERR_SOURCE_TXDMA BIT(1) #define XGE_HAL_SERR_SOURCE_RXDMA BIT(2) -#define XGE_HAL_SERR_SOURCE_MAC BIT(3) -#define XGE_HAL_SERR_SOURCE_MC BIT(4) -#define XGE_HAL_SERR_SOURCE_XGXS BIT(5) -#define XGE_HAL_SERR_SOURCE_ANY (XGE_HAL_SERR_SOURCE_PIC | \ - XGE_HAL_SERR_SOURCE_TXDMA | \ - XGE_HAL_SERR_SOURCE_RXDMA | \ - XGE_HAL_SERR_SOURCE_MAC | \ - XGE_HAL_SERR_SOURCE_MC | \ - XGE_HAL_SERR_SOURCE_XGXS) - - u64 pci_info; -#define XGE_HAL_PCI_INFO vBIT(0xF,0,4) -#define XGE_HAL_PCI_32_BIT BIT(8) +#define XGE_HAL_SERR_SOURCE_MAC BIT(3) +#define XGE_HAL_SERR_SOURCE_MC BIT(4) +#define XGE_HAL_SERR_SOURCE_XGXS BIT(5) +#define XGE_HAL_SERR_SOURCE_ANY (XGE_HAL_SERR_SOURCE_PIC | \ + XGE_HAL_SERR_SOURCE_TXDMA | \ + XGE_HAL_SERR_SOURCE_RXDMA | \ + XGE_HAL_SERR_SOURCE_MAC | \ + XGE_HAL_SERR_SOURCE_MC | \ + XGE_HAL_SERR_SOURCE_XGXS) + + u64 pci_info; +#define XGE_HAL_PCI_INFO vBIT(0xF,0,4) +#define XGE_HAL_PCI_32_BIT BIT(8) u8 unused0_1[0x160 - 0x128]; @@ -206,9 +200,9 @@ typedef struct { u64 msi_pending_reg; u64 misc_int_reg; -#define XGE_HAL_MISC_INT_REG_DP_ERR_INT BIT(0) -#define XGE_HAL_MISC_INT_REG_LINK_DOWN_INT BIT(1) -#define XGE_HAL_MISC_INT_REG_LINK_UP_INT BIT(2) +#define XGE_HAL_MISC_INT_REG_DP_ERR_INT BIT(0) +#define XGE_HAL_MISC_INT_REG_LINK_DOWN_INT BIT(1) +#define XGE_HAL_MISC_INT_REG_LINK_UP_INT BIT(2) u64 misc_int_mask; u64 misc_alarms; @@ -266,14 +260,14 @@ typedef struct { u64 scheduled_int_ctrl; #define XGE_HAL_SCHED_INT_CTRL_TIMER_EN BIT(0) #define XGE_HAL_SCHED_INT_CTRL_ONE_SHOT BIT(1) -#define XGE_HAL_SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6) -#define XGE_HAL_SCHED_INT_PERIOD(val) vBIT(val,32,32) -#define XGE_HAL_SCHED_INT_PERIOD_MASK 0xFFFFFFFF00000000ULL +#define XGE_HAL_SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6) +#define XGE_HAL_SCHED_INT_PERIOD(val) vBIT(val,32,32) +#define XGE_HAL_SCHED_INT_PERIOD_MASK 0xFFFFFFFF00000000ULL u64 txreqtimeout; -#define XGE_HAL_TXREQTO_VAL(val) vBIT(val,0,32) -#define XGE_HAL_TXREQTO_EN BIT(63) +#define XGE_HAL_TXREQTO_VAL(val) vBIT(val,0,32) +#define XGE_HAL_TXREQTO_EN BIT(63) u64 statsreqtimeout; #define XGE_HAL_STATREQTO_VAL(n) TBD @@ -285,25 +279,25 @@ typedef struct { u64 write_retry_acceleration; u64 xmsi_control; -#define XGE_HAL_XMSI_EN BIT(0) -#define XGE_HAL_XMSI_DIS_TINT_SERR BIT(1) -#define XGE_HAL_XMSI_BYTE_COUNT(val) vBIT(val,13,3) +#define XGE_HAL_XMSI_EN BIT(0) +#define XGE_HAL_XMSI_DIS_TINT_SERR BIT(1) +#define XGE_HAL_XMSI_BYTE_COUNT(val) vBIT(val,13,3) u64 xmsi_access; -#define XGE_HAL_XMSI_WR_RDN BIT(7) -#define XGE_HAL_XMSI_STROBE BIT(15) -#define XGE_HAL_XMSI_NO(val) vBIT(val,26,6) +#define XGE_HAL_XMSI_WR_RDN BIT(7) +#define XGE_HAL_XMSI_STROBE BIT(15) +#define XGE_HAL_XMSI_NO(val) vBIT(val,26,6) u64 xmsi_address; u64 xmsi_data; u64 rx_mat; -#define XGE_HAL_SET_RX_MAT(ring, msi) vBIT(msi, (8 * ring), 8) +#define XGE_HAL_SET_RX_MAT(ring, msi) vBIT(msi, (8 * ring), 8) u8 unused6[0x8]; u64 tx_mat[8]; -#define XGE_HAL_SET_TX_MAT(fifo, msi) vBIT(msi, (8 * fifo), 8) +#define XGE_HAL_SET_TX_MAT(fifo, msi) vBIT(msi, (8 * fifo), 8) u64 xmsi_mask_reg; @@ -314,64 +308,64 @@ typedef struct { #define XGE_HAL_STAT_CFG_ONE_SHOT_EN BIT(1) #define XGE_HAL_STAT_CFG_STAT_NS_EN BIT(8) #define XGE_HAL_STAT_CFG_STAT_RO BIT(9) -#define XGE_HAL_XENA_PER_SEC 0x208d5 -#define XGE_HAL_SET_UPDT_PERIOD(n) vBIT(n,32,32) +#define XGE_HAL_XENA_PER_SEC 0x208d5 +#define XGE_HAL_SET_UPDT_PERIOD(n) vBIT(n,32,32) u64 stat_addr; /* General Configuration */ u64 mdio_control; -#define XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(n) vBIT(n,0,16) -#define XGE_HAL_MDIO_CONTROL_MMD_DEV_ADDR(n) vBIT(n,19,5) -#define XGE_HAL_MDIO_CONTROL_MMD_PRT_ADDR(n) vBIT(n,27,5) -#define XGE_HAL_MDIO_CONTROL_MMD_DATA(n) vBIT(n,32,16) -#define XGE_HAL_MDIO_CONTROL_MMD_CTRL(n) vBIT(n,56,4) -#define XGE_HAL_MDIO_CONTROL_MMD_OP(n) vBIT(n,60,2) -#define XGE_HAL_MDIO_CONTROL_MMD_DATA_GET(n) ((n>>16)&0xFFFF) -#define XGE_HAL_MDIO_MMD_PMA_DEV_ADDR 0x01 -#define XGE_HAL_MDIO_DOM_REG_ADDR 0xA100 -#define XGE_HAL_MDIO_ALARM_FLAGS_ADDR 0xA070 -#define XGE_HAL_MDIO_WARN_FLAGS_ADDR 0xA074 -#define XGE_HAL_MDIO_CTRL_START 0xE -#define XGE_HAL_MDIO_OP_ADDRESS 0x0 -#define XGE_HAL_MDIO_OP_WRITE 0x1 -#define XGE_HAL_MDIO_OP_READ 0x3 -#define XGE_HAL_MDIO_OP_READ_POST_INCREMENT 0x2 -#define XGE_HAL_MDIO_ALARM_TEMPHIGH 0x0080 -#define XGE_HAL_MDIO_ALARM_TEMPLOW 0x0040 -#define XGE_HAL_MDIO_ALARM_BIASHIGH 0x0008 -#define XGE_HAL_MDIO_ALARM_BIASLOW 0x0004 -#define XGE_HAL_MDIO_ALARM_POUTPUTHIGH 0x0002 -#define XGE_HAL_MDIO_ALARM_POUTPUTLOW 0x0001 -#define XGE_HAL_MDIO_WARN_TEMPHIGH 0x0080 -#define XGE_HAL_MDIO_WARN_TEMPLOW 0x0040 -#define XGE_HAL_MDIO_WARN_BIASHIGH 0x0008 -#define XGE_HAL_MDIO_WARN_BIASLOW 0x0004 -#define XGE_HAL_MDIO_WARN_POUTPUTHIGH 0x0002 -#define XGE_HAL_MDIO_WARN_POUTPUTLOW 0x0001 +#define XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(n) vBIT(n,0,16) +#define XGE_HAL_MDIO_CONTROL_MMD_DEV_ADDR(n) vBIT(n,19,5) +#define XGE_HAL_MDIO_CONTROL_MMD_PRT_ADDR(n) vBIT(n,27,5) +#define XGE_HAL_MDIO_CONTROL_MMD_DATA(n) vBIT(n,32,16) +#define XGE_HAL_MDIO_CONTROL_MMD_CTRL(n) vBIT(n,56,4) +#define XGE_HAL_MDIO_CONTROL_MMD_OP(n) vBIT(n,60,2) +#define XGE_HAL_MDIO_CONTROL_MMD_DATA_GET(n) ((n>>16)&0xFFFF) +#define XGE_HAL_MDIO_MMD_PMA_DEV_ADDR 0x01 +#define XGE_HAL_MDIO_DOM_REG_ADDR 0xA100 +#define XGE_HAL_MDIO_ALARM_FLAGS_ADDR 0xA070 +#define XGE_HAL_MDIO_WARN_FLAGS_ADDR 0xA074 +#define XGE_HAL_MDIO_CTRL_START 0xE +#define XGE_HAL_MDIO_OP_ADDRESS 0x0 +#define XGE_HAL_MDIO_OP_WRITE 0x1 +#define XGE_HAL_MDIO_OP_READ 0x3 +#define XGE_HAL_MDIO_OP_READ_POST_INCREMENT 0x2 +#define XGE_HAL_MDIO_ALARM_TEMPHIGH 0x0080 +#define XGE_HAL_MDIO_ALARM_TEMPLOW 0x0040 +#define XGE_HAL_MDIO_ALARM_BIASHIGH 0x0008 +#define XGE_HAL_MDIO_ALARM_BIASLOW 0x0004 +#define XGE_HAL_MDIO_ALARM_POUTPUTHIGH 0x0002 +#define XGE_HAL_MDIO_ALARM_POUTPUTLOW 0x0001 +#define XGE_HAL_MDIO_WARN_TEMPHIGH 0x0080 +#define XGE_HAL_MDIO_WARN_TEMPLOW 0x0040 +#define XGE_HAL_MDIO_WARN_BIASHIGH 0x0008 +#define XGE_HAL_MDIO_WARN_BIASLOW 0x0004 +#define XGE_HAL_MDIO_WARN_POUTPUTHIGH 0x0002 +#define XGE_HAL_MDIO_WARN_POUTPUTLOW 0x0001 u64 dtx_control; u64 i2c_control; -#define XGE_HAL_I2C_CONTROL_DEV_ID(id) vBIT(id,1,3) -#define XGE_HAL_I2C_CONTROL_ADDR(addr) vBIT(addr,5,11) -#define XGE_HAL_I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2) -#define XGE_HAL_I2C_CONTROL_READ BIT(24) -#define XGE_HAL_I2C_CONTROL_NACK BIT(25) -#define XGE_HAL_I2C_CONTROL_CNTL_START vBIT(0xE,28,4) -#define XGE_HAL_I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4)) -#define XGE_HAL_I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF) -#define XGE_HAL_I2C_CONTROL_SET_DATA(val) vBIT(val,32,32) +#define XGE_HAL_I2C_CONTROL_DEV_ID(id) vBIT(id,1,3) +#define XGE_HAL_I2C_CONTROL_ADDR(addr) vBIT(addr,5,11) +#define XGE_HAL_I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2) +#define XGE_HAL_I2C_CONTROL_READ BIT(24) +#define XGE_HAL_I2C_CONTROL_NACK BIT(25) +#define XGE_HAL_I2C_CONTROL_CNTL_START vBIT(0xE,28,4) +#define XGE_HAL_I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4)) +#define XGE_HAL_I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF) +#define XGE_HAL_I2C_CONTROL_SET_DATA(val) vBIT(val,32,32) u64 beacon_control; u64 misc_control; -#define XGE_HAL_MISC_CONTROL_LINK_STABILITY_PERIOD(val) vBIT(val,29,3) +#define XGE_HAL_MISC_CONTROL_LINK_STABILITY_PERIOD(val) vBIT(val,29,3) #define XGE_HAL_MISC_CONTROL_EXT_REQ_EN BIT(1) -#define XGE_HAL_MISC_CONTROL_LINK_FAULT BIT(0) +#define XGE_HAL_MISC_CONTROL_LINK_FAULT BIT(0) u64 xfb_control; u64 gpio_control; -#define XGE_HAL_GPIO_CTRL_GPIO_0 BIT(8) +#define XGE_HAL_GPIO_CTRL_GPIO_0 BIT(8) u64 txfifo_dw_mask; u64 split_table_line_no; @@ -387,17 +381,17 @@ typedef struct { u64 txp_status; u64 txp_err_context; u64 spdm_bir_offset; -#define XGE_HAL_SPDM_PCI_BAR_NUM(spdm_bir_offset) \ - (u8)(spdm_bir_offset >> 61) +#define XGE_HAL_SPDM_PCI_BAR_NUM(spdm_bir_offset) \ + (u8)(spdm_bir_offset >> 61) #define XGE_HAL_SPDM_PCI_BAR_OFFSET(spdm_bir_offset) \ - (u32)((spdm_bir_offset >> 32) & 0x1FFFFFFF) + (u32)((spdm_bir_offset >> 32) & 0x1FFFFFFF) u64 spdm_overwrite; #define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_ENTRY(spdm_overwrite) \ - (u8)((spdm_overwrite >> 48) & 0xff) + (u8)((spdm_overwrite >> 48) & 0xff) #define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_DW(spdm_overwrite) \ - (u8)((spdm_overwrite >> 40) & 0x3) + (u8)((spdm_overwrite >> 40) & 0x3) #define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_LINE(spdm_overwrite) \ - (u8)((spdm_overwrite >> 32) & 0x7) + (u8)((spdm_overwrite >> 32) & 0x7) u64 cfg_addr_on_dperr; u64 pif_addr_on_dperr; u64 tags_in_use; @@ -409,9 +403,9 @@ typedef struct { u64 spdm_structure; #define XGE_HAL_SPDM_MAX_ENTRIES(spdm_structure) (u16)(spdm_structure >> 48) #define XGE_HAL_SPDM_INT_QW_PER_ENTRY(spdm_structure) \ - (u8)((spdm_structure >> 40) & 0xff) + (u8)((spdm_structure >> 40) & 0xff) #define XGE_HAL_SPDM_PCI_QW_PER_ENTRY(spdm_structure) \ - (u8)((spdm_structure >> 32) & 0xff) + (u8)((spdm_structure >> 32) & 0xff) u64 txdw_ptr_cnt_0; u64 txdw_ptr_cnt_1; @@ -435,73 +429,73 @@ typedef struct { /* TxDMA registers */ u64 txdma_int_status; u64 txdma_int_mask; -#define XGE_HAL_TXDMA_PFC_INT BIT(0) -#define XGE_HAL_TXDMA_TDA_INT BIT(1) -#define XGE_HAL_TXDMA_PCC_INT BIT(2) -#define XGE_HAL_TXDMA_TTI_INT BIT(3) -#define XGE_HAL_TXDMA_LSO_INT BIT(4) -#define XGE_HAL_TXDMA_TPA_INT BIT(5) -#define XGE_HAL_TXDMA_SM_INT BIT(6) +#define XGE_HAL_TXDMA_PFC_INT BIT(0) +#define XGE_HAL_TXDMA_TDA_INT BIT(1) +#define XGE_HAL_TXDMA_PCC_INT BIT(2) +#define XGE_HAL_TXDMA_TTI_INT BIT(3) +#define XGE_HAL_TXDMA_LSO_INT BIT(4) +#define XGE_HAL_TXDMA_TPA_INT BIT(5) +#define XGE_HAL_TXDMA_SM_INT BIT(6) u64 pfc_err_reg; -#define XGE_HAL_PFC_ECC_SG_ERR BIT(7) -#define XGE_HAL_PFC_ECC_DB_ERR BIT(15) -#define XGE_HAL_PFC_SM_ERR_ALARM BIT(23) -#define XGE_HAL_PFC_MISC_0_ERR BIT(31) -#define XGE_HAL_PFC_MISC_1_ERR BIT(32) -#define XGE_HAL_PFC_PCIX_ERR BIT(39) +#define XGE_HAL_PFC_ECC_SG_ERR BIT(7) +#define XGE_HAL_PFC_ECC_DB_ERR BIT(15) +#define XGE_HAL_PFC_SM_ERR_ALARM BIT(23) +#define XGE_HAL_PFC_MISC_0_ERR BIT(31) +#define XGE_HAL_PFC_MISC_1_ERR BIT(32) +#define XGE_HAL_PFC_PCIX_ERR BIT(39) u64 pfc_err_mask; u64 pfc_err_alarm; u64 tda_err_reg; -#define XGE_HAL_TDA_Fn_ECC_SG_ERR vBIT(0xff,0,8) -#define XGE_HAL_TDA_Fn_ECC_DB_ERR vBIT(0xff,8,8) -#define XGE_HAL_TDA_SM0_ERR_ALARM BIT(22) -#define XGE_HAL_TDA_SM1_ERR_ALARM BIT(23) -#define XGE_HAL_TDA_PCIX_ERR BIT(39) +#define XGE_HAL_TDA_Fn_ECC_SG_ERR vBIT(0xff,0,8) +#define XGE_HAL_TDA_Fn_ECC_DB_ERR vBIT(0xff,8,8) +#define XGE_HAL_TDA_SM0_ERR_ALARM BIT(22) +#define XGE_HAL_TDA_SM1_ERR_ALARM BIT(23) +#define XGE_HAL_TDA_PCIX_ERR BIT(39) u64 tda_err_mask; u64 tda_err_alarm; u64 pcc_err_reg; -#define XGE_HAL_PCC_FB_ECC_SG_ERR vBIT(0xFF,0,8) -#define XGE_HAL_PCC_TXB_ECC_SG_ERR vBIT(0xFF,8,8) -#define XGE_HAL_PCC_FB_ECC_DB_ERR vBIT(0xFF,16, 8) -#define XGE_HAL_PCC_TXB_ECC_DB_ERR vBIT(0xff,24,8) -#define XGE_HAL_PCC_SM_ERR_ALARM vBIT(0xff,32,8) -#define XGE_HAL_PCC_WR_ERR_ALARM vBIT(0xff,40,8) -#define XGE_HAL_PCC_N_SERR vBIT(0xff,48,8) -#define XGE_HAL_PCC_ENABLE_FOUR vBIT(0x0F,0,8) -#define XGE_HAL_PCC_6_COF_OV_ERR BIT(56) -#define XGE_HAL_PCC_7_COF_OV_ERR BIT(57) -#define XGE_HAL_PCC_6_LSO_OV_ERR BIT(58) -#define XGE_HAL_PCC_7_LSO_OV_ERR BIT(59) +#define XGE_HAL_PCC_FB_ECC_SG_ERR vBIT(0xFF,0,8) +#define XGE_HAL_PCC_TXB_ECC_SG_ERR vBIT(0xFF,8,8) +#define XGE_HAL_PCC_FB_ECC_DB_ERR vBIT(0xFF,16, 8) +#define XGE_HAL_PCC_TXB_ECC_DB_ERR vBIT(0xff,24,8) +#define XGE_HAL_PCC_SM_ERR_ALARM vBIT(0xff,32,8) +#define XGE_HAL_PCC_WR_ERR_ALARM vBIT(0xff,40,8) +#define XGE_HAL_PCC_N_SERR vBIT(0xff,48,8) +#define XGE_HAL_PCC_ENABLE_FOUR vBIT(0x0F,0,8) +#define XGE_HAL_PCC_6_COF_OV_ERR BIT(56) +#define XGE_HAL_PCC_7_COF_OV_ERR BIT(57) +#define XGE_HAL_PCC_6_LSO_OV_ERR BIT(58) +#define XGE_HAL_PCC_7_LSO_OV_ERR BIT(59) u64 pcc_err_mask; u64 pcc_err_alarm; u64 tti_err_reg; -#define XGE_HAL_TTI_ECC_SG_ERR BIT(7) -#define XGE_HAL_TTI_ECC_DB_ERR BIT(15) -#define XGE_HAL_TTI_SM_ERR_ALARM BIT(23) +#define XGE_HAL_TTI_ECC_SG_ERR BIT(7) +#define XGE_HAL_TTI_ECC_DB_ERR BIT(15) +#define XGE_HAL_TTI_SM_ERR_ALARM BIT(23) u64 tti_err_mask; u64 tti_err_alarm; u64 lso_err_reg; -#define XGE_HAL_LSO6_SEND_OFLOW BIT(12) -#define XGE_HAL_LSO7_SEND_OFLOW BIT(13) -#define XGE_HAL_LSO6_ABORT BIT(14) -#define XGE_HAL_LSO7_ABORT BIT(15) -#define XGE_HAL_LSO6_SM_ERR_ALARM BIT(22) -#define XGE_HAL_LSO7_SM_ERR_ALARM BIT(23) +#define XGE_HAL_LSO6_SEND_OFLOW BIT(12) +#define XGE_HAL_LSO7_SEND_OFLOW BIT(13) +#define XGE_HAL_LSO6_ABORT BIT(14) +#define XGE_HAL_LSO7_ABORT BIT(15) +#define XGE_HAL_LSO6_SM_ERR_ALARM BIT(22) +#define XGE_HAL_LSO7_SM_ERR_ALARM BIT(23) u64 lso_err_mask; u64 lso_err_alarm; u64 tpa_err_reg; -#define XGE_HAL_TPA_TX_FRM_DROP BIT(7) -#define XGE_HAL_TPA_SM_ERR_ALARM BIT(23) +#define XGE_HAL_TPA_TX_FRM_DROP BIT(7) +#define XGE_HAL_TPA_SM_ERR_ALARM BIT(23) u64 tpa_err_mask; u64 tpa_err_alarm; u64 sm_err_reg; -#define XGE_HAL_SM_SM_ERR_ALARM BIT(15) +#define XGE_HAL_SM_SM_ERR_ALARM BIT(15) u64 sm_err_mask; u64 sm_err_alarm; @@ -512,7 +506,7 @@ typedef struct { /* Tx FIFO controller */ #define XGE_HAL_X_MAX_FIFOS 8 -#define XGE_HAL_X_FIFO_MAX_LEN 0x1FFF /*8191 */ +#define XGE_HAL_X_FIFO_MAX_LEN 0x1FFF /*8191 */ u64 tx_fifo_partition_0; #define XGE_HAL_TX_FIFO_PARTITION_EN BIT(0) #define XGE_HAL_TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3) @@ -538,14 +532,14 @@ typedef struct { #define XGE_HAL_TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3) #define XGE_HAL_TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13) -#define XGE_HAL_TX_FIFO_PARTITION_PRI_0 0 /* highest */ +#define XGE_HAL_TX_FIFO_PARTITION_PRI_0 0 /* highest */ #define XGE_HAL_TX_FIFO_PARTITION_PRI_1 1 #define XGE_HAL_TX_FIFO_PARTITION_PRI_2 2 #define XGE_HAL_TX_FIFO_PARTITION_PRI_3 3 #define XGE_HAL_TX_FIFO_PARTITION_PRI_4 4 #define XGE_HAL_TX_FIFO_PARTITION_PRI_5 5 #define XGE_HAL_TX_FIFO_PARTITION_PRI_6 6 -#define XGE_HAL_TX_FIFO_PARTITION_PRI_7 7 /* lowest */ +#define XGE_HAL_TX_FIFO_PARTITION_PRI_7 7 /* lowest */ u64 tx_w_round_robin_0; u64 tx_w_round_robin_1; @@ -579,7 +573,7 @@ typedef struct { #define XGE_HAL_TX_PA_CFG_IGNORE_FRM_ERR BIT(1) #define XGE_HAL_TX_PA_CFG_IGNORE_SNAP_OUI BIT(2) #define XGE_HAL_TX_PA_CFG_IGNORE_LLC_CTRL BIT(3) -#define XGE_HAL_TX_PA_CFG_IGNORE_L2_ERR BIT(6) +#define XGE_HAL_TX_PA_CFG_IGNORE_L2_ERR BIT(6) /* Recent add, used only debug purposes. */ u64 pcc_enable; @@ -612,52 +606,52 @@ typedef struct { #define XGE_HAL_RXDMA_INT_RTI_INT_M BIT(3) u64 rda_err_reg; -#define XGE_HAL_RDA_RXDn_ECC_SG_ERR vBIT(0xFF,0,8) -#define XGE_HAL_RDA_RXDn_ECC_DB_ERR vBIT(0xFF,8,8) -#define XGE_HAL_RDA_FRM_ECC_SG_ERR BIT(23) -#define XGE_HAL_RDA_FRM_ECC_DB_N_AERR BIT(31) -#define XGE_HAL_RDA_SM1_ERR_ALARM BIT(38) -#define XGE_HAL_RDA_SM0_ERR_ALARM BIT(39) -#define XGE_HAL_RDA_MISC_ERR BIT(47) -#define XGE_HAL_RDA_PCIX_ERR BIT(55) -#define XGE_HAL_RDA_RXD_ECC_DB_SERR BIT(63) +#define XGE_HAL_RDA_RXDn_ECC_SG_ERR vBIT(0xFF,0,8) +#define XGE_HAL_RDA_RXDn_ECC_DB_ERR vBIT(0xFF,8,8) +#define XGE_HAL_RDA_FRM_ECC_SG_ERR BIT(23) +#define XGE_HAL_RDA_FRM_ECC_DB_N_AERR BIT(31) +#define XGE_HAL_RDA_SM1_ERR_ALARM BIT(38) +#define XGE_HAL_RDA_SM0_ERR_ALARM BIT(39) +#define XGE_HAL_RDA_MISC_ERR BIT(47) +#define XGE_HAL_RDA_PCIX_ERR BIT(55) +#define XGE_HAL_RDA_RXD_ECC_DB_SERR BIT(63) u64 rda_err_mask; u64 rda_err_alarm; u64 rc_err_reg; -#define XGE_HAL_RC_PRCn_ECC_SG_ERR vBIT(0xFF,0,8) -#define XGE_HAL_RC_PRCn_ECC_DB_ERR vBIT(0xFF,8,8) -#define XGE_HAL_RC_FTC_ECC_SG_ERR BIT(23) -#define XGE_HAL_RC_FTC_ECC_DB_ERR BIT(31) -#define XGE_HAL_RC_PRCn_SM_ERR_ALARM vBIT(0xFF,32,8) -#define XGE_HAL_RC_FTC_SM_ERR_ALARM BIT(47) -#define XGE_HAL_RC_RDA_FAIL_WR_Rn vBIT(0xFF,48,8) +#define XGE_HAL_RC_PRCn_ECC_SG_ERR vBIT(0xFF,0,8) +#define XGE_HAL_RC_PRCn_ECC_DB_ERR vBIT(0xFF,8,8) +#define XGE_HAL_RC_FTC_ECC_SG_ERR BIT(23) +#define XGE_HAL_RC_FTC_ECC_DB_ERR BIT(31) +#define XGE_HAL_RC_PRCn_SM_ERR_ALARM vBIT(0xFF,32,8) +#define XGE_HAL_RC_FTC_SM_ERR_ALARM BIT(47) +#define XGE_HAL_RC_RDA_FAIL_WR_Rn vBIT(0xFF,48,8) u64 rc_err_mask; u64 rc_err_alarm; u64 prc_pcix_err_reg; -#define XGE_HAL_PRC_PCI_AB_RD_Rn vBIT(0xFF,0,8) -#define XGE_HAL_PRC_PCI_DP_RD_Rn vBIT(0xFF,8,8) -#define XGE_HAL_PRC_PCI_AB_WR_Rn vBIT(0xFF,16,8) -#define XGE_HAL_PRC_PCI_DP_WR_Rn vBIT(0xFF,24,8) -#define XGE_HAL_PRC_PCI_AB_F_WR_Rn vBIT(0xFF,32,8) -#define XGE_HAL_PRC_PCI_DP_F_WR_Rn vBIT(0xFF,40,8) +#define XGE_HAL_PRC_PCI_AB_RD_Rn vBIT(0xFF,0,8) +#define XGE_HAL_PRC_PCI_DP_RD_Rn vBIT(0xFF,8,8) +#define XGE_HAL_PRC_PCI_AB_WR_Rn vBIT(0xFF,16,8) +#define XGE_HAL_PRC_PCI_DP_WR_Rn vBIT(0xFF,24,8) +#define XGE_HAL_PRC_PCI_AB_F_WR_Rn vBIT(0xFF,32,8) +#define XGE_HAL_PRC_PCI_DP_F_WR_Rn vBIT(0xFF,40,8) u64 prc_pcix_err_mask; u64 prc_pcix_err_alarm; u64 rpa_err_reg; -#define XGE_HAL_RPA_ECC_SG_ERR BIT(7) -#define XGE_HAL_RPA_ECC_DB_ERR BIT(15) -#define XGE_HAL_RPA_FLUSH_REQUEST BIT(22) -#define XGE_HAL_RPA_SM_ERR_ALARM BIT(23) -#define XGE_HAL_RPA_CREDIT_ERR BIT(31) +#define XGE_HAL_RPA_ECC_SG_ERR BIT(7) +#define XGE_HAL_RPA_ECC_DB_ERR BIT(15) +#define XGE_HAL_RPA_FLUSH_REQUEST BIT(22) +#define XGE_HAL_RPA_SM_ERR_ALARM BIT(23) +#define XGE_HAL_RPA_CREDIT_ERR BIT(31) u64 rpa_err_mask; u64 rpa_err_alarm; u64 rti_err_reg; -#define XGE_HAL_RTI_ECC_SG_ERR BIT(7) -#define XGE_HAL_RTI_ECC_DB_ERR BIT(15) -#define XGE_HAL_RTI_SM_ERR_ALARM BIT(23) +#define XGE_HAL_RTI_ECC_SG_ERR BIT(7) +#define XGE_HAL_RTI_ECC_DB_ERR BIT(15) +#define XGE_HAL_RTI_SM_ERR_ALARM BIT(23) u64 rti_err_mask; u64 rti_err_alarm; @@ -674,14 +668,14 @@ typedef struct { #define XGE_HAL_RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3) #define XGE_HAL_RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3) -#define XGE_HAL_RX_QUEUE_PRI_0 0 /* highest */ +#define XGE_HAL_RX_QUEUE_PRI_0 0 /* highest */ #define XGE_HAL_RX_QUEUE_PRI_1 1 #define XGE_HAL_RX_QUEUE_PRI_2 2 #define XGE_HAL_RX_QUEUE_PRI_3 3 #define XGE_HAL_RX_QUEUE_PRI_4 4 #define XGE_HAL_RX_QUEUE_PRI_5 5 #define XGE_HAL_RX_QUEUE_PRI_6 6 -#define XGE_HAL_RX_QUEUE_PRI_7 7 /* lowest */ +#define XGE_HAL_RX_QUEUE_PRI_7 7 /* lowest */ u64 rx_w_round_robin_0; u64 rx_w_round_robin_1; @@ -771,21 +765,21 @@ typedef struct { #define XGE_HAL_MAC_INT_STATUS_RMAC_INT BIT(1) u64 mac_tmac_err_reg; -#define XGE_HAL_TMAC_ECC_DB_ERR BIT(15) -#define XGE_HAL_TMAC_TX_BUF_OVRN BIT(23) -#define XGE_HAL_TMAC_TX_CRI_ERR BIT(31) -#define XGE_HAL_TMAC_TX_SM_ERR BIT(39) +#define XGE_HAL_TMAC_ECC_DB_ERR BIT(15) +#define XGE_HAL_TMAC_TX_BUF_OVRN BIT(23) +#define XGE_HAL_TMAC_TX_CRI_ERR BIT(31) +#define XGE_HAL_TMAC_TX_SM_ERR BIT(39) u64 mac_tmac_err_mask; u64 mac_tmac_err_alarm; u64 mac_rmac_err_reg; -#define XGE_HAL_RMAC_RX_BUFF_OVRN BIT(0) -#define XGE_HAL_RMAC_RTH_SPDM_ECC_SG_ERR BIT(0) -#define XGE_HAL_RMAC_RTS_ECC_DB_ERR BIT(0) -#define XGE_HAL_RMAC_ECC_DB_ERR BIT(0) -#define XGE_HAL_RMAC_RTH_SPDM_ECC_DB_ERR BIT(0) -#define XGE_HAL_RMAC_LINK_STATE_CHANGE_INT BIT(0) -#define XGE_HAL_RMAC_RX_SM_ERR BIT(39) +#define XGE_HAL_RMAC_RX_BUFF_OVRN BIT(0) +#define XGE_HAL_RMAC_RTH_SPDM_ECC_SG_ERR BIT(0) +#define XGE_HAL_RMAC_RTS_ECC_DB_ERR BIT(0) +#define XGE_HAL_RMAC_ECC_DB_ERR BIT(0) +#define XGE_HAL_RMAC_RTH_SPDM_ECC_DB_ERR BIT(0) +#define XGE_HAL_RMAC_LINK_STATE_CHANGE_INT BIT(0) +#define XGE_HAL_RMAC_RX_SM_ERR BIT(39) u64 mac_rmac_err_mask; u64 mac_rmac_err_alarm; @@ -846,7 +840,7 @@ typedef struct { u8 unused16[0x8]; /* - u64 rmac_addr_cfg; + u64 rmac_addr_cfg; #define XGE_HAL_RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n) #define XGE_HAL_RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n) #define XGE_HAL_RMAC_ADDR_BCAST_EN vBIT(0)_48 @@ -874,12 +868,12 @@ typedef struct { #define XGE_HAL_MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4) #define XGE_HAL_MAC_LINK_UTIL_DISABLE (XGE_HAL_MAC_TX_LINK_UTIL_DISABLE | \ - XGE_HAL_MAC_RX_LINK_UTIL_DISABLE) + XGE_HAL_MAC_RX_LINK_UTIL_DISABLE) u64 rmac_invalid_ipg; /* rx traffic steering */ -#define XGE_HAL_MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14) +#define XGE_HAL_MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14) u64 rts_frm_len_n[8]; u64 rts_qos_steering; @@ -891,12 +885,12 @@ typedef struct { u64 rts_q_alternates; u64 rts_default_q; -#define XGE_HAL_RTS_DEFAULT_Q(n) vBIT(n,5,3) +#define XGE_HAL_RTS_DEFAULT_Q(n) vBIT(n,5,3) u64 rts_ctrl; #define XGE_HAL_RTS_CTRL_IGNORE_SNAP_OUI BIT(2) #define XGE_HAL_RTS_CTRL_IGNORE_LLC_CTRL BIT(3) -#define XGE_HAL_RTS_CTRL_ENHANCED_MODE BIT(7) +#define XGE_HAL_RTS_CTRL_ENHANCED_MODE BIT(7) u64 rts_pn_cam_ctrl; #define XGE_HAL_RTS_PN_CAM_CTRL_WE BIT(7) @@ -1024,7 +1018,7 @@ typedef struct { u8 unused17_2[0x700 - 0x5F0]; u64 mac_debug_ctrl; -#define XGE_HAL_MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL +#define XGE_HAL_MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL u8 unused18[0x2800 - 0x2708]; @@ -1073,8 +1067,8 @@ typedef struct { #define XGE_HAL_RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8) u64 mc_rldram_mrs; -#define XGE_HAL_MC_RLDRAM_QUEUE_SIZE_ENABLE BIT(39) -#define XGE_HAL_MC_RLDRAM_MRS_ENABLE BIT(47) +#define XGE_HAL_MC_RLDRAM_QUEUE_SIZE_ENABLE BIT(39) +#define XGE_HAL_MC_RLDRAM_MRS_ENABLE BIT(47) u64 mc_rldram_interleave; @@ -1087,11 +1081,11 @@ typedef struct { u64 mc_rldram_ref_per; u8 unused21[0x220 - 0x208]; u64 mc_rldram_test_ctrl; -#define XGE_HAL_MC_RLDRAM_TEST_MODE BIT(47) -#define XGE_HAL_MC_RLDRAM_TEST_WRITE BIT(7) -#define XGE_HAL_MC_RLDRAM_TEST_GO BIT(15) -#define XGE_HAL_MC_RLDRAM_TEST_DONE BIT(23) -#define XGE_HAL_MC_RLDRAM_TEST_PASS BIT(31) +#define XGE_HAL_MC_RLDRAM_TEST_MODE BIT(47) +#define XGE_HAL_MC_RLDRAM_TEST_WRITE BIT(7) +#define XGE_HAL_MC_RLDRAM_TEST_GO BIT(15) +#define XGE_HAL_MC_RLDRAM_TEST_DONE BIT(23) +#define XGE_HAL_MC_RLDRAM_TEST_PASS BIT(31) u8 unused22[0x240 - 0x228]; u64 mc_rldram_test_add; @@ -1147,16 +1141,16 @@ typedef struct { #define XGE_HAL_XGXS_INT_MASK_RXGXS BIT(1) u64 xgxs_txgxs_err_reg; -#define XGE_HAL_TXGXS_ECC_SG_ERR BIT(7) -#define XGE_HAL_TXGXS_ECC_DB_ERR BIT(15) -#define XGE_HAL_TXGXS_ESTORE_UFLOW BIT(31) -#define XGE_HAL_TXGXS_TX_SM_ERR BIT(39) +#define XGE_HAL_TXGXS_ECC_SG_ERR BIT(7) +#define XGE_HAL_TXGXS_ECC_DB_ERR BIT(15) +#define XGE_HAL_TXGXS_ESTORE_UFLOW BIT(31) +#define XGE_HAL_TXGXS_TX_SM_ERR BIT(39) u64 xgxs_txgxs_err_mask; u64 xgxs_txgxs_err_alarm; u64 xgxs_rxgxs_err_reg; -#define XGE_HAL_RXGXS_ESTORE_OFLOW BIT(7) -#define XGE_HAL_RXGXS_RX_SM_ERR BIT(39) +#define XGE_HAL_RXGXS_ESTORE_OFLOW BIT(7) +#define XGE_HAL_RXGXS_RX_SM_ERR BIT(39) u64 xgxs_rxgxs_err_mask; u64 xgxs_rxgxs_err_alarm; @@ -1185,193 +1179,195 @@ typedef struct { /* Using this strcture to calculate offsets */ typedef struct xge_hal_pci_config_le_t { - u16 vendor_id; // 0x00 - u16 device_id; // 0x02 + u16 vendor_id; // 0x00 + u16 device_id; // 0x02 - u16 command; // 0x04 - u16 status; // 0x06 + u16 command; // 0x04 + u16 status; // 0x06 - u8 revision; // 0x08 - u8 pciClass[3]; // 0x09 + u8 revision; // 0x08 + u8 pciClass[3]; // 0x09 - u8 cache_line_size; // 0x0c - u8 latency_timer; // 0x0d - u8 header_type; // 0x0e - u8 bist; // 0x0f + u8 cache_line_size; // 0x0c + u8 latency_timer; // 0x0d + u8 header_type; // 0x0e + u8 bist; // 0x0f - u32 base_addr0_lo; // 0x10 - u32 base_addr0_hi; // 0x14 + u32 base_addr0_lo; // 0x10 + u32 base_addr0_hi; // 0x14 - u32 base_addr1_lo; // 0x18 - u32 base_addr1_hi; // 0x1C + u32 base_addr1_lo; // 0x18 + u32 base_addr1_hi; // 0x1C - u32 not_Implemented1; // 0x20 - u32 not_Implemented2; // 0x24 + u32 not_Implemented1; // 0x20 + u32 not_Implemented2; // 0x24 - u32 cardbus_cis_pointer; // 0x28 + u32 cardbus_cis_pointer; // 0x28 - u16 subsystem_vendor_id; // 0x2c - u16 subsystem_id; // 0x2e + u16 subsystem_vendor_id; // 0x2c + u16 subsystem_id; // 0x2e - u32 rom_base; // 0x30 - u8 capabilities_pointer; // 0x34 - u8 rsvd_35[3]; // 0x35 - u32 rsvd_38; // 0x38 + u32 rom_base; // 0x30 + u8 capabilities_pointer; // 0x34 + u8 rsvd_35[3]; // 0x35 + u32 rsvd_38; // 0x38 - u8 interrupt_line; // 0x3c - u8 interrupt_pin; // 0x3d - u8 min_grant; // 0x3e - u8 max_latency; // 0x3f + u8 interrupt_line; // 0x3c + u8 interrupt_pin; // 0x3d + u8 min_grant; // 0x3e + u8 max_latency; // 0x3f - u8 msi_cap_id; // 0x40 - u8 msi_next_ptr; // 0x41 - u16 msi_control; // 0x42 - u32 msi_lower_address; // 0x44 - u32 msi_higher_address; // 0x48 - u16 msi_data; // 0x4c - u16 msi_unused; // 0x4e + u8 msi_cap_id; // 0x40 + u8 msi_next_ptr; // 0x41 + u16 msi_control; // 0x42 + u32 msi_lower_address; // 0x44 + u32 msi_higher_address; // 0x48 + u16 msi_data; // 0x4c + u16 msi_unused; // 0x4e - u8 vpd_cap_id; // 0x50 - u8 vpd_next_cap; // 0x51 - u16 vpd_addr; // 0x52 - u32 vpd_data; // 0x54 + u8 vpd_cap_id; // 0x50 + u8 vpd_next_cap; // 0x51 + u16 vpd_addr; // 0x52 + u32 vpd_data; // 0x54 - u8 rsvd_b0[8]; // 0x58 + u8 rsvd_b0[8]; // 0x58 - u8 pcix_cap; // 0x60 - u8 pcix_next_cap; // 0x61 - u16 pcix_command; // 0x62 + u8 pcix_cap; // 0x60 + u8 pcix_next_cap; // 0x61 + u16 pcix_command; // 0x62 - u32 pcix_status; // 0x64 + u32 pcix_status; // 0x64 - u8 rsvd_b1[XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE-0x68]; + u8 rsvd_b1[XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE-0x68]; } xge_hal_pci_config_le_t; // 0x100 typedef struct xge_hal_pci_config_t { #ifdef XGE_OS_HOST_BIG_ENDIAN - u16 device_id; // 0x02 - u16 vendor_id; // 0x00 + u16 device_id; // 0x02 + u16 vendor_id; // 0x00 - u16 status; // 0x06 - u16 command; // 0x04 + u16 status; // 0x06 + u16 command; // 0x04 - u8 pciClass[3]; // 0x09 - u8 revision; // 0x08 + u8 pciClass[3]; // 0x09 + u8 revision; // 0x08 - u8 bist; // 0x0f - u8 header_type; // 0x0e - u8 latency_timer; // 0x0d - u8 cache_line_size; // 0x0c + u8 bist; // 0x0f + u8 header_type; // 0x0e + u8 latency_timer; // 0x0d + u8 cache_line_size; // 0x0c - u32 base_addr0_lo; // 0x10 - u32 base_addr0_hi; // 0x14 + u32 base_addr0_lo; // 0x10 + u32 base_addr0_hi; // 0x14 - u32 base_addr1_lo; // 0x18 - u32 base_addr1_hi; // 0x1C + u32 base_addr1_lo; // 0x18 + u32 base_addr1_hi; // 0x1C - u32 not_Implemented1; // 0x20 - u32 not_Implemented2; // 0x24 + u32 not_Implemented1; // 0x20 + u32 not_Implemented2; // 0x24 - u32 cardbus_cis_pointer; // 0x28 + u32 cardbus_cis_pointer; // 0x28 - u16 subsystem_id; // 0x2e - u16 subsystem_vendor_id; // 0x2c + u16 subsystem_id; // 0x2e + u16 subsystem_vendor_id; // 0x2c - u32 rom_base; // 0x30 - u8 rsvd_35[3]; // 0x35 - u8 capabilities_pointer; // 0x34 - u32 rsvd_38; // 0x38 + u32 rom_base; // 0x30 + u8 rsvd_35[3]; // 0x35 + u8 capabilities_pointer; // 0x34 + u32 rsvd_38; // 0x38 - u8 max_latency; // 0x3f - u8 min_grant; // 0x3e - u8 interrupt_pin; // 0x3d - u8 interrupt_line; // 0x3c + u8 max_latency; // 0x3f + u8 min_grant; // 0x3e + u8 interrupt_pin; // 0x3d + u8 interrupt_line; // 0x3c - u16 msi_control; // 0x42 - u8 msi_next_ptr; // 0x41 - u8 msi_cap_id; // 0x40 - u32 msi_lower_address; // 0x44 - u32 msi_higher_address; // 0x48 - u16 msi_unused; // 0x4e - u16 msi_data; // 0x4c + u16 msi_control; // 0x42 + u8 msi_next_ptr; // 0x41 + u8 msi_cap_id; // 0x40 + u32 msi_lower_address; // 0x44 + u32 msi_higher_address; // 0x48 + u16 msi_unused; // 0x4e + u16 msi_data; // 0x4c - u16 vpd_addr; // 0x52 - u8 vpd_next_cap; // 0x51 - u8 vpd_cap_id; // 0x50 - u32 vpd_data; // 0x54 + u16 vpd_addr; // 0x52 + u8 vpd_next_cap; // 0x51 + u8 vpd_cap_id; // 0x50 + u32 vpd_data; // 0x54 - u8 rsvd_b0[8]; // 0x58 + u8 rsvd_b0[8]; // 0x58 - u16 pcix_command; // 0x62 - u8 pcix_next_cap; // 0x61 - u8 pcix_cap; // 0x60 + u16 pcix_command; // 0x62 + u8 pcix_next_cap; // 0x61 + u8 pcix_cap; // 0x60 - u32 pcix_status; // 0x64 + u32 pcix_status; // 0x64 #else - u16 vendor_id; // 0x00 - u16 device_id; // 0x02 + u16 vendor_id; // 0x00 + u16 device_id; // 0x02 - u16 command; // 0x04 - u16 status; // 0x06 + u16 command; // 0x04 + u16 status; // 0x06 - u8 revision; // 0x08 - u8 pciClass[3]; // 0x09 + u8 revision; // 0x08 + u8 pciClass[3]; // 0x09 - u8 cache_line_size; // 0x0c - u8 latency_timer; // 0x0d - u8 header_type; // 0x0e - u8 bist; // 0x0f + u8 cache_line_size; // 0x0c + u8 latency_timer; // 0x0d + u8 header_type; // 0x0e + u8 bist; // 0x0f - u32 base_addr0_lo; // 0x10 - u32 base_addr0_hi; // 0x14 + u32 base_addr0_lo; // 0x10 + u32 base_addr0_hi; // 0x14 - u32 base_addr1_lo; // 0x18 - u32 base_addr1_hi; // 0x1C + u32 base_addr1_lo; // 0x18 + u32 base_addr1_hi; // 0x1C - u32 not_Implemented1; // 0x20 - u32 not_Implemented2; // 0x24 + u32 not_Implemented1; // 0x20 + u32 not_Implemented2; // 0x24 - u32 cardbus_cis_pointer; // 0x28 + u32 cardbus_cis_pointer; // 0x28 - u16 subsystem_vendor_id; // 0x2c - u16 subsystem_id; // 0x2e + u16 subsystem_vendor_id; // 0x2c + u16 subsystem_id; // 0x2e - u32 rom_base; // 0x30 - u8 capabilities_pointer; // 0x34 - u8 rsvd_35[3]; // 0x35 - u32 rsvd_38; // 0x38 + u32 rom_base; // 0x30 + u8 capabilities_pointer; // 0x34 + u8 rsvd_35[3]; // 0x35 + u32 rsvd_38; // 0x38 - u8 interrupt_line; // 0x3c - u8 interrupt_pin; // 0x3d - u8 min_grant; // 0x3e - u8 max_latency; // 0x3f + u8 interrupt_line; // 0x3c + u8 interrupt_pin; // 0x3d + u8 min_grant; // 0x3e + u8 max_latency; // 0x3f - u8 msi_cap_id; // 0x40 - u8 msi_next_ptr; // 0x41 - u16 msi_control; // 0x42 - u32 msi_lower_address; // 0x44 - u32 msi_higher_address; // 0x48 - u16 msi_data; // 0x4c - u16 msi_unused; // 0x4e + u8 msi_cap_id; // 0x40 + u8 msi_next_ptr; // 0x41 + u16 msi_control; // 0x42 + u32 msi_lower_address; // 0x44 + u32 msi_higher_address; // 0x48 + u16 msi_data; // 0x4c + u16 msi_unused; // 0x4e - u8 vpd_cap_id; // 0x50 - u8 vpd_next_cap; // 0x51 - u16 vpd_addr; // 0x52 - u32 vpd_data; // 0x54 + u8 vpd_cap_id; // 0x50 + u8 vpd_next_cap; // 0x51 + u16 vpd_addr; // 0x52 + u32 vpd_data; // 0x54 - u8 rsvd_b0[8]; // 0x58 + u8 rsvd_b0[8]; // 0x58 - u8 pcix_cap; // 0x60 - u8 pcix_next_cap; // 0x61 - u16 pcix_command; // 0x62 + u8 pcix_cap; // 0x60 + u8 pcix_next_cap; // 0x61 + u16 pcix_command; // 0x62 - u32 pcix_status; // 0x64 + u32 pcix_status; // 0x64 #endif - u8 rsvd_b1[XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE-0x68]; + u8 rsvd_b1[XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE-0x68]; } xge_hal_pci_config_t; // 0x100 -#define XGE_HAL_REG_SPACE sizeof(xge_hal_pci_bar0_t) -#define XGE_HAL_EEPROM_SIZE (0x01 << 11) +#define XGE_HAL_REG_SPACE sizeof(xge_hal_pci_bar0_t) +#define XGE_HAL_EEPROM_SIZE (0x01 << 11) + +__EXTERN_END_DECLS #endif /* XGE_HAL_REGS_H */ diff --git a/sys/dev/nxge/include/xgehal-ring.h b/sys/dev/nxge/include/xgehal-ring.h index c3efdf0..0e5b7e6 100644 --- a/sys/dev/nxge/include/xgehal-ring.h +++ b/sys/dev/nxge/include/xgehal-ring.h @@ -26,14 +26,6 @@ * $FreeBSD$ */ -/* - * FileName : xgehal-ring.h - * - * Description: HAL Rx ring object functionality - * - * Created: 19 May 2004 - */ - #ifndef XGE_HAL_RING_H #define XGE_HAL_RING_H @@ -44,52 +36,52 @@ __EXTERN_BEGIN_DECLS /* HW ring configuration */ -#define XGE_HAL_RING_RXDBLOCK_SIZE 0x1000 +#define XGE_HAL_RING_RXDBLOCK_SIZE 0x1000 -#define XGE_HAL_RXD_T_CODE_OK 0x0 -#define XGE_HAL_RXD_T_CODE_PARITY 0x1 -#define XGE_HAL_RXD_T_CODE_ABORT 0x2 -#define XGE_HAL_RXD_T_CODE_PARITY_ABORT 0x3 -#define XGE_HAL_RXD_T_CODE_RDA_FAILURE 0x4 +#define XGE_HAL_RXD_T_CODE_OK 0x0 +#define XGE_HAL_RXD_T_CODE_PARITY 0x1 +#define XGE_HAL_RXD_T_CODE_ABORT 0x2 +#define XGE_HAL_RXD_T_CODE_PARITY_ABORT 0x3 +#define XGE_HAL_RXD_T_CODE_RDA_FAILURE 0x4 #define XGE_HAL_RXD_T_CODE_UNKNOWN_PROTO 0x5 -#define XGE_HAL_RXD_T_CODE_BAD_FCS 0x6 -#define XGE_HAL_RXD_T_CODE_BUFF_SIZE 0x7 -#define XGE_HAL_RXD_T_CODE_BAD_ECC 0x8 -#define XGE_HAL_RXD_T_CODE_UNUSED_C 0xC -#define XGE_HAL_RXD_T_CODE_UNKNOWN 0xF +#define XGE_HAL_RXD_T_CODE_BAD_FCS 0x6 +#define XGE_HAL_RXD_T_CODE_BUFF_SIZE 0x7 +#define XGE_HAL_RXD_T_CODE_BAD_ECC 0x8 +#define XGE_HAL_RXD_T_CODE_UNUSED_C 0xC +#define XGE_HAL_RXD_T_CODE_UNKNOWN 0xF -#define XGE_HAL_RING_USE_MTU -1 +#define XGE_HAL_RING_USE_MTU -1 /* control_1 and control_2 formatting - same for all buffer modes */ #define XGE_HAL_RXD_GET_L3_CKSUM(control_1) ((u16)(control_1>>16) & 0xFFFF) #define XGE_HAL_RXD_GET_L4_CKSUM(control_1) ((u16)(control_1 & 0xFFFF)) -#define XGE_HAL_RXD_MASK_VLAN_TAG vBIT(0xFFFF,48,16) +#define XGE_HAL_RXD_MASK_VLAN_TAG vBIT(0xFFFF,48,16) #define XGE_HAL_RXD_SET_VLAN_TAG(control_2, val) control_2 |= (u16)val -#define XGE_HAL_RXD_GET_VLAN_TAG(control_2) ((u16)(control_2 & 0xFFFF)) +#define XGE_HAL_RXD_GET_VLAN_TAG(control_2) ((u16)(control_2 & 0xFFFF)) -#define XGE_HAL_RXD_POSTED_4_XFRAME BIT(7) /* control_1 */ +#define XGE_HAL_RXD_POSTED_4_XFRAME BIT(7) /* control_1 */ #define XGE_HAL_RXD_NOT_COMPLETED BIT(0) /* control_2 */ -#define XGE_HAL_RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15)) -#define XGE_HAL_RXD_GET_T_CODE(control_1) \ - ((control_1 & XGE_HAL_RXD_T_CODE)>>48) +#define XGE_HAL_RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15)) +#define XGE_HAL_RXD_GET_T_CODE(control_1) \ + ((control_1 & XGE_HAL_RXD_T_CODE)>>48) #define XGE_HAL_RXD_SET_T_CODE(control_1, val) \ - (control_1 |= (((u64)val & 0xF) << 48)) - -#define XGE_HAL_RXD_MASK_FRAME_TYPE vBIT(0x3,25,2) -#define XGE_HAL_RXD_MASK_FRAME_PROTO vBIT(0xFFFF,24,8) -#define XGE_HAL_RXD_GET_FRAME_TYPE(control_1) \ - (u8)(0x3 & ((control_1 & XGE_HAL_RXD_MASK_FRAME_TYPE) >> 37)) -#define XGE_HAL_RXD_GET_FRAME_PROTO(control_1) \ - (u8)((control_1 & XGE_HAL_RXD_MASK_FRAME_PROTO) >> 32) -#define XGE_HAL_RXD_FRAME_PROTO_VLAN_TAGGED BIT(24) -#define XGE_HAL_RXD_FRAME_PROTO_IPV4 BIT(27) -#define XGE_HAL_RXD_FRAME_PROTO_IPV6 BIT(28) -#define XGE_HAL_RXD_FRAME_PROTO_IP_FRAGMENTED BIT(29) -#define XGE_HAL_RXD_FRAME_PROTO_TCP BIT(30) -#define XGE_HAL_RXD_FRAME_PROTO_UDP BIT(31) + (control_1 |= (((u64)val & 0xF) << 48)) + +#define XGE_HAL_RXD_MASK_FRAME_TYPE vBIT(0x3,25,2) +#define XGE_HAL_RXD_MASK_FRAME_PROTO vBIT(0xFFFF,24,8) +#define XGE_HAL_RXD_GET_FRAME_TYPE(control_1) \ + (u8)(0x3 & ((control_1 & XGE_HAL_RXD_MASK_FRAME_TYPE) >> 37)) +#define XGE_HAL_RXD_GET_FRAME_PROTO(control_1) \ + (u8)((control_1 & XGE_HAL_RXD_MASK_FRAME_PROTO) >> 32) +#define XGE_HAL_RXD_FRAME_PROTO_VLAN_TAGGED BIT(24) +#define XGE_HAL_RXD_FRAME_PROTO_IPV4 BIT(27) +#define XGE_HAL_RXD_FRAME_PROTO_IPV6 BIT(28) +#define XGE_HAL_RXD_FRAME_PROTO_IP_FRAGMENTED BIT(29) +#define XGE_HAL_RXD_FRAME_PROTO_TCP BIT(30) +#define XGE_HAL_RXD_FRAME_PROTO_UDP BIT(31) #define XGE_HAL_RXD_FRAME_TCP_OR_UDP (XGE_HAL_RXD_FRAME_PROTO_TCP | \ - XGE_HAL_RXD_FRAME_PROTO_UDP) + XGE_HAL_RXD_FRAME_PROTO_UDP) /** * enum xge_hal_frame_type_e - Ethernet frame format. @@ -101,10 +93,10 @@ __EXTERN_BEGIN_DECLS * Ethernet frame format. */ typedef enum xge_hal_frame_type_e { - XGE_HAL_FRAME_TYPE_DIX = 0x0, - XGE_HAL_FRAME_TYPE_LLC = 0x1, - XGE_HAL_FRAME_TYPE_SNAP = 0x2, - XGE_HAL_FRAME_TYPE_IPX = 0x3, + XGE_HAL_FRAME_TYPE_DIX = 0x0, + XGE_HAL_FRAME_TYPE_LLC = 0x1, + XGE_HAL_FRAME_TYPE_SNAP = 0x2, + XGE_HAL_FRAME_TYPE_IPX = 0x3, } xge_hal_frame_type_e; /** @@ -120,14 +112,14 @@ typedef enum xge_hal_frame_type_e { * Higher layer ethernet protocols and options. */ typedef enum xge_hal_frame_proto_e { - XGE_HAL_FRAME_PROTO_VLAN_TAGGED = 0x80, - XGE_HAL_FRAME_PROTO_IPV4 = 0x10, - XGE_HAL_FRAME_PROTO_IPV6 = 0x08, - XGE_HAL_FRAME_PROTO_IP_FRAGMENTED = 0x04, - XGE_HAL_FRAME_PROTO_TCP = 0x02, - XGE_HAL_FRAME_PROTO_UDP = 0x01, - XGE_HAL_FRAME_PROTO_TCP_OR_UDP = (XGE_HAL_FRAME_PROTO_TCP | \ - XGE_HAL_FRAME_PROTO_UDP) + XGE_HAL_FRAME_PROTO_VLAN_TAGGED = 0x80, + XGE_HAL_FRAME_PROTO_IPV4 = 0x10, + XGE_HAL_FRAME_PROTO_IPV6 = 0x08, + XGE_HAL_FRAME_PROTO_IP_FRAGMENTED = 0x04, + XGE_HAL_FRAME_PROTO_TCP = 0x02, + XGE_HAL_FRAME_PROTO_UDP = 0x01, + XGE_HAL_FRAME_PROTO_TCP_OR_UDP = (XGE_HAL_FRAME_PROTO_TCP | \ + XGE_HAL_FRAME_PROTO_UDP) } xge_hal_frame_proto_e; /* @@ -137,12 +129,12 @@ typedef struct { u64 host_control; u64 control_1; u64 control_2; -#define XGE_HAL_RXD_1_MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16) -#define XGE_HAL_RXD_1_SET_BUFFER0_SIZE(val) vBIT(val,0,16) +#define XGE_HAL_RXD_1_MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16) +#define XGE_HAL_RXD_1_SET_BUFFER0_SIZE(val) vBIT(val,0,16) #define XGE_HAL_RXD_1_GET_BUFFER0_SIZE(Control_2) \ - (int)((Control_2 & vBIT(0xFFFF,0,16))>>48) + (int)((Control_2 & vBIT(0xFFFF,0,16))>>48) #define XGE_HAL_RXD_1_GET_RTH_VALUE(Control_2) \ - (u32)((Control_2 & vBIT(0xFFFFFFFF,16,32))>>16) + (u32)((Control_2 & vBIT(0xFFFFFFFF,16,32))>>16) u64 buffer0_ptr; } xge_hal_ring_rxd_1_t; @@ -154,20 +146,20 @@ typedef struct { u64 control_1; u64 control_2; -#define XGE_HAL_RXD_3_MASK_BUFFER0_SIZE vBIT(0xFF,8,8) -#define XGE_HAL_RXD_3_SET_BUFFER0_SIZE(val) vBIT(val,8,8) -#define XGE_HAL_RXD_3_MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16) -#define XGE_HAL_RXD_3_SET_BUFFER1_SIZE(val) vBIT(val,16,16) -#define XGE_HAL_RXD_3_MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16) -#define XGE_HAL_RXD_3_SET_BUFFER2_SIZE(val) vBIT(val,32,16) +#define XGE_HAL_RXD_3_MASK_BUFFER0_SIZE vBIT(0xFF,8,8) +#define XGE_HAL_RXD_3_SET_BUFFER0_SIZE(val) vBIT(val,8,8) +#define XGE_HAL_RXD_3_MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16) +#define XGE_HAL_RXD_3_SET_BUFFER1_SIZE(val) vBIT(val,16,16) +#define XGE_HAL_RXD_3_MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16) +#define XGE_HAL_RXD_3_SET_BUFFER2_SIZE(val) vBIT(val,32,16) #define XGE_HAL_RXD_3_GET_BUFFER0_SIZE(Control_2) \ - (int)((Control_2 & vBIT(0xFF,8,8))>>48) + (int)((Control_2 & vBIT(0xFF,8,8))>>48) #define XGE_HAL_RXD_3_GET_BUFFER1_SIZE(Control_2) \ - (int)((Control_2 & vBIT(0xFFFF,16,16))>>32) + (int)((Control_2 & vBIT(0xFFFF,16,16))>>32) #define XGE_HAL_RXD_3_GET_BUFFER2_SIZE(Control_2) \ - (int)((Control_2 & vBIT(0xFFFF,32,16))>>16) + (int)((Control_2 & vBIT(0xFFFF,32,16))>>16) u64 buffer0_ptr; u64 buffer1_ptr; @@ -187,33 +179,33 @@ typedef struct { #endif -#define XGE_HAL_RXD_5_MASK_BUFFER3_SIZE vBIT(0xFFFF,32,16) -#define XGE_HAL_RXD_5_SET_BUFFER3_SIZE(val) vBIT(val,32,16) -#define XGE_HAL_RXD_5_MASK_BUFFER4_SIZE vBIT(0xFFFF,48,16) -#define XGE_HAL_RXD_5_SET_BUFFER4_SIZE(val) vBIT(val,48,16) +#define XGE_HAL_RXD_5_MASK_BUFFER3_SIZE vBIT(0xFFFF,32,16) +#define XGE_HAL_RXD_5_SET_BUFFER3_SIZE(val) vBIT(val,32,16) +#define XGE_HAL_RXD_5_MASK_BUFFER4_SIZE vBIT(0xFFFF,48,16) +#define XGE_HAL_RXD_5_SET_BUFFER4_SIZE(val) vBIT(val,48,16) #define XGE_HAL_RXD_5_GET_BUFFER3_SIZE(Control_3) \ - (int)((Control_3 & vBIT(0xFFFF,32,16))>>16) + (int)((Control_3 & vBIT(0xFFFF,32,16))>>16) #define XGE_HAL_RXD_5_GET_BUFFER4_SIZE(Control_3) \ - (int)((Control_3 & vBIT(0xFFFF,48,16))) + (int)((Control_3 & vBIT(0xFFFF,48,16))) u64 control_1; u64 control_2; -#define XGE_HAL_RXD_5_MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16) -#define XGE_HAL_RXD_5_SET_BUFFER0_SIZE(val) vBIT(val,0,16) -#define XGE_HAL_RXD_5_MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16) -#define XGE_HAL_RXD_5_SET_BUFFER1_SIZE(val) vBIT(val,16,16) -#define XGE_HAL_RXD_5_MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16) -#define XGE_HAL_RXD_5_SET_BUFFER2_SIZE(val) vBIT(val,32,16) +#define XGE_HAL_RXD_5_MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16) +#define XGE_HAL_RXD_5_SET_BUFFER0_SIZE(val) vBIT(val,0,16) +#define XGE_HAL_RXD_5_MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16) +#define XGE_HAL_RXD_5_SET_BUFFER1_SIZE(val) vBIT(val,16,16) +#define XGE_HAL_RXD_5_MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16) +#define XGE_HAL_RXD_5_SET_BUFFER2_SIZE(val) vBIT(val,32,16) #define XGE_HAL_RXD_5_GET_BUFFER0_SIZE(Control_2) \ - (int)((Control_2 & vBIT(0xFFFF,0,16))>>48) + (int)((Control_2 & vBIT(0xFFFF,0,16))>>48) #define XGE_HAL_RXD_5_GET_BUFFER1_SIZE(Control_2) \ - (int)((Control_2 & vBIT(0xFFFF,16,16))>>32) + (int)((Control_2 & vBIT(0xFFFF,16,16))>>32) #define XGE_HAL_RXD_5_GET_BUFFER2_SIZE(Control_2) \ - (int)((Control_2 & vBIT(0xFFFF,32,16))>>16) + (int)((Control_2 & vBIT(0xFFFF,32,16))>>16) u64 buffer0_ptr; u64 buffer1_ptr; u64 buffer2_ptr; @@ -222,32 +214,32 @@ typedef struct { } xge_hal_ring_rxd_5_t; #define XGE_HAL_RXD_GET_RTH_SPDM_HIT(Control_1) \ - (u8)((Control_1 & BIT(18))>>45) + (u8)((Control_1 & BIT(18))>>45) #define XGE_HAL_RXD_GET_RTH_IT_HIT(Control_1) \ - (u8)((Control_1 & BIT(19))>>44) + (u8)((Control_1 & BIT(19))>>44) #define XGE_HAL_RXD_GET_RTH_HASH_TYPE(Control_1) \ - (u8)((Control_1 & vBIT(0xF,20,4))>>40) - -#define XGE_HAL_RXD_HASH_TYPE_NONE 0x0 -#define XGE_HAL_RXD_HASH_TYPE_TCP_IPV4 0x1 -#define XGE_HAL_RXD_HASH_TYPE_UDP_IPV4 0x2 -#define XGE_HAL_RXD_HASH_TYPE_IPV4 0x3 -#define XGE_HAL_RXD_HASH_TYPE_TCP_IPV6 0x4 -#define XGE_HAL_RXD_HASH_TYPE_UDP_IPV6 0x5 -#define XGE_HAL_RXD_HASH_TYPE_IPV6 0x6 -#define XGE_HAL_RXD_HASH_TYPE_TCP_IPV6_EX 0x7 -#define XGE_HAL_RXD_HASH_TYPE_UDP_IPV6_EX 0x8 -#define XGE_HAL_RXD_HASH_TYPE_IPV6_EX 0x9 + (u8)((Control_1 & vBIT(0xF,20,4))>>40) + +#define XGE_HAL_RXD_HASH_TYPE_NONE 0x0 +#define XGE_HAL_RXD_HASH_TYPE_TCP_IPV4 0x1 +#define XGE_HAL_RXD_HASH_TYPE_UDP_IPV4 0x2 +#define XGE_HAL_RXD_HASH_TYPE_IPV4 0x3 +#define XGE_HAL_RXD_HASH_TYPE_TCP_IPV6 0x4 +#define XGE_HAL_RXD_HASH_TYPE_UDP_IPV6 0x5 +#define XGE_HAL_RXD_HASH_TYPE_IPV6 0x6 +#define XGE_HAL_RXD_HASH_TYPE_TCP_IPV6_EX 0x7 +#define XGE_HAL_RXD_HASH_TYPE_UDP_IPV6_EX 0x8 +#define XGE_HAL_RXD_HASH_TYPE_IPV6_EX 0x9 typedef u8 xge_hal_ring_block_t[XGE_HAL_RING_RXDBLOCK_SIZE]; -#define XGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET 0xFF8 -#define XGE_HAL_RING_MEMBLOCK_IDX_OFFSET 0xFF0 +#define XGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET 0xFF8 +#define XGE_HAL_RING_MEMBLOCK_IDX_OFFSET 0xFF0 #define XGE_HAL_RING_RXD_SIZEOF(n) \ (n==1 ? sizeof(xge_hal_ring_rxd_1_t) : \ - (n==3 ? sizeof(xge_hal_ring_rxd_3_t) : \ - sizeof(xge_hal_ring_rxd_5_t))) + (n==3 ? sizeof(xge_hal_ring_rxd_3_t) : \ + sizeof(xge_hal_ring_rxd_5_t))) #define XGE_HAL_RING_RXDS_PER_BLOCK(n) \ (n==1 ? 127 : (n==3 ? 85 : 63)) @@ -274,14 +266,14 @@ typedef u8 xge_hal_ring_block_t[XGE_HAL_RING_RXDBLOCK_SIZE]; * purposes. */ typedef struct xge_hal_ring_rxd_priv_t { - dma_addr_t dma_addr; - pci_dma_h dma_handle; - ptrdiff_t dma_offset; + dma_addr_t dma_addr; + pci_dma_h dma_handle; + ptrdiff_t dma_offset; #ifdef XGE_DEBUG_ASSERT - xge_hal_mempool_dma_t *dma_object; + xge_hal_mempool_dma_t *dma_object; #endif #ifdef XGE_OS_MEMORY_CHECK - int allocated; + int allocated; #endif } xge_hal_ring_rxd_priv_t; @@ -317,17 +309,17 @@ typedef struct xge_hal_ring_rxd_priv_t { * CPU cache performance. */ typedef struct xge_hal_ring_t { - xge_hal_channel_t channel; - int buffer_mode; - int indicate_max_pkts; - xge_hal_ring_config_t *config; - int rxd_size; - int rxd_priv_size; - int rxds_per_block; - xge_hal_mempool_t *mempool; - int rxdblock_priv_size; - void **reserved_rxds_arr; - int cmpl_cnt; + xge_hal_channel_t channel; + int buffer_mode; + int indicate_max_pkts; + xge_hal_ring_config_t *config; + int rxd_size; + int rxd_priv_size; + int rxds_per_block; + xge_hal_mempool_t *mempool; + int rxdblock_priv_size; + void **reserved_rxds_arr; + int cmpl_cnt; } __xge_os_attr_cacheline_aligned xge_hal_ring_t; /** @@ -343,7 +335,7 @@ typedef struct xge_hal_ring_t { * corrupted. * @frame: See xge_hal_frame_type_e{}. * @proto: Reporting bits for various higher-layer protocols, including (but - * note restricted to) TCP and UDP. See xge_hal_frame_proto_e{}. + * note restricted to) TCP and UDP. See xge_hal_frame_proto_e{}. * @vlan: VLAN tag extracted from the received frame. * @rth_value: Receive Traffic Hashing(RTH) hash value. Produced by Xframe II * hardware if RTH is enabled. @@ -355,22 +347,22 @@ typedef struct xge_hal_ring_t { * @reserved_pad: Unused byte. */ typedef struct xge_hal_dtr_info_t { - int l3_cksum; - int l4_cksum; - int frame; /* zero or more of xge_hal_frame_type_e flags */ - int proto; /* zero or more of xge_hal_frame_proto_e flags */ - int vlan; - u32 rth_value; - u8 rth_it_hit; - u8 rth_spdm_hit; - u8 rth_hash_type; - u8 reserved_pad; + int l3_cksum; + int l4_cksum; + int frame; /* zero or more of xge_hal_frame_type_e flags */ + int proto; /* zero or more of xge_hal_frame_proto_e flags */ + int vlan; + u32 rth_value; + u8 rth_it_hit; + u8 rth_spdm_hit; + u8 rth_hash_type; + u8 reserved_pad; } xge_hal_dtr_info_t; /* ========================== RING PRIVATE API ============================ */ xge_hal_status_e __hal_ring_open(xge_hal_channel_h channelh, - xge_hal_channel_attr_t *attr); + xge_hal_channel_attr_t *attr); void __hal_ring_close(xge_hal_channel_h channelh); @@ -383,7 +375,7 @@ void __hal_ring_prc_enable(xge_hal_channel_h channelh); void __hal_ring_prc_disable(xge_hal_channel_h channelh); xge_hal_status_e __hal_ring_initial_replenish(xge_hal_channel_t *channel, - xge_hal_channel_reopen_e reopen); + xge_hal_channel_reopen_e reopen); #if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_RING) #define __HAL_STATIC_RING @@ -400,7 +392,7 @@ __hal_ring_block_next_pointer(xge_hal_ring_block_t *block); __HAL_STATIC_RING __HAL_INLINE_RING void __hal_ring_block_next_pointer_set(xge_hal_ring_block_t*block, - dma_addr_t dma_next); + dma_addr_t dma_next); __HAL_STATIC_RING __HAL_INLINE_RING xge_hal_ring_rxd_priv_t* __hal_ring_rxd_priv(xge_hal_ring_t *ring, xge_hal_dtr_h dtrh); @@ -414,31 +406,31 @@ __HAL_STATIC_RING __HAL_INLINE_RING void* xge_hal_ring_dtr_private(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); __HAL_STATIC_RING __HAL_INLINE_RING void -xge_hal_ring_dtr_1b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointer, int size); +xge_hal_ring_dtr_1b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointer, int size); __HAL_STATIC_RING __HAL_INLINE_RING void xge_hal_ring_dtr_info_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, - xge_hal_dtr_info_t *ext_info); + xge_hal_dtr_info_t *ext_info); __HAL_STATIC_RING __HAL_INLINE_RING void xge_hal_ring_dtr_1b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, - dma_addr_t *dma_pointer, int *pkt_length); + dma_addr_t *dma_pointer, int *pkt_length); __HAL_STATIC_RING __HAL_INLINE_RING void xge_hal_ring_dtr_3b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[], - int sizes[]); + int sizes[]); __HAL_STATIC_RING __HAL_INLINE_RING void xge_hal_ring_dtr_3b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, - dma_addr_t dma_pointers[], int sizes[]); + dma_addr_t dma_pointers[], int sizes[]); __HAL_STATIC_RING __HAL_INLINE_RING void xge_hal_ring_dtr_5b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[], - int sizes[]); + int sizes[]); __HAL_STATIC_RING __HAL_INLINE_RING void xge_hal_ring_dtr_5b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, - dma_addr_t dma_pointer[], int sizes[]); + dma_addr_t dma_pointer[], int sizes[]); __HAL_STATIC_RING __HAL_INLINE_RING void xge_hal_ring_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); @@ -454,12 +446,12 @@ xge_hal_ring_dtr_post_post_wmb(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); __HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e xge_hal_ring_dtr_next_completed(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh, - u8 *t_code); + u8 *t_code); __HAL_STATIC_RING __HAL_INLINE_RING void xge_hal_ring_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); -__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e +__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e xge_hal_ring_is_next_dtr_completed(xge_hal_channel_h channelh); #else /* XGE_FASTPATH_EXTERN */ diff --git a/sys/dev/nxge/include/xgehal-stats.h b/sys/dev/nxge/include/xgehal-stats.h index ffe0e6e..ec093e7 100644 --- a/sys/dev/nxge/include/xgehal-stats.h +++ b/sys/dev/nxge/include/xgehal-stats.h @@ -26,15 +26,6 @@ * $FreeBSD$ */ -/* - xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh; - * FileName : xgehal-stats.h - * - * Description: HW statistics object - * - * Created: 2 June 2004 - */ - #ifndef XGE_HAL_STATS_H #define XGE_HAL_STATS_H @@ -524,7 +515,7 @@ typedef struct xge_hal_stats_hw_info_t { u32 wr_disc_cnt; u32 rd_rtry_wr_ack_cnt; -/* DMA Transaction statistics. */ +/* DMA Transaction statistics. */ u32 txp_wr_cnt; u32 txd_rd_cnt; u32 txd_wr_cnt; @@ -696,7 +687,7 @@ typedef struct xge_hal_stats_hw_info_t { u32 wr_disc_cnt; u32 wr_rtry_cnt; -/* PCI/PCI-X Write / DMA Transaction statistics. */ +/* PCI/PCI-X Write / DMA Transaction statistics. */ u32 txp_wr_cnt; u32 rd_rtry_wr_ack_cnt; u32 txd_wr_cnt; @@ -805,34 +796,34 @@ typedef struct xge_hal_stats_hw_info_t { * @total_posts_dtrs_many: Total number of posts on the channel that involving * more than one descriptor. * @total_posts_frags_many: Total number of fragments posted on the channel - * during post requests of multiple descriptors. + * during post requests of multiple descriptors. * @total_posts_dang_dtrs: Total number of posts on the channel involving * dangling descriptors. * @total_posts_dang_frags: Total number of dangling fragments posted on the channel - * during post request containing multiple descriptors. + * during post request containing multiple descriptors. * * HAL channel counters. * See also: xge_hal_stats_device_info_t{}. */ typedef struct xge_hal_stats_channel_info_t { - u32 full_cnt; - u32 usage_max; - u32 reserve_free_swaps_cnt; - u32 avg_compl_per_intr_cnt; - u32 total_compl_cnt; - u32 total_posts; - u32 total_posts_many; - u32 total_buffers; - u32 copied_frags; - u32 copied_buffers; - u32 avg_buffers_per_post; - u32 avg_buffer_size; - u32 avg_post_size; - u32 ring_bump_cnt; - u32 total_posts_dtrs_many; - u32 total_posts_frags_many; - u32 total_posts_dang_dtrs; - u32 total_posts_dang_frags; + u32 full_cnt; + u32 usage_max; + u32 reserve_free_swaps_cnt; + u32 avg_compl_per_intr_cnt; + u32 total_compl_cnt; + u32 total_posts; + u32 total_posts_many; + u32 total_buffers; + u32 copied_frags; + u32 copied_buffers; + u32 avg_buffers_per_post; + u32 avg_buffer_size; + u32 avg_post_size; + u32 ring_bump_cnt; + u32 total_posts_dtrs_many; + u32 total_posts_frags_many; + u32 total_posts_dang_dtrs; + u32 total_posts_dang_frags; } xge_hal_stats_channel_info_t; /** @@ -843,10 +834,10 @@ typedef struct xge_hal_stats_channel_info_t { * @tick_period: tick count for each cycle */ typedef struct xge_hal_xpak_counter_t { - u32 excess_temp; - u32 excess_bias_current; - u32 excess_laser_output; - u32 tick_period; + u32 excess_temp; + u32 excess_bias_current; + u32 excess_laser_output; + u32 tick_period; } xge_hal_xpak_counter_t; /** @@ -865,18 +856,18 @@ typedef struct xge_hal_xpak_counter_t { * @warn_laser_output_power_low: warn_laser_output_power_low count value */ typedef struct xge_hal_stats_xpak_t { - u16 alarm_transceiver_temp_high; - u16 alarm_transceiver_temp_low; - u16 alarm_laser_bias_current_high; - u16 alarm_laser_bias_current_low; - u16 alarm_laser_output_power_high; - u16 alarm_laser_output_power_low; - u16 warn_transceiver_temp_high; - u16 warn_transceiver_temp_low; - u16 warn_laser_bias_current_high; - u16 warn_laser_bias_current_low; - u16 warn_laser_output_power_high; - u16 warn_laser_output_power_low; + u16 alarm_transceiver_temp_high; + u16 alarm_transceiver_temp_low; + u16 alarm_laser_bias_current_high; + u16 alarm_laser_bias_current_low; + u16 alarm_laser_output_power_high; + u16 alarm_laser_output_power_low; + u16 warn_transceiver_temp_high; + u16 warn_transceiver_temp_low; + u16 warn_laser_bias_current_high; + u16 warn_laser_bias_current_low; + u16 warn_laser_output_power_high; + u16 warn_laser_output_power_low; } xge_hal_stats_xpak_t; @@ -955,83 +946,55 @@ typedef struct xge_hal_stats_sw_err_t { * See also: xge_hal_stats_channel_info_t{}. */ typedef struct xge_hal_stats_device_info_t { - u32 rx_traffic_intr_cnt; - u32 tx_traffic_intr_cnt; - u32 txpic_intr_cnt; - u32 txdma_intr_cnt; - u32 pfc_err_cnt; - u32 tda_err_cnt; - u32 pcc_err_cnt; - u32 tti_err_cnt; - u32 lso_err_cnt; - u32 tpa_err_cnt; - u32 sm_err_cnt; - u32 txmac_intr_cnt; - u32 mac_tmac_err_cnt; - u32 txxgxs_intr_cnt; - u32 xgxs_txgxs_err_cnt; - u32 rxpic_intr_cnt; - u32 rxdma_intr_cnt; - u32 rc_err_cnt; - u32 rpa_err_cnt; - u32 rda_err_cnt; - u32 rti_err_cnt; - u32 rxmac_intr_cnt; - u32 mac_rmac_err_cnt; - u32 rxxgxs_intr_cnt; - u32 xgxs_rxgxs_err_cnt; - u32 mc_intr_cnt; - u32 not_traffic_intr_cnt; - u32 not_xge_intr_cnt; - u32 traffic_intr_cnt; - u32 total_intr_cnt; - u32 soft_reset_cnt; - u32 rxufca_hi_adjust_cnt; - u32 rxufca_lo_adjust_cnt; - u32 bimodal_hi_adjust_cnt; - u32 bimodal_lo_adjust_cnt; + u32 rx_traffic_intr_cnt; + u32 tx_traffic_intr_cnt; + u32 txpic_intr_cnt; + u32 txdma_intr_cnt; + u32 pfc_err_cnt; + u32 tda_err_cnt; + u32 pcc_err_cnt; + u32 tti_err_cnt; + u32 lso_err_cnt; + u32 tpa_err_cnt; + u32 sm_err_cnt; + u32 txmac_intr_cnt; + u32 mac_tmac_err_cnt; + u32 txxgxs_intr_cnt; + u32 xgxs_txgxs_err_cnt; + u32 rxpic_intr_cnt; + u32 rxdma_intr_cnt; + u32 rc_err_cnt; + u32 rpa_err_cnt; + u32 rda_err_cnt; + u32 rti_err_cnt; + u32 rxmac_intr_cnt; + u32 mac_rmac_err_cnt; + u32 rxxgxs_intr_cnt; + u32 xgxs_rxgxs_err_cnt; + u32 mc_intr_cnt; + u32 not_traffic_intr_cnt; + u32 not_xge_intr_cnt; + u32 traffic_intr_cnt; + u32 total_intr_cnt; + u32 soft_reset_cnt; + u32 rxufca_hi_adjust_cnt; + u32 rxufca_lo_adjust_cnt; + u32 bimodal_hi_adjust_cnt; + u32 bimodal_lo_adjust_cnt; #ifdef XGE_HAL_CONFIG_LRO - u32 tot_frms_lroised; - u32 tot_lro_sessions; - u32 lro_frm_len_exceed_cnt; - u32 lro_sg_exceed_cnt; - u32 lro_out_of_seq_pkt_cnt; - u32 lro_dup_pkt_cnt; + u32 tot_frms_lroised; + u32 tot_lro_sessions; + u32 lro_frm_len_exceed_cnt; + u32 lro_sg_exceed_cnt; + u32 lro_out_of_seq_pkt_cnt; + u32 lro_dup_pkt_cnt; #endif } xge_hal_stats_device_info_t; -#ifdef XGEHAL_RNIC - -/** - * struct xge_hal_vp_statistics_t - Virtual Path Statistics - * - * @no_nces: Number of NCEs on Adapter in this VP - * @no_sqs: Number of SQs on Adapter in this VP - * @no_srqs: Number of SRQs on Adapter in this VP - * @no_cqrqs: Number of CQRQs on Adapter in this VP - * @no_tcp_sessions: Number of TCP sessions on Adapter in this VP - * @no_lro_sessions: Number of LRO sessions on Adapter in this VP - * @no_spdm_sessions: Number of SPDM sessions on Adapter in this VP - * - * This structure contains fields to keep statistics of virtual path - */ -typedef struct xge_hal_vp_statistics_t { - u32 no_nces; - u32 no_sqs; - u32 no_srqs; - u32 no_cqrqs; - u32 no_tcp_sessions; - u32 no_lro_sessions; - u32 no_spdm_sessions; -}xge_hal_vp_statistics_t; - -#endif - - /* ========================== XFRAME ER STATISTICS ======================== */ -#define XGE_HAL_MAC_LINKS 3 -#define XGE_HAL_MAC_AGGREGATORS 2 -#define XGE_HAL_VPATHS 17 +#define XGE_HAL_MAC_LINKS 3 +#define XGE_HAL_MAC_AGGREGATORS 2 +#define XGE_HAL_VPATHS 17 /** * struct xge_hal_stats_link_info_t - XGMAC statistics for a link * @@ -1207,97 +1170,97 @@ typedef struct xge_hal_vp_statistics_t { * queue for mac the link. */ typedef struct xge_hal_stats_link_info_t { - u64 tx_frms; - u64 tx_ttl_eth_octets; - u64 tx_data_octets; - u64 tx_mcst_frms; - u64 tx_bcst_frms; - u64 tx_ucst_frms; - u64 tx_tagged_frms; - u64 tx_vld_ip; - u64 tx_vld_ip_octets; - u64 tx_icmp; - u64 tx_tcp; - u64 tx_rst_tcp; - u64 tx_udp; - u64 tx_unknown_protocol; - u64 tx_parse_error; - u64 tx_pause_ctrl_frms; - u64 tx_lacpdu_frms; - u64 tx_marker_pdu_frms; - u64 tx_marker_resp_pdu_frms; - u64 tx_drop_ip; - u64 tx_xgmii_char1_match; - u64 tx_xgmii_char2_match; - u64 tx_xgmii_column1_match; - u64 tx_xgmii_column2_match; - u64 tx_drop_frms; - u64 tx_any_err_frms; - u64 rx_ttl_frms; - u64 rx_vld_frms; - u64 rx_offld_frms; - u64 rx_ttl_eth_octets; - u64 rx_data_octets; - u64 rx_offld_octets; - u64 rx_vld_mcst_frms; - u64 rx_vld_bcst_frms; - u64 rx_accepted_ucst_frms; - u64 rx_accepted_nucst_frms; - u64 rx_tagged_frms; - u64 rx_long_frms; - u64 rx_usized_frms; - u64 rx_osized_frms; - u64 rx_frag_frms; - u64 rx_jabber_frms; - u64 rx_ttl_64_frms; - u64 rx_ttl_65_127_frms; - u64 rx_ttl_128_255_frms; - u64 rx_ttl_256_511_frms; - u64 rx_ttl_512_1023_frms; - u64 rx_ttl_1024_1518_frms; - u64 rx_ttl_1519_4095_frms; - u64 rx_ttl_40956_8191_frms; - u64 rx_ttl_8192_max_frms; - u64 rx_ttl_gt_max_frms; - u64 rx_ip; - u64 rx_ip_octets; - u64 rx_hdr_err_ip; - u64 rx_icmp; - u64 rx_tcp; - u64 rx_udp; - u64 rx_err_tcp; - u64 rx_pause_cnt; - u64 rx_pause_ctrl_frms; - u64 rx_unsup_ctrl_frms; - u64 rx_in_rng_len_err_frms; - u64 rx_out_rng_len_err_frms; - u64 rx_drop_frms; - u64 rx_discarded_frms; - u64 rx_drop_ip; - u64 rx_err_drp_udp; - u64 rx_lacpdu_frms; - u64 rx_marker_pdu_frms; - u64 rx_marker_resp_pdu_frms; - u64 rx_unknown_pdu_frms; - u64 rx_illegal_pdu_frms; - u64 rx_fcs_discard; - u64 rx_len_discard; - u64 rx_pf_discard; - u64 rx_trash_discard; - u64 rx_rts_discard; - u64 rx_wol_discard; - u64 rx_red_discard; - u64 rx_ingm_full_discard; - u64 rx_xgmii_data_err_cnt; - u64 rx_xgmii_ctrl_err_cnt; - u64 rx_xgmii_err_sym; - u64 rx_xgmii_char1_match; - u64 rx_xgmii_char2_match; - u64 rx_xgmii_column1_match; - u64 rx_xgmii_column2_match; - u64 rx_local_fault; - u64 rx_remote_fault; - u64 rx_queue_full; + u64 tx_frms; + u64 tx_ttl_eth_octets; + u64 tx_data_octets; + u64 tx_mcst_frms; + u64 tx_bcst_frms; + u64 tx_ucst_frms; + u64 tx_tagged_frms; + u64 tx_vld_ip; + u64 tx_vld_ip_octets; + u64 tx_icmp; + u64 tx_tcp; + u64 tx_rst_tcp; + u64 tx_udp; + u64 tx_unknown_protocol; + u64 tx_parse_error; + u64 tx_pause_ctrl_frms; + u64 tx_lacpdu_frms; + u64 tx_marker_pdu_frms; + u64 tx_marker_resp_pdu_frms; + u64 tx_drop_ip; + u64 tx_xgmii_char1_match; + u64 tx_xgmii_char2_match; + u64 tx_xgmii_column1_match; + u64 tx_xgmii_column2_match; + u64 tx_drop_frms; + u64 tx_any_err_frms; + u64 rx_ttl_frms; + u64 rx_vld_frms; + u64 rx_offld_frms; + u64 rx_ttl_eth_octets; + u64 rx_data_octets; + u64 rx_offld_octets; + u64 rx_vld_mcst_frms; + u64 rx_vld_bcst_frms; + u64 rx_accepted_ucst_frms; + u64 rx_accepted_nucst_frms; + u64 rx_tagged_frms; + u64 rx_long_frms; + u64 rx_usized_frms; + u64 rx_osized_frms; + u64 rx_frag_frms; + u64 rx_jabber_frms; + u64 rx_ttl_64_frms; + u64 rx_ttl_65_127_frms; + u64 rx_ttl_128_255_frms; + u64 rx_ttl_256_511_frms; + u64 rx_ttl_512_1023_frms; + u64 rx_ttl_1024_1518_frms; + u64 rx_ttl_1519_4095_frms; + u64 rx_ttl_40956_8191_frms; + u64 rx_ttl_8192_max_frms; + u64 rx_ttl_gt_max_frms; + u64 rx_ip; + u64 rx_ip_octets; + u64 rx_hdr_err_ip; + u64 rx_icmp; + u64 rx_tcp; + u64 rx_udp; + u64 rx_err_tcp; + u64 rx_pause_cnt; + u64 rx_pause_ctrl_frms; + u64 rx_unsup_ctrl_frms; + u64 rx_in_rng_len_err_frms; + u64 rx_out_rng_len_err_frms; + u64 rx_drop_frms; + u64 rx_discarded_frms; + u64 rx_drop_ip; + u64 rx_err_drp_udp; + u64 rx_lacpdu_frms; + u64 rx_marker_pdu_frms; + u64 rx_marker_resp_pdu_frms; + u64 rx_unknown_pdu_frms; + u64 rx_illegal_pdu_frms; + u64 rx_fcs_discard; + u64 rx_len_discard; + u64 rx_pf_discard; + u64 rx_trash_discard; + u64 rx_rts_discard; + u64 rx_wol_discard; + u64 rx_red_discard; + u64 rx_ingm_full_discard; + u64 rx_xgmii_data_err_cnt; + u64 rx_xgmii_ctrl_err_cnt; + u64 rx_xgmii_err_sym; + u64 rx_xgmii_char1_match; + u64 rx_xgmii_char2_match; + u64 rx_xgmii_column1_match; + u64 rx_xgmii_column2_match; + u64 rx_local_fault; + u64 rx_remote_fault; + u64 rx_queue_full; }xge_hal_stats_link_info_t; /** @@ -1323,18 +1286,18 @@ typedef struct xge_hal_stats_link_info_t { * the aggregator. */ typedef struct xge_hal_stats_aggr_info_t { - u64 tx_frms; - u64 tx_mcst_frms; - u64 tx_bcst_frms; - u64 tx_discarded_frms; - u64 tx_errored_frms; - u64 rx_frms; - u64 rx_data_octets; - u64 rx_mcst_frms; - u64 rx_bcst_frms; - u64 rx_discarded_frms; - u64 rx_errored_frms; - u64 rx_unknown_protocol_frms; + u64 tx_frms; + u64 tx_mcst_frms; + u64 tx_bcst_frms; + u64 tx_discarded_frms; + u64 tx_errored_frms; + u64 rx_frms; + u64 rx_data_octets; + u64 rx_mcst_frms; + u64 rx_bcst_frms; + u64 rx_discarded_frms; + u64 rx_errored_frms; + u64 rx_unknown_protocol_frms; }xge_hal_stats_aggr_info_t; /** @@ -1439,60 +1402,60 @@ typedef struct xge_hal_stats_aggr_info_t { * the vpath. */ typedef struct xge_hal_stats_vpath_info_t { - u64 tx_frms; - u64 tx_ttl_eth_octets; - u64 tx_data_octets; - u64 tx_mcst_frms; - u64 tx_bcst_frms; - u64 tx_ucst_frms; - u64 tx_tagged_frms; - u64 tx_vld_ip; - u64 tx_vld_ip_octets; - u64 tx_icmp; - u64 tx_tcp; - u64 tx_rst_tcp; - u64 tx_udp; - u64 tx_unknown_protocol; - u64 tx_parse_error; - u64 rx_ttl_frms; - u64 rx_vld_frms; - u64 rx_offld_frms; - u64 rx_ttl_eth_octets; - u64 rx_data_octets; - u64 rx_offld_octets; - u64 rx_vld_mcst_frms; - u64 rx_vld_bcst_frms; - u64 rx_accepted_ucst_frms; - u64 rx_accepted_nucst_frms; - u64 rx_tagged_frms; - u64 rx_long_frms; - u64 rx_usized_frms; - u64 rx_osized_frms; - u64 rx_frag_frms; - u64 rx_jabber_frms; - u64 rx_ttl_64_frms; - u64 rx_ttl_65_127_frms; - u64 rx_ttl_128_255_frms; - u64 rx_ttl_256_511_frms; - u64 rx_ttl_512_1023_frms; - u64 rx_ttl_1024_1518_frms; - u64 rx_ttl_1519_4095_frms; - u64 rx_ttl_40956_8191_frms; - u64 rx_ttl_8192_max_frms; - u64 rx_ttl_gt_max_frms; - u64 rx_ip; - u64 rx_accepted_ip; - u64 rx_ip_octets; - u64 rx_hdr_err_ip; - u64 rx_icmp; - u64 rx_tcp; - u64 rx_udp; - u64 rx_err_tcp; - u64 rx_mpa_ok_frms; - u64 rx_mpa_crc_fail_frms; - u64 rx_mpa_mrk_fail_frms; - u64 rx_mpa_len_fail_frms; - u64 rx_wol_frms; + u64 tx_frms; + u64 tx_ttl_eth_octets; + u64 tx_data_octets; + u64 tx_mcst_frms; + u64 tx_bcst_frms; + u64 tx_ucst_frms; + u64 tx_tagged_frms; + u64 tx_vld_ip; + u64 tx_vld_ip_octets; + u64 tx_icmp; + u64 tx_tcp; + u64 tx_rst_tcp; + u64 tx_udp; + u64 tx_unknown_protocol; + u64 tx_parse_error; + u64 rx_ttl_frms; + u64 rx_vld_frms; + u64 rx_offld_frms; + u64 rx_ttl_eth_octets; + u64 rx_data_octets; + u64 rx_offld_octets; + u64 rx_vld_mcst_frms; + u64 rx_vld_bcst_frms; + u64 rx_accepted_ucst_frms; + u64 rx_accepted_nucst_frms; + u64 rx_tagged_frms; + u64 rx_long_frms; + u64 rx_usized_frms; + u64 rx_osized_frms; + u64 rx_frag_frms; + u64 rx_jabber_frms; + u64 rx_ttl_64_frms; + u64 rx_ttl_65_127_frms; + u64 rx_ttl_128_255_frms; + u64 rx_ttl_256_511_frms; + u64 rx_ttl_512_1023_frms; + u64 rx_ttl_1024_1518_frms; + u64 rx_ttl_1519_4095_frms; + u64 rx_ttl_40956_8191_frms; + u64 rx_ttl_8192_max_frms; + u64 rx_ttl_gt_max_frms; + u64 rx_ip; + u64 rx_accepted_ip; + u64 rx_ip_octets; + u64 rx_hdr_err_ip; + u64 rx_icmp; + u64 rx_tcp; + u64 rx_udp; + u64 rx_err_tcp; + u64 rx_mpa_ok_frms; + u64 rx_mpa_crc_fail_frms; + u64 rx_mpa_mrk_fail_frms; + u64 rx_mpa_len_fail_frms; + u64 rx_wol_frms; }xge_hal_stats_vpath_info_t; /** @@ -1503,8 +1466,8 @@ typedef struct xge_hal_stats_vpath_info_t { * See also: xge_hal_stats_link_info_t{}, xge_hal_stats_aggr_info_t{}. */ typedef struct xge_hal_stats_pcim_info_t { - xge_hal_stats_link_info_t link_info[XGE_HAL_MAC_LINKS]; - xge_hal_stats_aggr_info_t aggr_info[XGE_HAL_MAC_AGGREGATORS]; + xge_hal_stats_link_info_t link_info[XGE_HAL_MAC_LINKS]; + xge_hal_stats_aggr_info_t aggr_info[XGE_HAL_MAC_AGGREGATORS]; }xge_hal_stats_pcim_info_t; /** @@ -1541,35 +1504,35 @@ typedef struct xge_hal_stats_pcim_info_t { * See also: xge_hal_stats_channel_info_t{}. */ typedef struct xge_hal_stats_t { - /* handles */ - xge_hal_device_h devh; - dma_addr_t dma_addr; - pci_dma_h hw_info_dmah; - pci_dma_acc_h hw_info_dma_acch; + /* handles */ + xge_hal_device_h devh; + dma_addr_t dma_addr; + pci_dma_h hw_info_dmah; + pci_dma_acc_h hw_info_dma_acch; - /* HAL device hardware statistics */ - xge_hal_stats_hw_info_t *hw_info; - xge_hal_stats_hw_info_t hw_info_saved; - xge_hal_stats_hw_info_t hw_info_latest; + /* HAL device hardware statistics */ + xge_hal_stats_hw_info_t *hw_info; + xge_hal_stats_hw_info_t hw_info_saved; + xge_hal_stats_hw_info_t hw_info_latest; /* HAL device hardware statistics for XFRAME ER */ - xge_hal_stats_pcim_info_t *pcim_info; - xge_hal_stats_pcim_info_t *pcim_info_saved; - xge_hal_stats_pcim_info_t *pcim_info_latest; + xge_hal_stats_pcim_info_t *pcim_info; + xge_hal_stats_pcim_info_t *pcim_info_saved; + xge_hal_stats_pcim_info_t *pcim_info_latest; - /* HAL device "soft" stats */ + /* HAL device "soft" stats */ xge_hal_stats_sw_err_t sw_dev_err_stats; xge_hal_stats_device_info_t sw_dev_info_stats; - /* flags */ - int is_initialized; - int is_enabled; + /* flags */ + int is_initialized; + int is_enabled; } xge_hal_stats_t; /* ========================== STATS PRIVATE API ========================= */ xge_hal_status_e __hal_stats_initialize(xge_hal_stats_t *stats, - xge_hal_device_h devh); + xge_hal_device_h devh); void __hal_stats_terminate(xge_hal_stats_t *stats); @@ -1582,16 +1545,16 @@ void __hal_stats_soft_reset(xge_hal_device_h devh, int reset_all); /* ========================== STATS PUBLIC API ========================= */ xge_hal_status_e xge_hal_stats_hw(xge_hal_device_h devh, - xge_hal_stats_hw_info_t **hw_info); + xge_hal_stats_hw_info_t **hw_info); xge_hal_status_e xge_hal_stats_pcim(xge_hal_device_h devh, - xge_hal_stats_pcim_info_t **pcim_info); + xge_hal_stats_pcim_info_t **pcim_info); xge_hal_status_e xge_hal_stats_device(xge_hal_device_h devh, - xge_hal_stats_device_info_t **device_info); + xge_hal_stats_device_info_t **device_info); xge_hal_status_e xge_hal_stats_channel(xge_hal_channel_h channelh, - xge_hal_stats_channel_info_t **channel_info); + xge_hal_stats_channel_info_t **channel_info); xge_hal_status_e xge_hal_stats_reset(xge_hal_device_h devh); diff --git a/sys/dev/nxge/include/xgehal-types.h b/sys/dev/nxge/include/xgehal-types.h index ec1942b..58dd091 100644 --- a/sys/dev/nxge/include/xgehal-types.h +++ b/sys/dev/nxge/include/xgehal-types.h @@ -26,14 +26,6 @@ * $FreeBSD$ */ -/* - * FileName : xgehal-types.h - * - * Description: HAL commonly used types and enumerations - * - * Created: 19 May 2004 - */ - #ifndef XGE_HAL_TYPES_H #define XGE_HAL_TYPES_H @@ -44,44 +36,44 @@ __EXTERN_BEGIN_DECLS /* * BIT(loc) - set bit at offset */ -#define BIT(loc) (0x8000000000000000ULL >> (loc)) +#define BIT(loc) (0x8000000000000000ULL >> (loc)) /* * vBIT(val, loc, sz) - set bits at offset */ -#define vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) -#define vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) +#define vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) +#define vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) /* * bVALx(bits, loc) - Get the value of x bits at location */ -#define bVAL1(bits, loc) ((((u64)bits) >> (64-(loc+1))) & 0x1) -#define bVAL2(bits, loc) ((((u64)bits) >> (64-(loc+2))) & 0x3) -#define bVAL3(bits, loc) ((((u64)bits) >> (64-(loc+3))) & 0x7) -#define bVAL4(bits, loc) ((((u64)bits) >> (64-(loc+4))) & 0xF) -#define bVAL5(bits, loc) ((((u64)bits) >> (64-(loc+5))) & 0x1F) -#define bVAL6(bits, loc) ((((u64)bits) >> (64-(loc+6))) & 0x3F) -#define bVAL7(bits, loc) ((((u64)bits) >> (64-(loc+7))) & 0x7F) -#define bVAL8(bits, loc) ((((u64)bits) >> (64-(loc+8))) & 0xFF) -#define bVAL12(bits, loc) ((((u64)bits) >> (64-(loc+12))) & 0xFFF) -#define bVAL14(bits, loc) ((((u64)bits) >> (64-(loc+14))) & 0x3FFF) -#define bVAL16(bits, loc) ((((u64)bits) >> (64-(loc+16))) & 0xFFFF) -#define bVAL20(bits, loc) ((((u64)bits) >> (64-(loc+20))) & 0xFFFFF) -#define bVAL22(bits, loc) ((((u64)bits) >> (64-(loc+22))) & 0x3FFFFF) -#define bVAL24(bits, loc) ((((u64)bits) >> (64-(loc+24))) & 0xFFFFFF) -#define bVAL28(bits, loc) ((((u64)bits) >> (64-(loc+28))) & 0xFFFFFFF) -#define bVAL32(bits, loc) ((((u64)bits) >> (64-(loc+32))) & 0xFFFFFFFF) -#define bVAL36(bits, loc) ((((u64)bits) >> (64-(loc+36))) & 0xFFFFFFFFF) -#define bVAL40(bits, loc) ((((u64)bits) >> (64-(loc+40))) & 0xFFFFFFFFFF) -#define bVAL44(bits, loc) ((((u64)bits) >> (64-(loc+44))) & 0xFFFFFFFFFFF) -#define bVAL48(bits, loc) ((((u64)bits) >> (64-(loc+48))) & 0xFFFFFFFFFFFF) -#define bVAL52(bits, loc) ((((u64)bits) >> (64-(loc+52))) & 0xFFFFFFFFFFFFF) -#define bVAL56(bits, loc) ((((u64)bits) >> (64-(loc+56))) & 0xFFFFFFFFFFFFFF) -#define bVAL60(bits, loc) ((((u64)bits) >> (64-(loc+60))) & 0xFFFFFFFFFFFFFFF) - -#define XGE_HAL_BASE_INF 100 -#define XGE_HAL_BASE_ERR 200 -#define XGE_HAL_BASE_BADCFG 300 +#define bVAL1(bits, loc) ((((u64)bits) >> (64-(loc+1))) & 0x1) +#define bVAL2(bits, loc) ((((u64)bits) >> (64-(loc+2))) & 0x3) +#define bVAL3(bits, loc) ((((u64)bits) >> (64-(loc+3))) & 0x7) +#define bVAL4(bits, loc) ((((u64)bits) >> (64-(loc+4))) & 0xF) +#define bVAL5(bits, loc) ((((u64)bits) >> (64-(loc+5))) & 0x1F) +#define bVAL6(bits, loc) ((((u64)bits) >> (64-(loc+6))) & 0x3F) +#define bVAL7(bits, loc) ((((u64)bits) >> (64-(loc+7))) & 0x7F) +#define bVAL8(bits, loc) ((((u64)bits) >> (64-(loc+8))) & 0xFF) +#define bVAL12(bits, loc) ((((u64)bits) >> (64-(loc+12))) & 0xFFF) +#define bVAL14(bits, loc) ((((u64)bits) >> (64-(loc+14))) & 0x3FFF) +#define bVAL16(bits, loc) ((((u64)bits) >> (64-(loc+16))) & 0xFFFF) +#define bVAL20(bits, loc) ((((u64)bits) >> (64-(loc+20))) & 0xFFFFF) +#define bVAL22(bits, loc) ((((u64)bits) >> (64-(loc+22))) & 0x3FFFFF) +#define bVAL24(bits, loc) ((((u64)bits) >> (64-(loc+24))) & 0xFFFFFF) +#define bVAL28(bits, loc) ((((u64)bits) >> (64-(loc+28))) & 0xFFFFFFF) +#define bVAL32(bits, loc) ((((u64)bits) >> (64-(loc+32))) & 0xFFFFFFFF) +#define bVAL36(bits, loc) ((((u64)bits) >> (64-(loc+36))) & 0xFFFFFFFFF) +#define bVAL40(bits, loc) ((((u64)bits) >> (64-(loc+40))) & 0xFFFFFFFFFF) +#define bVAL44(bits, loc) ((((u64)bits) >> (64-(loc+44))) & 0xFFFFFFFFFFF) +#define bVAL48(bits, loc) ((((u64)bits) >> (64-(loc+48))) & 0xFFFFFFFFFFFF) +#define bVAL52(bits, loc) ((((u64)bits) >> (64-(loc+52))) & 0xFFFFFFFFFFFFF) +#define bVAL56(bits, loc) ((((u64)bits) >> (64-(loc+56))) & 0xFFFFFFFFFFFFFF) +#define bVAL60(bits, loc) ((((u64)bits) >> (64-(loc+60))) & 0xFFFFFFFFFFFFFFF) + +#define XGE_HAL_BASE_INF 100 +#define XGE_HAL_BASE_ERR 200 +#define XGE_HAL_BASE_BADCFG 300 #define XGE_HAL_ALL_FOXES 0xFFFFFFFFFFFFFFFFULL @@ -356,176 +348,176 @@ __EXTERN_BEGIN_DECLS * */ typedef enum xge_hal_status_e { - XGE_HAL_OK = 0, - XGE_HAL_FAIL = 1, - XGE_HAL_COMPLETIONS_REMAIN = 2, + XGE_HAL_OK = 0, + XGE_HAL_FAIL = 1, + XGE_HAL_COMPLETIONS_REMAIN = 2, XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS = XGE_HAL_BASE_INF + 1, - XGE_HAL_INF_OUT_OF_DESCRIPTORS = XGE_HAL_BASE_INF + 2, - XGE_HAL_INF_CHANNEL_IS_NOT_READY = XGE_HAL_BASE_INF + 3, - XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING = XGE_HAL_BASE_INF + 4, - XGE_HAL_INF_STATS_IS_NOT_READY = XGE_HAL_BASE_INF + 5, - XGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS = XGE_HAL_BASE_INF + 6, - XGE_HAL_INF_IRQ_POLLING_CONTINUE = XGE_HAL_BASE_INF + 7, - XGE_HAL_INF_LRO_BEGIN = XGE_HAL_BASE_INF + 8, - XGE_HAL_INF_LRO_CONT = XGE_HAL_BASE_INF + 9, - XGE_HAL_INF_LRO_UNCAPABLE = XGE_HAL_BASE_INF + 10, - XGE_HAL_INF_LRO_END_1 = XGE_HAL_BASE_INF + 11, - XGE_HAL_INF_LRO_END_2 = XGE_HAL_BASE_INF + 12, - XGE_HAL_INF_LRO_END_3 = XGE_HAL_BASE_INF + 13, - XGE_HAL_INF_LRO_SESSIONS_XCDED = XGE_HAL_BASE_INF + 14, - XGE_HAL_INF_NOT_ENOUGH_HW_CQES = XGE_HAL_BASE_INF + 15, - XGE_HAL_ERR_DRIVER_NOT_INITIALIZED = XGE_HAL_BASE_ERR + 1, - XGE_HAL_ERR_OUT_OF_MEMORY = XGE_HAL_BASE_ERR + 4, - XGE_HAL_ERR_CHANNEL_NOT_FOUND = XGE_HAL_BASE_ERR + 5, - XGE_HAL_ERR_WRONG_IRQ = XGE_HAL_BASE_ERR + 6, - XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES = XGE_HAL_BASE_ERR + 7, - XGE_HAL_ERR_SWAPPER_CTRL = XGE_HAL_BASE_ERR + 8, - XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT = XGE_HAL_BASE_ERR + 9, - XGE_HAL_ERR_INVALID_MTU_SIZE = XGE_HAL_BASE_ERR + 10, - XGE_HAL_ERR_OUT_OF_MAPPING = XGE_HAL_BASE_ERR + 11, - XGE_HAL_ERR_BAD_SUBSYSTEM_ID = XGE_HAL_BASE_ERR + 12, - XGE_HAL_ERR_INVALID_BAR_ID = XGE_HAL_BASE_ERR + 13, - XGE_HAL_ERR_INVALID_OFFSET = XGE_HAL_BASE_ERR + 14, - XGE_HAL_ERR_INVALID_DEVICE = XGE_HAL_BASE_ERR + 15, - XGE_HAL_ERR_OUT_OF_SPACE = XGE_HAL_BASE_ERR + 16, - XGE_HAL_ERR_INVALID_VALUE_BIT_SIZE = XGE_HAL_BASE_ERR + 17, - XGE_HAL_ERR_VERSION_CONFLICT = XGE_HAL_BASE_ERR + 18, - XGE_HAL_ERR_INVALID_MAC_ADDRESS = XGE_HAL_BASE_ERR + 19, - XGE_HAL_ERR_BAD_DEVICE_ID = XGE_HAL_BASE_ERR + 20, - XGE_HAL_ERR_OUT_ALIGNED_FRAGS = XGE_HAL_BASE_ERR + 21, - XGE_HAL_ERR_DEVICE_NOT_INITIALIZED = XGE_HAL_BASE_ERR + 22, - XGE_HAL_ERR_SPDM_NOT_ENABLED = XGE_HAL_BASE_ERR + 23, - XGE_HAL_ERR_SPDM_TABLE_FULL = XGE_HAL_BASE_ERR + 24, - XGE_HAL_ERR_SPDM_INVALID_ENTRY = XGE_HAL_BASE_ERR + 25, - XGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND = XGE_HAL_BASE_ERR + 26, + XGE_HAL_INF_OUT_OF_DESCRIPTORS = XGE_HAL_BASE_INF + 2, + XGE_HAL_INF_CHANNEL_IS_NOT_READY = XGE_HAL_BASE_INF + 3, + XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING = XGE_HAL_BASE_INF + 4, + XGE_HAL_INF_STATS_IS_NOT_READY = XGE_HAL_BASE_INF + 5, + XGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS = XGE_HAL_BASE_INF + 6, + XGE_HAL_INF_IRQ_POLLING_CONTINUE = XGE_HAL_BASE_INF + 7, + XGE_HAL_INF_LRO_BEGIN = XGE_HAL_BASE_INF + 8, + XGE_HAL_INF_LRO_CONT = XGE_HAL_BASE_INF + 9, + XGE_HAL_INF_LRO_UNCAPABLE = XGE_HAL_BASE_INF + 10, + XGE_HAL_INF_LRO_END_1 = XGE_HAL_BASE_INF + 11, + XGE_HAL_INF_LRO_END_2 = XGE_HAL_BASE_INF + 12, + XGE_HAL_INF_LRO_END_3 = XGE_HAL_BASE_INF + 13, + XGE_HAL_INF_LRO_SESSIONS_XCDED = XGE_HAL_BASE_INF + 14, + XGE_HAL_INF_NOT_ENOUGH_HW_CQES = XGE_HAL_BASE_INF + 15, + XGE_HAL_ERR_DRIVER_NOT_INITIALIZED = XGE_HAL_BASE_ERR + 1, + XGE_HAL_ERR_OUT_OF_MEMORY = XGE_HAL_BASE_ERR + 4, + XGE_HAL_ERR_CHANNEL_NOT_FOUND = XGE_HAL_BASE_ERR + 5, + XGE_HAL_ERR_WRONG_IRQ = XGE_HAL_BASE_ERR + 6, + XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES = XGE_HAL_BASE_ERR + 7, + XGE_HAL_ERR_SWAPPER_CTRL = XGE_HAL_BASE_ERR + 8, + XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT = XGE_HAL_BASE_ERR + 9, + XGE_HAL_ERR_INVALID_MTU_SIZE = XGE_HAL_BASE_ERR + 10, + XGE_HAL_ERR_OUT_OF_MAPPING = XGE_HAL_BASE_ERR + 11, + XGE_HAL_ERR_BAD_SUBSYSTEM_ID = XGE_HAL_BASE_ERR + 12, + XGE_HAL_ERR_INVALID_BAR_ID = XGE_HAL_BASE_ERR + 13, + XGE_HAL_ERR_INVALID_OFFSET = XGE_HAL_BASE_ERR + 14, + XGE_HAL_ERR_INVALID_DEVICE = XGE_HAL_BASE_ERR + 15, + XGE_HAL_ERR_OUT_OF_SPACE = XGE_HAL_BASE_ERR + 16, + XGE_HAL_ERR_INVALID_VALUE_BIT_SIZE = XGE_HAL_BASE_ERR + 17, + XGE_HAL_ERR_VERSION_CONFLICT = XGE_HAL_BASE_ERR + 18, + XGE_HAL_ERR_INVALID_MAC_ADDRESS = XGE_HAL_BASE_ERR + 19, + XGE_HAL_ERR_BAD_DEVICE_ID = XGE_HAL_BASE_ERR + 20, + XGE_HAL_ERR_OUT_ALIGNED_FRAGS = XGE_HAL_BASE_ERR + 21, + XGE_HAL_ERR_DEVICE_NOT_INITIALIZED = XGE_HAL_BASE_ERR + 22, + XGE_HAL_ERR_SPDM_NOT_ENABLED = XGE_HAL_BASE_ERR + 23, + XGE_HAL_ERR_SPDM_TABLE_FULL = XGE_HAL_BASE_ERR + 24, + XGE_HAL_ERR_SPDM_INVALID_ENTRY = XGE_HAL_BASE_ERR + 25, + XGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND = XGE_HAL_BASE_ERR + 26, XGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT= XGE_HAL_BASE_ERR + 27, - XGE_HAL_ERR_INVALID_PCI_INFO = XGE_HAL_BASE_ERR + 28, - XGE_HAL_ERR_CRITICAL = XGE_HAL_BASE_ERR + 29, - XGE_HAL_ERR_RESET_FAILED = XGE_HAL_BASE_ERR + 30, - XGE_HAL_ERR_TOO_MANY = XGE_HAL_BASE_ERR + 32, - XGE_HAL_ERR_PKT_DROP = XGE_HAL_BASE_ERR + 33, - - XGE_HAL_BADCFG_TX_URANGE_A = XGE_HAL_BASE_BADCFG + 1, - XGE_HAL_BADCFG_TX_UFC_A = XGE_HAL_BASE_BADCFG + 2, - XGE_HAL_BADCFG_TX_URANGE_B = XGE_HAL_BASE_BADCFG + 3, - XGE_HAL_BADCFG_TX_UFC_B = XGE_HAL_BASE_BADCFG + 4, - XGE_HAL_BADCFG_TX_URANGE_C = XGE_HAL_BASE_BADCFG + 5, - XGE_HAL_BADCFG_TX_UFC_C = XGE_HAL_BASE_BADCFG + 6, - XGE_HAL_BADCFG_TX_UFC_D = XGE_HAL_BASE_BADCFG + 8, - XGE_HAL_BADCFG_TX_TIMER_VAL = XGE_HAL_BASE_BADCFG + 9, - XGE_HAL_BADCFG_TX_TIMER_CI_EN = XGE_HAL_BASE_BADCFG + 10, - XGE_HAL_BADCFG_RX_URANGE_A = XGE_HAL_BASE_BADCFG + 11, - XGE_HAL_BADCFG_RX_UFC_A = XGE_HAL_BASE_BADCFG + 12, - XGE_HAL_BADCFG_RX_URANGE_B = XGE_HAL_BASE_BADCFG + 13, - XGE_HAL_BADCFG_RX_UFC_B = XGE_HAL_BASE_BADCFG + 14, - XGE_HAL_BADCFG_RX_URANGE_C = XGE_HAL_BASE_BADCFG + 15, - XGE_HAL_BADCFG_RX_UFC_C = XGE_HAL_BASE_BADCFG + 16, - XGE_HAL_BADCFG_RX_UFC_D = XGE_HAL_BASE_BADCFG + 17, - XGE_HAL_BADCFG_RX_TIMER_VAL = XGE_HAL_BASE_BADCFG + 18, - XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH= XGE_HAL_BASE_BADCFG + 19, + XGE_HAL_ERR_INVALID_PCI_INFO = XGE_HAL_BASE_ERR + 28, + XGE_HAL_ERR_CRITICAL = XGE_HAL_BASE_ERR + 29, + XGE_HAL_ERR_RESET_FAILED = XGE_HAL_BASE_ERR + 30, + XGE_HAL_ERR_TOO_MANY = XGE_HAL_BASE_ERR + 32, + XGE_HAL_ERR_PKT_DROP = XGE_HAL_BASE_ERR + 33, + + XGE_HAL_BADCFG_TX_URANGE_A = XGE_HAL_BASE_BADCFG + 1, + XGE_HAL_BADCFG_TX_UFC_A = XGE_HAL_BASE_BADCFG + 2, + XGE_HAL_BADCFG_TX_URANGE_B = XGE_HAL_BASE_BADCFG + 3, + XGE_HAL_BADCFG_TX_UFC_B = XGE_HAL_BASE_BADCFG + 4, + XGE_HAL_BADCFG_TX_URANGE_C = XGE_HAL_BASE_BADCFG + 5, + XGE_HAL_BADCFG_TX_UFC_C = XGE_HAL_BASE_BADCFG + 6, + XGE_HAL_BADCFG_TX_UFC_D = XGE_HAL_BASE_BADCFG + 8, + XGE_HAL_BADCFG_TX_TIMER_VAL = XGE_HAL_BASE_BADCFG + 9, + XGE_HAL_BADCFG_TX_TIMER_CI_EN = XGE_HAL_BASE_BADCFG + 10, + XGE_HAL_BADCFG_RX_URANGE_A = XGE_HAL_BASE_BADCFG + 11, + XGE_HAL_BADCFG_RX_UFC_A = XGE_HAL_BASE_BADCFG + 12, + XGE_HAL_BADCFG_RX_URANGE_B = XGE_HAL_BASE_BADCFG + 13, + XGE_HAL_BADCFG_RX_UFC_B = XGE_HAL_BASE_BADCFG + 14, + XGE_HAL_BADCFG_RX_URANGE_C = XGE_HAL_BASE_BADCFG + 15, + XGE_HAL_BADCFG_RX_UFC_C = XGE_HAL_BASE_BADCFG + 16, + XGE_HAL_BADCFG_RX_UFC_D = XGE_HAL_BASE_BADCFG + 17, + XGE_HAL_BADCFG_RX_TIMER_VAL = XGE_HAL_BASE_BADCFG + 18, + XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH= XGE_HAL_BASE_BADCFG + 19, XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH = XGE_HAL_BASE_BADCFG + 20, - XGE_HAL_BADCFG_FIFO_QUEUE_INTR = XGE_HAL_BASE_BADCFG + 21, - XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS=XGE_HAL_BASE_BADCFG + 22, - XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS = XGE_HAL_BASE_BADCFG + 23, - XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE = XGE_HAL_BASE_BADCFG + 24, - XGE_HAL_BADCFG_RING_QUEUE_SIZE = XGE_HAL_BASE_BADCFG + 25, - XGE_HAL_BADCFG_BACKOFF_INTERVAL_US = XGE_HAL_BASE_BADCFG + 26, - XGE_HAL_BADCFG_MAX_FRM_LEN = XGE_HAL_BASE_BADCFG + 27, - XGE_HAL_BADCFG_RING_PRIORITY = XGE_HAL_BASE_BADCFG + 28, - XGE_HAL_BADCFG_TMAC_UTIL_PERIOD = XGE_HAL_BASE_BADCFG + 29, - XGE_HAL_BADCFG_RMAC_UTIL_PERIOD = XGE_HAL_BASE_BADCFG + 30, - XGE_HAL_BADCFG_RMAC_BCAST_EN = XGE_HAL_BASE_BADCFG + 31, - XGE_HAL_BADCFG_RMAC_HIGH_PTIME = XGE_HAL_BASE_BADCFG + 32, - XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3 = XGE_HAL_BASE_BADCFG +33, - XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7 = XGE_HAL_BASE_BADCFG + 34, - XGE_HAL_BADCFG_FIFO_FRAGS = XGE_HAL_BASE_BADCFG + 35, - XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD = XGE_HAL_BASE_BADCFG + 37, - XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE = XGE_HAL_BASE_BADCFG + 38, - XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE = XGE_HAL_BASE_BADCFG + 39, - XGE_HAL_BADCFG_MAX_MTU = XGE_HAL_BASE_BADCFG + 40, - XGE_HAL_BADCFG_ISR_POLLING_CNT = XGE_HAL_BASE_BADCFG + 41, - XGE_HAL_BADCFG_LATENCY_TIMER = XGE_HAL_BASE_BADCFG + 42, - XGE_HAL_BADCFG_MAX_SPLITS_TRANS = XGE_HAL_BASE_BADCFG + 43, - XGE_HAL_BADCFG_MMRB_COUNT = XGE_HAL_BASE_BADCFG + 44, - XGE_HAL_BADCFG_SHARED_SPLITS = XGE_HAL_BASE_BADCFG + 45, - XGE_HAL_BADCFG_STATS_REFRESH_TIME = XGE_HAL_BASE_BADCFG + 46, - XGE_HAL_BADCFG_PCI_FREQ_MHERZ = XGE_HAL_BASE_BADCFG + 47, - XGE_HAL_BADCFG_PCI_MODE = XGE_HAL_BASE_BADCFG + 48, - XGE_HAL_BADCFG_INTR_MODE = XGE_HAL_BASE_BADCFG + 49, - XGE_HAL_BADCFG_SCHED_TIMER_US = XGE_HAL_BASE_BADCFG + 50, - XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT = XGE_HAL_BASE_BADCFG + 51, - XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL = XGE_HAL_BASE_BADCFG + 52, - XGE_HAL_BADCFG_QUEUE_SIZE_MAX = XGE_HAL_BASE_BADCFG + 53, - XGE_HAL_BADCFG_RING_RTH_EN = XGE_HAL_BASE_BADCFG + 54, - XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS = XGE_HAL_BASE_BADCFG + 55, - XGE_HAL_BADCFG_TX_TIMER_AC_EN = XGE_HAL_BASE_BADCFG + 56, - XGE_HAL_BADCFG_RX_TIMER_AC_EN = XGE_HAL_BASE_BADCFG + 57, - XGE_HAL_BADCFG_RXUFCA_INTR_THRES = XGE_HAL_BASE_BADCFG + 58, - XGE_HAL_BADCFG_RXUFCA_LO_LIM = XGE_HAL_BASE_BADCFG + 59, - XGE_HAL_BADCFG_RXUFCA_HI_LIM = XGE_HAL_BASE_BADCFG + 60, - XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD = XGE_HAL_BASE_BADCFG + 61, - XGE_HAL_BADCFG_TRACEBUF_SIZE = XGE_HAL_BASE_BADCFG + 62, - XGE_HAL_BADCFG_LINK_VALID_CNT = XGE_HAL_BASE_BADCFG + 63, - XGE_HAL_BADCFG_LINK_RETRY_CNT = XGE_HAL_BASE_BADCFG + 64, - XGE_HAL_BADCFG_LINK_STABILITY_PERIOD = XGE_HAL_BASE_BADCFG + 65, + XGE_HAL_BADCFG_FIFO_QUEUE_INTR = XGE_HAL_BASE_BADCFG + 21, + XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS=XGE_HAL_BASE_BADCFG + 22, + XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS = XGE_HAL_BASE_BADCFG + 23, + XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE = XGE_HAL_BASE_BADCFG + 24, + XGE_HAL_BADCFG_RING_QUEUE_SIZE = XGE_HAL_BASE_BADCFG + 25, + XGE_HAL_BADCFG_BACKOFF_INTERVAL_US = XGE_HAL_BASE_BADCFG + 26, + XGE_HAL_BADCFG_MAX_FRM_LEN = XGE_HAL_BASE_BADCFG + 27, + XGE_HAL_BADCFG_RING_PRIORITY = XGE_HAL_BASE_BADCFG + 28, + XGE_HAL_BADCFG_TMAC_UTIL_PERIOD = XGE_HAL_BASE_BADCFG + 29, + XGE_HAL_BADCFG_RMAC_UTIL_PERIOD = XGE_HAL_BASE_BADCFG + 30, + XGE_HAL_BADCFG_RMAC_BCAST_EN = XGE_HAL_BASE_BADCFG + 31, + XGE_HAL_BADCFG_RMAC_HIGH_PTIME = XGE_HAL_BASE_BADCFG + 32, + XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3 = XGE_HAL_BASE_BADCFG +33, + XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7 = XGE_HAL_BASE_BADCFG + 34, + XGE_HAL_BADCFG_FIFO_FRAGS = XGE_HAL_BASE_BADCFG + 35, + XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD = XGE_HAL_BASE_BADCFG + 37, + XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE = XGE_HAL_BASE_BADCFG + 38, + XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE = XGE_HAL_BASE_BADCFG + 39, + XGE_HAL_BADCFG_MAX_MTU = XGE_HAL_BASE_BADCFG + 40, + XGE_HAL_BADCFG_ISR_POLLING_CNT = XGE_HAL_BASE_BADCFG + 41, + XGE_HAL_BADCFG_LATENCY_TIMER = XGE_HAL_BASE_BADCFG + 42, + XGE_HAL_BADCFG_MAX_SPLITS_TRANS = XGE_HAL_BASE_BADCFG + 43, + XGE_HAL_BADCFG_MMRB_COUNT = XGE_HAL_BASE_BADCFG + 44, + XGE_HAL_BADCFG_SHARED_SPLITS = XGE_HAL_BASE_BADCFG + 45, + XGE_HAL_BADCFG_STATS_REFRESH_TIME = XGE_HAL_BASE_BADCFG + 46, + XGE_HAL_BADCFG_PCI_FREQ_MHERZ = XGE_HAL_BASE_BADCFG + 47, + XGE_HAL_BADCFG_PCI_MODE = XGE_HAL_BASE_BADCFG + 48, + XGE_HAL_BADCFG_INTR_MODE = XGE_HAL_BASE_BADCFG + 49, + XGE_HAL_BADCFG_SCHED_TIMER_US = XGE_HAL_BASE_BADCFG + 50, + XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT = XGE_HAL_BASE_BADCFG + 51, + XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL = XGE_HAL_BASE_BADCFG + 52, + XGE_HAL_BADCFG_QUEUE_SIZE_MAX = XGE_HAL_BASE_BADCFG + 53, + XGE_HAL_BADCFG_RING_RTH_EN = XGE_HAL_BASE_BADCFG + 54, + XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS = XGE_HAL_BASE_BADCFG + 55, + XGE_HAL_BADCFG_TX_TIMER_AC_EN = XGE_HAL_BASE_BADCFG + 56, + XGE_HAL_BADCFG_RX_TIMER_AC_EN = XGE_HAL_BASE_BADCFG + 57, + XGE_HAL_BADCFG_RXUFCA_INTR_THRES = XGE_HAL_BASE_BADCFG + 58, + XGE_HAL_BADCFG_RXUFCA_LO_LIM = XGE_HAL_BASE_BADCFG + 59, + XGE_HAL_BADCFG_RXUFCA_HI_LIM = XGE_HAL_BASE_BADCFG + 60, + XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD = XGE_HAL_BASE_BADCFG + 61, + XGE_HAL_BADCFG_TRACEBUF_SIZE = XGE_HAL_BASE_BADCFG + 62, + XGE_HAL_BADCFG_LINK_VALID_CNT = XGE_HAL_BASE_BADCFG + 63, + XGE_HAL_BADCFG_LINK_RETRY_CNT = XGE_HAL_BASE_BADCFG + 64, + XGE_HAL_BADCFG_LINK_STABILITY_PERIOD = XGE_HAL_BASE_BADCFG + 65, XGE_HAL_BADCFG_DEVICE_POLL_MILLIS = XGE_HAL_BASE_BADCFG + 66, - XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN = XGE_HAL_BASE_BADCFG + 67, - XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN = XGE_HAL_BASE_BADCFG + 68, - XGE_HAL_BADCFG_MEDIA = XGE_HAL_BASE_BADCFG + 69, - XGE_HAL_BADCFG_NO_ISR_EVENTS = XGE_HAL_BASE_BADCFG + 70, - XGE_HAL_BADCFG_RING_RTS_MAC_EN = XGE_HAL_BASE_BADCFG + 71, - XGE_HAL_BADCFG_LRO_SG_SIZE = XGE_HAL_BASE_BADCFG + 72, - XGE_HAL_BADCFG_LRO_FRM_LEN = XGE_HAL_BASE_BADCFG + 73, - XGE_HAL_BADCFG_WQE_NUM_ODS = XGE_HAL_BASE_BADCFG + 74, - XGE_HAL_BADCFG_BIMODAL_INTR = XGE_HAL_BASE_BADCFG + 75, - XGE_HAL_BADCFG_BIMODAL_TIMER_LO_US = XGE_HAL_BASE_BADCFG + 76, - XGE_HAL_BADCFG_BIMODAL_TIMER_HI_US = XGE_HAL_BASE_BADCFG + 77, - XGE_HAL_BADCFG_BIMODAL_XENA_NOT_ALLOWED = XGE_HAL_BASE_BADCFG + 78, - XGE_HAL_BADCFG_RTS_QOS_EN = XGE_HAL_BASE_BADCFG + 79, - XGE_HAL_BADCFG_FIFO_QUEUE_INTR_VECTOR = XGE_HAL_BASE_BADCFG + 80, - XGE_HAL_BADCFG_RING_QUEUE_INTR_VECTOR = XGE_HAL_BASE_BADCFG + 81, - XGE_HAL_BADCFG_RTS_PORT_EN = XGE_HAL_BASE_BADCFG + 82, - XGE_HAL_BADCFG_RING_RTS_PORT_EN = XGE_HAL_BASE_BADCFG + 83, - XGE_HAL_BADCFG_TRACEBUF_TIMESTAMP = XGE_HAL_BASE_BADCFG + 84, - XGE_HAL_EOF_TRACE_BUF = -1 + XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN = XGE_HAL_BASE_BADCFG + 67, + XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN = XGE_HAL_BASE_BADCFG + 68, + XGE_HAL_BADCFG_MEDIA = XGE_HAL_BASE_BADCFG + 69, + XGE_HAL_BADCFG_NO_ISR_EVENTS = XGE_HAL_BASE_BADCFG + 70, + XGE_HAL_BADCFG_RING_RTS_MAC_EN = XGE_HAL_BASE_BADCFG + 71, + XGE_HAL_BADCFG_LRO_SG_SIZE = XGE_HAL_BASE_BADCFG + 72, + XGE_HAL_BADCFG_LRO_FRM_LEN = XGE_HAL_BASE_BADCFG + 73, + XGE_HAL_BADCFG_WQE_NUM_ODS = XGE_HAL_BASE_BADCFG + 74, + XGE_HAL_BADCFG_BIMODAL_INTR = XGE_HAL_BASE_BADCFG + 75, + XGE_HAL_BADCFG_BIMODAL_TIMER_LO_US = XGE_HAL_BASE_BADCFG + 76, + XGE_HAL_BADCFG_BIMODAL_TIMER_HI_US = XGE_HAL_BASE_BADCFG + 77, + XGE_HAL_BADCFG_BIMODAL_XENA_NOT_ALLOWED = XGE_HAL_BASE_BADCFG + 78, + XGE_HAL_BADCFG_RTS_QOS_EN = XGE_HAL_BASE_BADCFG + 79, + XGE_HAL_BADCFG_FIFO_QUEUE_INTR_VECTOR = XGE_HAL_BASE_BADCFG + 80, + XGE_HAL_BADCFG_RING_QUEUE_INTR_VECTOR = XGE_HAL_BASE_BADCFG + 81, + XGE_HAL_BADCFG_RTS_PORT_EN = XGE_HAL_BASE_BADCFG + 82, + XGE_HAL_BADCFG_RING_RTS_PORT_EN = XGE_HAL_BASE_BADCFG + 83, + XGE_HAL_BADCFG_TRACEBUF_TIMESTAMP = XGE_HAL_BASE_BADCFG + 84, + XGE_HAL_EOF_TRACE_BUF = -1 } xge_hal_status_e; -#define XGE_HAL_ETH_ALEN 6 +#define XGE_HAL_ETH_ALEN 6 typedef u8 macaddr_t[XGE_HAL_ETH_ALEN]; -#define XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE 0x100 +#define XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE 0x100 /* frames sizes */ -#define XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE 14 -#define XGE_HAL_HEADER_802_2_SIZE 3 -#define XGE_HAL_HEADER_SNAP_SIZE 5 -#define XGE_HAL_HEADER_VLAN_SIZE 4 +#define XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE 14 +#define XGE_HAL_HEADER_802_2_SIZE 3 +#define XGE_HAL_HEADER_SNAP_SIZE 5 +#define XGE_HAL_HEADER_VLAN_SIZE 4 #define XGE_HAL_MAC_HEADER_MAX_SIZE \ - (XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE + \ - XGE_HAL_HEADER_802_2_SIZE + \ - XGE_HAL_HEADER_SNAP_SIZE) + (XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE + \ + XGE_HAL_HEADER_802_2_SIZE + \ + XGE_HAL_HEADER_SNAP_SIZE) -#define XGE_HAL_TCPIP_HEADER_MAX_SIZE (64 + 64) +#define XGE_HAL_TCPIP_HEADER_MAX_SIZE (64 + 64) /* 32bit alignments */ -#define XGE_HAL_HEADER_ETHERNET_II_802_3_ALIGN 2 -#define XGE_HAL_HEADER_802_2_SNAP_ALIGN 2 -#define XGE_HAL_HEADER_802_2_ALIGN 3 -#define XGE_HAL_HEADER_SNAP_ALIGN 1 +#define XGE_HAL_HEADER_ETHERNET_II_802_3_ALIGN 2 +#define XGE_HAL_HEADER_802_2_SNAP_ALIGN 2 +#define XGE_HAL_HEADER_802_2_ALIGN 3 +#define XGE_HAL_HEADER_SNAP_ALIGN 1 -#define XGE_HAL_L3_CKSUM_OK 0xFFFF -#define XGE_HAL_L4_CKSUM_OK 0xFFFF -#define XGE_HAL_MIN_MTU 46 -#define XGE_HAL_MAX_MTU 9600 -#define XGE_HAL_DEFAULT_MTU 1500 +#define XGE_HAL_L3_CKSUM_OK 0xFFFF +#define XGE_HAL_L4_CKSUM_OK 0xFFFF +#define XGE_HAL_MIN_MTU 46 +#define XGE_HAL_MAX_MTU 9600 +#define XGE_HAL_DEFAULT_MTU 1500 -#define XGE_HAL_SEGEMENT_OFFLOAD_MAX_SIZE 81920 +#define XGE_HAL_SEGEMENT_OFFLOAD_MAX_SIZE 81920 -#define XGE_HAL_PCISIZE_XENA 26 /* multiples of dword */ -#define XGE_HAL_PCISIZE_HERC 64 /* multiples of dword */ +#define XGE_HAL_PCISIZE_XENA 26 /* multiples of dword */ +#define XGE_HAL_PCISIZE_HERC 64 /* multiples of dword */ -#define XGE_HAL_MAX_MSIX_MESSAGES 64 +#define XGE_HAL_MAX_MSIX_MESSAGES 64 #define XGE_HAL_MAX_MSIX_MESSAGES_WITH_ADDR XGE_HAL_MAX_MSIX_MESSAGES * 2 /* Highest level interrupt blocks */ #define XGE_HAL_TX_PIC_INTR (0x0001<<0) @@ -541,17 +533,17 @@ typedef u8 macaddr_t[XGE_HAL_ETH_ALEN]; #define XGE_HAL_MC_INTR (0x0001<<10) #define XGE_HAL_SCHED_INTR (0x0001<<11) #define XGE_HAL_ALL_INTRS (XGE_HAL_TX_PIC_INTR | \ - XGE_HAL_TX_DMA_INTR | \ - XGE_HAL_TX_MAC_INTR | \ - XGE_HAL_TX_XGXS_INTR | \ - XGE_HAL_TX_TRAFFIC_INTR | \ - XGE_HAL_RX_PIC_INTR | \ - XGE_HAL_RX_DMA_INTR | \ - XGE_HAL_RX_MAC_INTR | \ - XGE_HAL_RX_XGXS_INTR | \ - XGE_HAL_RX_TRAFFIC_INTR | \ - XGE_HAL_MC_INTR | \ - XGE_HAL_SCHED_INTR) + XGE_HAL_TX_DMA_INTR | \ + XGE_HAL_TX_MAC_INTR | \ + XGE_HAL_TX_XGXS_INTR | \ + XGE_HAL_TX_TRAFFIC_INTR | \ + XGE_HAL_RX_PIC_INTR | \ + XGE_HAL_RX_DMA_INTR | \ + XGE_HAL_RX_MAC_INTR | \ + XGE_HAL_RX_XGXS_INTR | \ + XGE_HAL_RX_TRAFFIC_INTR | \ + XGE_HAL_MC_INTR | \ + XGE_HAL_SCHED_INTR) #define XGE_HAL_GEN_MASK_INTR (0x0001<<12) /* Interrupt masks for the general interrupt mask register */ @@ -570,7 +562,7 @@ typedef u8 macaddr_t[XGE_HAL_ETH_ALEN]; #define XGE_HAL_RXTRAFFIC_INT_M BIT(40) /* MSI level Interrupts */ -#define XGE_HAL_MAX_MSIX_VECTORS (16) +#define XGE_HAL_MAX_MSIX_VECTORS (16) typedef struct xge_hal_ipv4 { u32 addr; @@ -586,33 +578,22 @@ typedef union xge_hal_ipaddr_t { }xge_hal_ipaddr_t; /* DMA level Interrupts */ -#define XGE_HAL_TXDMA_PFC_INT_M BIT(0) +#define XGE_HAL_TXDMA_PFC_INT_M BIT(0) /* PFC block interrupts */ -#define XGE_HAL_PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO +#define XGE_HAL_PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */ /* basic handles */ typedef void* xge_hal_device_h; typedef void* xge_hal_dtr_h; typedef void* xge_hal_channel_h; -#ifdef XGEHAL_RNIC -typedef void* xge_hal_towi_h; -typedef void* xge_hal_hw_wqe_h; -typedef void* xge_hal_hw_cqe_h; -typedef void* xge_hal_lro_wqe_h; -typedef void* xge_hal_lro_cqe_h; -typedef void* xge_hal_up_msg_h; -typedef void* xge_hal_down_msg_h; -typedef void* xge_hal_channel_callback_fh; -typedef void* xge_hal_msg_queueh; -typedef void* xge_hal_pblist_h; -#endif + /* * I2C device id. Used in I2C control register for accessing EEPROM device * memory. */ -#define XGE_DEV_ID 5 +#define XGE_DEV_ID 5 typedef enum xge_hal_xpak_alarm_type_e { XGE_HAL_XPAK_ALARM_EXCESS_TEMP = 1, diff --git a/sys/dev/nxge/include/xgehal.h b/sys/dev/nxge/include/xgehal.h index 4c3c08a..c864512 100644 --- a/sys/dev/nxge/include/xgehal.h +++ b/sys/dev/nxge/include/xgehal.h @@ -26,15 +26,6 @@ * $FreeBSD$ */ -/* - * FileName : xgehal.h - * - * Description: Consolidated header. Upper layers should include it to - * avoid include order problems. - * - * Created: 14 May 2004 - */ - #ifndef XGE_HAL_H #define XGE_HAL_H |
