Neterion Xframe 10GbE Server/Storage adapter driver.

The nxge driver provides support for Neterion Xframe-I and Xframe-II
adapters. The driver supports TCP Segmentation Offload (TSO/LSO),
Jumbo frames (5 buffer mode), Header separation (2 and 3 Receive
buffer modes), VLAN, and Promiscuous mode.

Submitted by:	Neterion
Reviewed by:	rwatson
Approved by:	re (kensmith)

22 files changed, 9868 insertions, 0 deletions

diff --git a/sys/dev/nxge/include/build-version.h b/sys/dev/nxge/include/build-version.h
new file mode 100644
index 0000000..b9b5e00
--- /dev/null
+++ b/sys/dev/nxge/include/build-version.h
@@ -0,0 +1,6 @@
+/* $FreeBSD$ */
+#ifndef BUILD_VERSION_H
+#define BUILD_VERSION_H
+/* Do not edit! Automatically generated when released.*/
+#define GENERATED_BUILD_VERSION "10294"
+#endif /* BUILD_VERSION_H */
diff --git a/sys/dev/nxge/include/version.h b/sys/dev/nxge/include/version.h
new file mode 100644
index 0000000..0a212f4
--- /dev/null
+++ b/sys/dev/nxge/include/version.h
@@ -0,0 +1,53 @@
+/*-
+ * Copyright (c) 2002-2007 Neterion, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ *  FileName :    version.h
+ *
+ *  Description:  versioning file
+ *
+ *  Created:      3 September 2004
+ */
+
+#ifndef VERSION_H
+#define VERSION_H
+
+#include <dev/nxge/include/build-version.h>
+
+#define XGE_HAL_VERSION_MAJOR	"2"
+#define XGE_HAL_VERSION_MINOR   "5"
+#define XGE_HAL_VERSION_FIX	"0"
+#define XGE_HAL_VERSION_BUILD	GENERATED_BUILD_VERSION
+#define XGE_HAL_VERSION XGE_HAL_VERSION_MAJOR"."XGE_HAL_VERSION_MINOR"."\
+			XGE_HAL_VERSION_FIX"."XGE_HAL_VERSION_BUILD
+#define XGE_HAL_DESC	XGE_DRIVER_NAME" v."XGE_HAL_VERSION
+
+/* Link Layer versioning */
+#include <dev/nxge/xgell-version.h>
+
+#endif /* VERSION_H */
diff --git a/sys/dev/nxge/include/xge-debug.h b/sys/dev/nxge/include/xge-debug.h
new file mode 100644
index 0000000..a4efbcb
--- /dev/null
+++ b/sys/dev/nxge/include/xge-debug.h
@@ -0,0 +1,568 @@
+/*-
+ * Copyright (c) 2002-2007 Neterion, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ *  FileName :    xge-debug.h
+ *
+ *  Description:  debug facilities
+ *
+ *  Created:      6 May 2004
+ */
+
+#ifndef XGE_DEBUG_H
+#define XGE_DEBUG_H
+
+#include <dev/nxge/include/xge-os-pal.h>
+
+__EXTERN_BEGIN_DECLS
+
+/*
+ * __FUNCTION__ is, together with __PRETTY_FUNCTION__ or something similar,
+ * a gcc extension. we'll have to #ifdef around that, and provide some
+ * meaningful replacement for those, so to make some gcc versions happier
+ */
+#ifndef __func__
+#ifdef __FUNCTION__
+#define __func__ __FUNCTION__
+#endif
+#endif
+
+
+#ifdef XGE_DEBUG_FP
+#define XGE_DEBUG_FP_DEVICE	0x1
+#define XGE_DEBUG_FP_CHANNEL	0x2
+#define XGE_DEBUG_FP_FIFO	0x4
+#define XGE_DEBUG_FP_RING	0x8
+#endif
+
+/**
+ * enum xge_debug_level_e
+ * @XGE_NONE: debug disabled
+ * @XGE_ERR: all errors going to be logged out
+ * @XGE_TRACE: all errors plus all kind of verbose tracing print outs
+ *                 going to be logged out. Very noisy.
+ *
+ * This enumeration going to be used to switch between different
+ * debug levels during runtime if DEBUG macro defined during
+ * compilation. If DEBUG macro not defined than code will be
+ * compiled out.
+ */
+typedef enum xge_debug_level_e {
+	XGE_NONE   = 0,
+	XGE_TRACE  = 1,
+	XGE_ERR    = 2,
+} xge_debug_level_e;
+
+#define XGE_DEBUG_MODULE_MASK_DEF	0x30000030
+#define XGE_DEBUG_LEVEL_DEF		XGE_ERR
+
+#if defined(XGE_DEBUG_TRACE_MASK) || defined(XGE_DEBUG_ERR_MASK)
+
+extern unsigned long *g_module_mask;
+extern int *g_level;
+
+#ifndef XGE_DEBUG_TRACE_MASK
+#define XGE_DEBUG_TRACE_MASK 0
+#endif
+
+#ifndef XGE_DEBUG_ERR_MASK
+#define XGE_DEBUG_ERR_MASK 0
+#endif
+
+/*
+ * @XGE_COMPONENT_HAL_CONFIG: do debug for xge core config module
+ * @XGE_COMPONENT_HAL_FIFO: do debug for xge core fifo module
+ * @XGE_COMPONENT_HAL_RING: do debug for xge core ring module
+ * @XGE_COMPONENT_HAL_CHANNEL: do debug for xge core channel module
+ * @XGE_COMPONENT_HAL_DEVICE: do debug for xge core device module
+ * @XGE_COMPONENT_HAL_DMQ: do debug for xge core DMQ module
+ * @XGE_COMPONENT_HAL_UMQ: do debug for xge core UMQ module
+ * @XGE_COMPONENT_HAL_SQ: do debug for xge core SQ module
+ * @XGE_COMPONENT_HAL_SRQ: do debug for xge core SRQ module
+ * @XGE_COMPONENT_HAL_CQRQ: do debug for xge core CRQ module
+ * @XGE_COMPONENT_HAL_POOL: do debug for xge core memory pool module
+ * @XGE_COMPONENT_HAL_BITMAP: do debug for xge core BITMAP module
+ * @XGE_COMPONENT_CORE: do debug for xge KMA core module
+ * @XGE_COMPONENT_OSDEP: do debug for xge KMA os dependent parts
+ * @XGE_COMPONENT_LL: do debug for xge link layer module
+ * @XGE_COMPONENT_ALL: activate debug for all modules with no exceptions
+ *
+ * This enumeration going to be used to distinguish modules
+ * or libraries during compilation and runtime.  Makefile must declare
+ * XGE_DEBUG_MODULE_MASK macro and set it to proper value.
+ */
+#define XGE_COMPONENT_HAL_CONFIG		0x00000001
+#define	XGE_COMPONENT_HAL_FIFO			0x00000002
+#define	XGE_COMPONENT_HAL_RING			0x00000004
+#define	XGE_COMPONENT_HAL_CHANNEL		0x00000008
+#define	XGE_COMPONENT_HAL_DEVICE		0x00000010
+#define	XGE_COMPONENT_HAL_MM			0x00000020
+#define	XGE_COMPONENT_HAL_QUEUE	        0x00000040
+#define	XGE_COMPONENT_HAL_INTERRUPT     0x00000080
+#define	XGE_COMPONENT_HAL_STATS	        0x00000100
+#ifdef XGEHAL_RNIC
+#define	XGE_COMPONENT_HAL_DMQ	        0x00000200
+#define	XGE_COMPONENT_HAL_UMQ	        0x00000400
+#define	XGE_COMPONENT_HAL_SQ	        0x00000800
+#define	XGE_COMPONENT_HAL_SRQ			0x00001000
+#define	XGE_COMPONENT_HAL_CQRQ			0x00002000
+#define	XGE_COMPONENT_HAL_POOL	        0x00004000
+#define	XGE_COMPONENT_HAL_BITMAP		0x00008000
+#endif
+
+	/* space for CORE_XXX */
+#define	XGE_COMPONENT_OSDEP			0x10000000
+#define	XGE_COMPONENT_LL			0x20000000
+#define	XGE_COMPONENT_ALL			0xffffffff
+
+#ifndef XGE_DEBUG_MODULE_MASK
+#error "XGE_DEBUG_MODULE_MASK macro must be defined for DEBUG mode..."
+#endif
+
+#ifndef __GNUC__
+#ifdef XGE_TRACE_INTO_CIRCULAR_ARR
+        #define xge_trace_aux(fmt) xge_os_vatrace(g_xge_os_tracebuf, fmt)
+#else
+        #define xge_trace_aux(fmt) xge_os_vaprintf(fmt)
+#endif
+
+/**
+ * xge_debug
+ * @level: level of debug verbosity.
+ * @fmt: printf like format string
+ *
+ * Provides logging facilities. Can be customized on per-module
+ * basis or/and with debug levels. Input parameters, except
+ * module and level, are the same as posix printf. This function
+ * may be compiled out if DEBUG macro was never defined.
+ * See also: xge_debug_level_e{}.
+ */
+#define xge_debug(module, level, fmt) { \
+if (((level >= XGE_TRACE && ((module & XGE_DEBUG_TRACE_MASK) == module)) || \
+    (level >= XGE_ERR && ((module & XGE_DEBUG_ERR_MASK) == module))) && \
+    level >= *g_level && module & *(unsigned int *)g_module_mask) { \
+                xge_trace_aux(fmt); \
+	} \
+}
+#else /* __GNUC__ */
+
+#ifdef XGE_TRACE_INTO_CIRCULAR_ARR
+        #define xge_trace_aux(fmt...) xge_os_trace(g_xge_os_tracebuf, fmt)
+#else
+        #define xge_trace_aux(fmt...) xge_os_printf(fmt)
+#endif
+
+#define xge_debug(module, level, fmt...) { \
+if (((level >= XGE_TRACE && ((module & XGE_DEBUG_TRACE_MASK) == module)) || \
+    (level >= XGE_ERR && ((module & XGE_DEBUG_ERR_MASK) == module))) && \
+    level >= *g_level && module & *(unsigned int *)g_module_mask) { \
+                xge_trace_aux(fmt); \
+	} \
+}
+#endif /* __GNUC__ */
+
+#if (XGE_COMPONENT_HAL_STATS & XGE_DEBUG_MODULE_MASK)
+#ifndef __GNUC__
+static inline void xge_debug_stats(xge_debug_level_e level, char *fmt, ...) {
+	u32 module = XGE_COMPONENT_HAL_STATS;
+	xge_debug(module, level, fmt);
+}
+#else /* __GNUC__ */
+#define xge_debug_stats(level, fmt...) \
+	xge_debug(XGE_COMPONENT_HAL_STATS, level, fmt)
+#endif /* __GNUC__ */
+#else
+#ifndef __GNUC__
+static inline void xge_debug_stats(xge_debug_level_e level, char *fmt, ...) {}
+#else /* __GNUC__ */
+#define xge_debug_stats(level, fmt...)
+#endif /* __GNUC__ */
+#endif
+
+/* Interrupt Related */
+#if (XGE_COMPONENT_HAL_INTERRUPT & XGE_DEBUG_MODULE_MASK)
+#ifndef __GNUC__
+static inline void xge_debug_interrupt(xge_debug_level_e level, char *fmt, ...) {
+	u32 module = XGE_COMPONENT_HAL_INTERRUPT;
+	xge_debug(module, level, fmt);
+}
+#else /* __GNUC__ */
+#define xge_debug_interrupt(level, fmt...) \
+	xge_debug(XGE_COMPONENT_HAL_INTERRUPT, level, fmt)
+#endif /* __GNUC__ */
+#else
+#ifndef __GNUC__
+static inline void xge_debug_interrupt(xge_debug_level_e level, char *fmt, ...) {}
+#else /* __GNUC__ */
+#define xge_debug_interrupt(level, fmt...)
+#endif /* __GNUC__ */
+#endif
+
+#if (XGE_COMPONENT_HAL_QUEUE & XGE_DEBUG_MODULE_MASK)
+#ifndef __GNUC__
+static inline void xge_debug_queue(xge_debug_level_e level, char *fmt, ...) {
+	u32 module = XGE_COMPONENT_HAL_QUEUE;
+	xge_debug(module, level, fmt);
+}
+#else /* __GNUC__ */
+#define xge_debug_queue(level, fmt...) \
+	xge_debug(XGE_COMPONENT_HAL_QUEUE, level, fmt)
+#endif /* __GNUC__ */
+#else
+#ifndef __GNUC__
+static inline void xge_debug_queue(xge_debug_level_e level, char *fmt,
+...) {}
+#else /* __GNUC__ */
+#define xge_debug_queue(level, fmt...)
+#endif /* __GNUC__ */
+#endif
+
+#if (XGE_COMPONENT_HAL_MM & XGE_DEBUG_MODULE_MASK)
+#ifndef __GNUC__
+static inline void xge_debug_mm(xge_debug_level_e level, char *fmt, ...)
+{
+	u32 module = XGE_COMPONENT_HAL_MM;
+	xge_debug(module, level, fmt);
+}
+#else /* __GNUC__ */
+#define xge_debug_mm(level, fmt...) \
+	xge_debug(XGE_COMPONENT_HAL_MM, level, fmt)
+#endif /* __GNUC__ */
+#else
+#ifndef __GNUC__
+static inline void xge_debug_mm(xge_debug_level_e level, char *fmt, ...)
+{}
+#else /* __GNUC__ */
+#define xge_debug_mm(level, fmt...)
+#endif /* __GNUC__ */
+#endif
+
+#if (XGE_COMPONENT_HAL_CONFIG & XGE_DEBUG_MODULE_MASK)
+#ifndef __GNUC__
+static inline void xge_debug_config(xge_debug_level_e level, char *fmt, ...) {
+	u32 module = XGE_COMPONENT_HAL_CONFIG;
+	xge_debug(module, level, fmt);
+}
+#else /* __GNUC__ */
+#define xge_debug_config(level, fmt...) \
+	xge_debug(XGE_COMPONENT_HAL_CONFIG, level, fmt)
+#endif /* __GNUC__ */
+#else
+#ifndef __GNUC__
+static inline void xge_debug_config(xge_debug_level_e level, char *fmt,
+...) {}
+#else /* __GNUC__ */
+#define xge_debug_config(level, fmt...)
+#endif /* __GNUC__ */
+#endif
+
+#if (XGE_COMPONENT_HAL_FIFO & XGE_DEBUG_MODULE_MASK)
+#ifndef __GNUC__
+static inline void xge_debug_fifo(xge_debug_level_e level, char *fmt, ...) {
+	u32 module = XGE_COMPONENT_HAL_FIFO;
+	xge_debug(module, level, fmt);
+}
+#else /* __GNUC__ */
+#define xge_debug_fifo(level, fmt...) \
+	xge_debug(XGE_COMPONENT_HAL_FIFO, level, fmt)
+#endif /* __GNUC__ */
+#else
+#ifndef __GNUC__
+static inline void xge_debug_fifo(xge_debug_level_e level, char *fmt, ...) {}
+#else /* __GNUC__ */
+#define xge_debug_fifo(level, fmt...)
+#endif /* __GNUC__ */
+#endif
+
+#if (XGE_COMPONENT_HAL_RING & XGE_DEBUG_MODULE_MASK)
+#ifndef __GNUC__
+static inline void xge_debug_ring(xge_debug_level_e level, char *fmt, ...) {
+	u32 module = XGE_COMPONENT_HAL_RING;
+	xge_debug(module, level, fmt);
+}
+#else /* __GNUC__ */
+#define xge_debug_ring(level, fmt...) \
+	xge_debug(XGE_COMPONENT_HAL_RING, level, fmt)
+#endif /* __GNUC__ */
+#else
+#ifndef __GNUC__
+static inline void xge_debug_ring(xge_debug_level_e level, char *fmt, ...) {}
+#else /* __GNUC__ */
+#define xge_debug_ring(level, fmt...)
+#endif /* __GNUC__ */
+#endif
+
+#if (XGE_COMPONENT_HAL_CHANNEL & XGE_DEBUG_MODULE_MASK)
+#ifndef __GNUC__
+static inline void xge_debug_channel(xge_debug_level_e level, char *fmt, ...) {
+	u32 module = XGE_COMPONENT_HAL_CHANNEL;
+	xge_debug(module, level, fmt);
+}
+#else /* __GNUC__ */
+#define xge_debug_channel(level, fmt...) \
+	xge_debug(XGE_COMPONENT_HAL_CHANNEL, level, fmt)
+#endif /* __GNUC__ */
+#else
+#ifndef __GNUC__
+static inline void xge_debug_channel(xge_debug_level_e level, char *fmt, ...) {}
+#else /* __GNUC__ */
+#define xge_debug_channel(level, fmt...)
+#endif /* __GNUC__ */
+#endif
+
+#if (XGE_COMPONENT_HAL_DEVICE & XGE_DEBUG_MODULE_MASK)
+#ifndef __GNUC__
+static inline void xge_debug_device(xge_debug_level_e level, char *fmt, ...) {
+	u32 module = XGE_COMPONENT_HAL_DEVICE;
+	xge_debug(module, level, fmt);
+}
+#else /* __GNUC__ */
+#define xge_debug_device(level, fmt...) \
+	xge_debug(XGE_COMPONENT_HAL_DEVICE, level, fmt)
+#endif /* __GNUC__ */
+#else
+#ifndef __GNUC__
+static inline void xge_debug_device(xge_debug_level_e level, char *fmt, ...) {}
+#else /* __GNUC__ */
+#define xge_debug_device(level, fmt...)
+#endif /* __GNUC__ */
+#endif
+
+#ifdef XGEHAL_RNIC
+
+#if (XGE_COMPONENT_HAL_DMQ & XGE_DEBUG_MODULE_MASK)
+#ifndef __GNUC__
+static inline void xge_debug_dmq(xge_debug_level_e level, char *fmt, ...) {
+	u32 module = XGE_COMPONENT_HAL_DMQ;
+	xge_debug(module, level, fmt);
+}
+#else /* __GNUC__ */
+#define xge_debug_dmq(level, fmt...) \
+	xge_debug(XGE_COMPONENT_HAL_DMQ, level, fmt)
+#endif /* __GNUC__ */
+#else
+#ifndef __GNUC__
+static inline void xge_debug_dmq(xge_debug_level_e level, char *fmt, ...) {}
+#else /* __GNUC__ */
+#define xge_debug_dmq(level, fmt...)
+#endif /* __GNUC__ */
+#endif
+
+#if (XGE_COMPONENT_HAL_UMQ & XGE_DEBUG_MODULE_MASK)
+#ifndef __GNUC__
+static inline void xge_debug_umq(xge_debug_level_e level, char *fmt, ...) {
+	u32 module = XGE_COMPONENT_HAL_UMQ;
+	xge_debug(module, level, fmt);
+}
+#else /* __GNUC__ */
+#define xge_debug_umq(level, fmt...) \
+	xge_debug(XGE_COMPONENT_HAL_UMQ, level, fmt)
+#endif /* __GNUC__ */
+#else
+#ifndef __GNUC__
+static inline void xge_debug_umq(xge_debug_level_e level, char *fmt, ...) {}
+#else /* __GNUC__ */
+#define xge_debug_umq(level, fmt...)
+#endif /* __GNUC__ */
+#endif
+
+#if (XGE_COMPONENT_HAL_SQ & XGE_DEBUG_MODULE_MASK)
+#ifndef __GNUC__
+static inline void xge_debug_sq(xge_debug_level_e level, char *fmt, ...) {
+	u32 module = XGE_COMPONENT_HAL_SQ;
+	xge_debug(module, level, fmt);
+}
+#else /* __GNUC__ */
+#define xge_debug_sq(level, fmt...) \
+	xge_debug(XGE_COMPONENT_HAL_SQ, level, fmt)
+#endif /* __GNUC__ */
+#else
+#ifndef __GNUC__
+static inline void xge_debug_sq(xge_debug_level_e level, char *fmt, ...) {}
+#else /* __GNUC__ */
+#define xge_debug_sq(level, fmt...)
+#endif /* __GNUC__ */
+#endif
+
+#if (XGE_COMPONENT_HAL_SRQ & XGE_DEBUG_MODULE_MASK)
+#ifndef __GNUC__
+static inline void xge_debug_srq(xge_debug_level_e level, char *fmt, ...) {
+	u32 module = XGE_COMPONENT_HAL_SRQ;
+	xge_debug(module, level, fmt);
+}
+#else /* __GNUC__ */
+#define xge_debug_srq(level, fmt...) \
+	xge_debug(XGE_COMPONENT_HAL_SRQ, level, fmt)
+#endif /* __GNUC__ */
+#else
+#ifndef __GNUC__
+static inline void xge_debug_srq(xge_debug_level_e level, char *fmt, ...) {}
+#else /* __GNUC__ */
+#define xge_debug_srq(level, fmt...)
+#endif /* __GNUC__ */
+#endif
+
+#if (XGE_COMPONENT_HAL_CQRQ & XGE_DEBUG_MODULE_MASK)
+#ifndef __GNUC__
+static inline void xge_debug_cqrq(xge_debug_level_e level, char *fmt, ...) {
+	u32 module = XGE_COMPONENT_HAL_CQRQ;
+	xge_debug(module, level, fmt);
+}
+#else /* __GNUC__ */
+#define xge_debug_cqrq(level, fmt...) \
+	xge_debug(XGE_COMPONENT_HAL_CQRQ, level, fmt)
+#endif /* __GNUC__ */
+#else
+#ifndef __GNUC__
+static inline void xge_debug_cqrq(xge_debug_level_e level, char *fmt, ...) {}
+#else /* __GNUC__ */
+#define xge_debug_cqrq(level, fmt...)
+#endif /* __GNUC__ */
+#endif
+
+#if (XGE_COMPONENT_HAL_POOL & XGE_DEBUG_MODULE_MASK)
+#ifndef __GNUC__
+static inline void xge_debug_pool(xge_debug_level_e level, char *fmt, ...) {
+	u32 module = XGE_COMPONENT_HAL_POOL;
+	xge_debug(module, level, fmt);
+}
+#else /* __GNUC__ */
+#define xge_debug_pool(level, fmt...) \
+	xge_debug(XGE_COMPONENT_HAL_POOL, level, fmt)
+#endif /* __GNUC__ */
+#else
+#ifndef __GNUC__
+static inline void xge_debug_pool(xge_debug_level_e level, char *fmt, ...) {}
+#else /* __GNUC__ */
+#define xge_debug_pool(level, fmt...)
+#endif /* __GNUC__ */
+#endif
+
+#if (XGE_COMPONENT_HAL_BITMAP & XGE_DEBUG_MODULE_MASK)
+#ifndef __GNUC__
+static inline void xge_debug_bitmap(xge_debug_level_e level, char *fmt, ...) {
+	u32 module = XGE_COMPONENT_HAL_BITMAP;
+	xge_debug(module, level, fmt);
+}
+#else /* __GNUC__ */
+#define xge_debug_bitmap(level, fmt...) \
+	xge_debug(XGE_COMPONENT_HAL_BITMAP, level, fmt)
+#endif /* __GNUC__ */
+#else
+#ifndef __GNUC__
+static inline void xge_debug_bitmap(xge_debug_level_e level, char *fmt, ...) {}
+#else /* __GNUC__ */
+#define xge_debug_bitmap(level, fmt...)
+#endif /* __GNUC__ */
+#endif
+
+#endif
+
+#if (XGE_COMPONENT_OSDEP & XGE_DEBUG_MODULE_MASK)
+#ifndef __GNUC__
+static inline void xge_debug_osdep(xge_debug_level_e level, char *fmt, ...) {
+	u32 module = XGE_COMPONENT_OSDEP;
+	xge_debug(module, level, fmt);
+}
+#else /* __GNUC__ */
+#define xge_debug_osdep(level, fmt...) \
+	xge_debug(XGE_COMPONENT_OSDEP, level, fmt)
+#endif /* __GNUC__ */
+#else
+#ifndef __GNUC__
+static inline void xge_debug_osdep(xge_debug_level_e level, char *fmt, ...) {}
+#else /* __GNUC__ */
+#define xge_debug_osdep(level, fmt...)
+#endif /* __GNUC__ */
+#endif
+
+#if (XGE_COMPONENT_LL & XGE_DEBUG_MODULE_MASK)
+#ifndef __GNUC__
+static inline void xge_debug_ll(xge_debug_level_e level, char *fmt, ...)
+{
+	u32 module = XGE_COMPONENT_LL;
+	xge_debug(module, level, fmt);
+}
+#else /* __GNUC__ */
+#define xge_debug_ll(level, fmt...) \
+	xge_debug(XGE_COMPONENT_LL, level, fmt)
+#endif /* __GNUC__ */
+#else
+#ifndef __GNUC__
+static inline void xge_debug_ll(xge_debug_level_e level, char *fmt, ...) {}
+#else /* __GNUC__ */
+#define xge_debug_ll(level, fmt...)
+#endif /* __GNUC__ */
+#endif
+
+#else
+
+static inline void xge_debug_interrupt(xge_debug_level_e level, char *fmt, ...) {}
+static inline void xge_debug_stats(xge_debug_level_e level, char *fmt, ...) {}
+static inline void xge_debug_queue(xge_debug_level_e level, char *fmt, ...) {}
+static inline void xge_debug_mm(xge_debug_level_e level, char *fmt, ...) {}
+static inline void xge_debug_config(xge_debug_level_e level, char *fmt, ...) {}
+static inline void xge_debug_fifo(xge_debug_level_e level, char *fmt, ...) {}
+static inline void xge_debug_ring(xge_debug_level_e level, char *fmt, ...) {}
+static inline void xge_debug_channel(xge_debug_level_e level, char *fmt, ...) {}
+static inline void xge_debug_device(xge_debug_level_e level, char *fmt, ...) {}
+static inline void xge_debug_dmq(xge_debug_level_e level, char *fmt, ...) {}
+static inline void xge_debug_umq(xge_debug_level_e level, char *fmt, ...) {}
+static inline void xge_debug_sq(xge_debug_level_e level, char *fmt, ...) {}
+static inline void xge_debug_srq(xge_debug_level_e level, char *fmt, ...) {}
+static inline void xge_debug_cqrq(xge_debug_level_e level, char *fmt, ...) {}
+static inline void xge_debug_pool(xge_debug_level_e level, char *fmt, ...) {}
+static inline void xge_debug_bitmap(xge_debug_level_e level, char *fmt, ...) {}
+static inline void xge_debug_hal(xge_debug_level_e level, char *fmt, ...) {}
+static inline void xge_debug_osdep(xge_debug_level_e level, char *fmt, ...) {}
+static inline void xge_debug_ll(xge_debug_level_e level, char *fmt, ...) {}
+
+#endif /* end of XGE_DEBUG_*_MASK */
+
+#ifdef XGE_DEBUG_ASSERT
+
+/**
+ * xge_assert
+ * @test: C-condition to check
+ * @fmt: printf like format string
+ *
+ * This function implements traditional assert. By default assertions
+ * are enabled. It can be disabled by defining XGE_DEBUG_ASSERT macro in
+ * compilation
+ * time.
+ */
+#define xge_assert(test) { \
+        if (!(test)) xge_os_bug("bad cond: "#test" at %s:%d\n", \
+	__FILE__, __LINE__); }
+#else
+#define xge_assert(test)
+#endif /* end of XGE_DEBUG_ASSERT */
+
+__EXTERN_END_DECLS
+
+#endif /* XGE_DEBUG_H */
diff --git a/sys/dev/nxge/include/xge-defs.h b/sys/dev/nxge/include/xge-defs.h
new file mode 100644
index 0000000..744a6b9
--- /dev/null
+++ b/sys/dev/nxge/include/xge-defs.h
@@ -0,0 +1,149 @@
+/*-
+ * Copyright (c) 2002-2007 Neterion, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ *  FileName :    xge-defs.h
+ *
+ *  Description:  global definitions
+ *
+ *  Created:      13 May 2004
+ */
+
+#ifndef XGE_DEFS_H
+#define XGE_DEFS_H
+
+#define XGE_PCI_VENDOR_ID			0x17D5
+#define XGE_PCI_DEVICE_ID_XENA_1	0x5731
+#define XGE_PCI_DEVICE_ID_XENA_2	0x5831
+#define XGE_PCI_DEVICE_ID_HERC_1	0x5732
+#define XGE_PCI_DEVICE_ID_HERC_2	0x5832
+#define XGE_PCI_DEVICE_ID_TITAN_1	0x5733
+#define XGE_PCI_DEVICE_ID_TITAN_2	0x5833
+
+#define XGE_DRIVER_NAME				"Xge driver"
+#define XGE_DRIVER_VENDOR			"Neterion, Inc"
+#define XGE_CHIP_FAMILY				"Xframe"
+#define XGE_SUPPORTED_MEDIA_0		"Fiber"
+
+#include <dev/nxge/include/version.h>
+
+#if defined(__cplusplus)
+#define __EXTERN_BEGIN_DECLS	extern "C" {
+#define __EXTERN_END_DECLS	}
+#else
+#define __EXTERN_BEGIN_DECLS
+#define __EXTERN_END_DECLS
+#endif
+
+__EXTERN_BEGIN_DECLS
+
+/*---------------------------- DMA attributes ------------------------------*/
+/*           Used in xge_os_dma_malloc() and xge_os_dma_map() */
+/*---------------------------- DMA attributes ------------------------------*/
+
+/* XGE_OS_DMA_REQUIRES_SYNC  - should be defined or
+                             NOT defined in the Makefile */
+#define XGE_OS_DMA_CACHELINE_ALIGNED      0x1
+/* Either STREAMING or CONSISTENT should be used.
+   The combination of both or none is invalid */
+#define XGE_OS_DMA_STREAMING              0x2
+#define XGE_OS_DMA_CONSISTENT             0x4
+#define XGE_OS_SPRINTF_STRLEN             64
+
+/*---------------------------- common stuffs -------------------------------*/
+
+#define XGE_OS_LLXFMT		"%llx"
+#define XGE_OS_NEWLINE      "\n"
+#ifdef XGE_OS_MEMORY_CHECK
+typedef struct {
+	void *ptr;
+	int size;
+	char *file;
+	int line;
+} xge_os_malloc_t;
+
+#define XGE_OS_MALLOC_CNT_MAX	64*1024
+extern xge_os_malloc_t g_malloc_arr[XGE_OS_MALLOC_CNT_MAX];
+extern int g_malloc_cnt;
+
+#define XGE_OS_MEMORY_CHECK_MALLOC(_vaddr, _size, _file, _line) { \
+	if (_vaddr) { \
+		int i; \
+		for (i=0; i<g_malloc_cnt; i++) { \
+			if (g_malloc_arr[i].ptr == NULL) { \
+				break; \
+			} \
+		} \
+		if (i == g_malloc_cnt) { \
+			g_malloc_cnt++; \
+			if (g_malloc_cnt >= XGE_OS_MALLOC_CNT_MAX) { \
+			  xge_os_bug("g_malloc_cnt exceed %d", \
+						XGE_OS_MALLOC_CNT_MAX); \
+			} \
+		} \
+		g_malloc_arr[i].ptr = _vaddr; \
+		g_malloc_arr[i].size = _size; \
+		g_malloc_arr[i].file = _file; \
+		g_malloc_arr[i].line = _line; \
+		for (i=0; i<_size; i++) { \
+			*((char *)_vaddr+i) = 0x5a; \
+		} \
+	} \
+}
+
+#define XGE_OS_MEMORY_CHECK_FREE(_vaddr, _check_size) { \
+	int i; \
+	for (i=0; i<XGE_OS_MALLOC_CNT_MAX; i++) { \
+		if (g_malloc_arr[i].ptr == _vaddr) { \
+			g_malloc_arr[i].ptr = NULL; \
+			if(_check_size && g_malloc_arr[i].size!=_check_size) { \
+				xge_os_printf("OSPAL: freeing with wrong " \
+				      "size %d! allocated at %s:%d:"XGE_OS_LLXFMT":%d", \
+					 (int)_check_size, \
+					 g_malloc_arr[i].file, \
+					 g_malloc_arr[i].line, \
+					 (unsigned long long)(ulong_t) \
+					    g_malloc_arr[i].ptr, \
+					 g_malloc_arr[i].size); \
+			} \
+			break; \
+		} \
+	} \
+	if (i == XGE_OS_MALLOC_CNT_MAX) { \
+		xge_os_printf("OSPAL: ptr "XGE_OS_LLXFMT" not found!", \
+			    (unsigned long long)(ulong_t)_vaddr); \
+	} \
+}
+#else
+#define XGE_OS_MEMORY_CHECK_MALLOC(ptr, size, file, line)
+#define XGE_OS_MEMORY_CHECK_FREE(vaddr, check_size)
+#endif
+
+__EXTERN_END_DECLS
+
+#endif /* XGE_DEFS_H */
diff --git a/sys/dev/nxge/include/xge-list.h b/sys/dev/nxge/include/xge-list.h
new file mode 100644
index 0000000..c49424d
--- /dev/null
+++ b/sys/dev/nxge/include/xge-list.h
@@ -0,0 +1,203 @@
+/*-
+ * Copyright (c) 2002-2007 Neterion, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ *  FileName :    xge-list.h
+ *
+ *  Description:  Generic bi-directional linked list implementation
+ *
+ *  Created:      14 May 2004
+ */
+
+#ifndef XGE_LIST_H
+#define XGE_LIST_H
+
+#include <dev/nxge/include/xge-debug.h>
+
+__EXTERN_BEGIN_DECLS
+
+/**
+ * struct xge_list_t - List item.
+ * @prev: Previous list item.
+ * @next: Next list item.
+ *
+ * Item of a bi-directional linked list.
+ */
+typedef struct xge_list_t {
+	struct xge_list_t* prev;
+	struct xge_list_t* next;
+} xge_list_t;
+
+/**
+ * xge_list_init - Initialize linked list.
+ * header: first element of the list (head)
+ *
+ * Initialize linked list.
+ * See also: xge_list_t{}.
+ */
+static inline void xge_list_init (xge_list_t *header)
+{
+	header->next = header;
+	header->prev = header;
+}
+
+/**
+ * xge_list_is_empty - Is the list empty?
+ * header: first element of the list (head)
+ *
+ * Determine whether the bi-directional list is empty. Return '1' in
+ * case of 'empty'.
+ * See also: xge_list_t{}.
+ */
+static inline int xge_list_is_empty(xge_list_t *header)
+{
+    xge_assert(header != NULL);
+
+    return header->next == header;
+}
+
+/**
+ * xge_list_first_get - Return the first item from the linked list.
+ * header: first element of the list (head)
+ *
+ * Returns the next item from the header.
+ * Returns NULL if the next item is header itself
+ * See also: xge_list_remove(), xge_list_insert(), xge_list_t{}.
+ */
+static inline xge_list_t *xge_list_first_get(xge_list_t *header)
+{
+	xge_assert(header != NULL);
+	xge_assert(header->next != NULL);
+	xge_assert(header->prev != NULL);
+
+	if(header->next == header)
+		return NULL;
+	else
+		return header->next;
+}
+
+/**
+ * xge_list_remove - Remove the specified item from the linked list.
+ * item: element of the list
+ *
+ * Remove item from a list.
+ * See also: xge_list_insert(), xge_list_t{}.
+ */
+static inline void xge_list_remove(xge_list_t *item)
+{
+	xge_assert(item != NULL);
+	xge_assert(item->next != NULL);
+	xge_assert(item->prev != NULL);
+
+	item->next->prev = item->prev;
+	item->prev->next = item->next;
+#ifdef XGE_DEBUG_ASSERT
+	item->next = item->prev = NULL;
+#endif
+}
+
+/**
+ * xge_list_insert - Insert a new item after the specified item.
+ * new_item: new element of the list
+ * prev_item: element of the list after which the new element is
+ *             inserted
+ *
+ * Insert new item (new_item) after given item (prev_item).
+ * See also: xge_list_remove(), xge_list_insert_before(), xge_list_t{}.
+ */
+static inline void xge_list_insert (xge_list_t *new_item,
+				    xge_list_t *prev_item)
+{
+	xge_assert(new_item  != NULL);
+	xge_assert(prev_item != NULL);
+	xge_assert(prev_item->next != NULL);
+
+	new_item->next = prev_item->next;
+	new_item->prev = prev_item;
+	prev_item->next->prev = new_item;
+	prev_item->next = new_item;
+}
+
+/**
+ * xge_list_insert_before - Insert a new item before the specified item.
+ * new_item: new element of the list
+ * next_item: element of the list after which the new element is inserted
+ *
+ * Insert new item (new_item) before given item (next_item).
+ */
+static inline void xge_list_insert_before (xge_list_t *new_item,
+				    	   xge_list_t *next_item)
+{
+	xge_assert(new_item  != NULL);
+	xge_assert(next_item != NULL);
+	xge_assert(next_item->next != NULL);
+
+	new_item->next = next_item;
+	new_item->prev = next_item->prev;
+	next_item->prev->next = new_item;
+	next_item->prev = new_item;
+}
+
+#define xge_list_for_each(_p, _h) \
+	for (_p = (_h)->next, xge_os_prefetch(_p->next); _p != (_h); \
+		_p = _p->next, xge_os_prefetch(_p->next))
+
+#define xge_list_for_each_safe(_p, _n, _h) \
+        for (_p = (_h)->next, _n = _p->next; _p != (_h); \
+                _p = _n, _n = _p->next)
+
+#ifdef __GNUC__
+/**
+ * xge_container_of - Given a member, return the containing structure.
+ * @ptr:	the pointer to the member.
+ * @type:	the type of the container struct this is embedded in.
+ * @member:	the name of the member within the struct.
+ *
+ * Cast a member of a structure out to the containing structure.
+ */
+#define xge_container_of(ptr, type, member) ({			\
+         __typeof( ((type *)0)->member ) *__mptr = (ptr);	\
+        (type *)(void *)( (char *)__mptr - ((size_t) &((type *)0)->member) );})
+#else
+/* type unsafe version */
+#define xge_container_of(ptr, type, member) \
+                ((type*)(void*)((char*)(ptr) - ((size_t) &((type *)0)->member)))
+#endif
+
+/**
+ * xge_offsetof - Offset of the member in the containing structure.
+ * @t:	struct name.
+ * @m:	the name of the member within the struct.
+ *
+ * Return the offset of the member @m in the structure @t.
+ */
+#define xge_offsetof(t, m) ((size_t) (&((t *)0)->m))
+
+__EXTERN_END_DECLS
+
+#endif /* XGE_LIST_H */
diff --git a/sys/dev/nxge/include/xge-os-pal.h b/sys/dev/nxge/include/xge-os-pal.h
new file mode 100644
index 0000000..5c92fe6
--- /dev/null
+++ b/sys/dev/nxge/include/xge-os-pal.h
@@ -0,0 +1,138 @@
+/*-
+ * Copyright (c) 2002-2007 Neterion, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ *  FileName :    xge-os-pal.h
+ *
+ *  Description:  top-level header file. works just like switching between
+ *                os-depndent parts
+ *
+ *  Created:      6st May 2004
+ */
+
+#ifndef XGE_OS_PAL_H
+#define XGE_OS_PAL_H
+
+#include <dev/nxge/include/xge-defs.h>
+
+__EXTERN_BEGIN_DECLS
+
+/*--------------------------- platform switch ------------------------------*/
+
+/* platform specific header */
+#include <dev/nxge/xge-osdep.h>
+#ifdef XGEHAL_RNIC
+#define IN
+#define OUT
+#endif
+
+#if !defined(XGE_OS_PLATFORM_64BIT) && !defined(XGE_OS_PLATFORM_32BIT)
+#error "either 32bit or 64bit switch must be defined!"
+#endif
+
+#if !defined(XGE_OS_HOST_BIG_ENDIAN) && !defined(XGE_OS_HOST_LITTLE_ENDIAN)
+#error "either little endian or big endian switch must be defined!"
+#endif
+
+#if defined(XGE_OS_PLATFORM_64BIT)
+#define XGE_OS_MEMORY_DEADCODE_PAT	0x5a5a5a5a5a5a5a5a
+#else
+#define XGE_OS_MEMORY_DEADCODE_PAT	0x5a5a5a5a
+#endif
+
+#define XGE_OS_TRACE_MSGBUF_MAX		512
+typedef struct xge_os_tracebuf_t {
+	int		wrapped_once;     /* circular buffer been wrapped */
+	int		timestamp;        /* whether timestamps are enabled */
+	volatile int	offset;           /* offset within the tracebuf */
+	int		size;             /* total size of trace buffer */
+	char		msg[XGE_OS_TRACE_MSGBUF_MAX]; /* each individual buffer */
+	int		msgbuf_max;	  /* actual size of msg buffer */
+	char		*data;            /* pointer to data buffer */
+} xge_os_tracebuf_t;
+extern xge_os_tracebuf_t *g_xge_os_tracebuf;
+
+#ifdef XGE_TRACE_INTO_CIRCULAR_ARR
+extern xge_os_tracebuf_t *g_xge_os_tracebuf;
+extern char *dmesg_start;
+
+/* Calculate the size of the msg and copy it into the global buffer */  
+#define __xge_trace(tb) { \
+	int msgsize = xge_os_strlen(tb->msg) + 2; \
+	int offset = tb->offset; \
+	if (msgsize != 2 && msgsize < tb->msgbuf_max) { \
+		int leftsize =  tb->size - offset; \
+		if ((msgsize + tb->msgbuf_max) > leftsize) { \
+			xge_os_memzero(tb->data + offset, leftsize); \
+			offset = 0; \
+			tb->wrapped_once = 1; \
+		} \
+		xge_os_memcpy(tb->data + offset, tb->msg, msgsize-1); \
+		*(tb->data + offset + msgsize-1) = '\n'; \
+		*(tb->data + offset + msgsize) = 0; \
+		offset += msgsize; \
+		tb->offset = offset; \
+		dmesg_start = tb->data + offset; \
+		*tb->msg = 0; \
+	} \
+}
+
+#define xge_os_vatrace(tb, fmt) { \
+	if (tb != NULL) { \
+		char *_p = tb->msg; \
+		if (tb->timestamp) { \
+			xge_os_timestamp(tb->msg); \
+			_p = tb->msg + xge_os_strlen(tb->msg); \
+		} \
+		xge_os_vasprintf(_p, fmt); \
+		__xge_trace(tb); \
+	} \
+}
+
+#ifdef __GNUC__
+#define xge_os_trace(tb, fmt...) { \
+	if (tb != NULL) { \
+		if (tb->timestamp) { \
+			xge_os_timestamp(tb->msg); \
+		} \
+		xge_os_sprintf(tb->msg + xge_os_strlen(tb->msg), fmt); \
+		__xge_trace(tb); \
+	} \
+}
+#endif /* __GNUC__ */
+
+#else
+#define xge_os_vatrace(tb, fmt)
+#ifdef __GNUC__
+#define xge_os_trace(tb, fmt...)
+#endif /* __GNUC__ */
+#endif
+
+__EXTERN_END_DECLS
+
+#endif /* XGE_OS_PAL_H */
diff --git a/sys/dev/nxge/include/xge-os-template.h b/sys/dev/nxge/include/xge-os-template.h
new file mode 100644
index 0000000..4d50e6e
--- /dev/null
+++ b/sys/dev/nxge/include/xge-os-template.h
@@ -0,0 +1,614 @@
+/*-
+ * Copyright (c) 2002-2007 Neterion, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ *  FileName :    xge-os-template.h
+ *
+ *  Description:  Template for creating platform-dependent "glue" code.
+ *
+ *  Created:      6 May 2004
+ */
+
+#ifndef XGE_OS_TEMPLATE_H
+#define XGE_OS_TEMPLATE_H
+
+#ifndef TEMPLATE
+#	error "should not be compiled for platforms other than TEMPLATE..."
+#endif
+
+/* ------------------------- includes and defines ------------------------- */
+
+/*
+ * Note:
+ *
+ *     - on some operating systems like Linux & FreeBSD, there is a macro
+ *       by using which it is possible to determine endiennes automatically
+ */
+#define XGE_OS_HOST_BIG_ENDIAN	TEMPLATE
+
+#define XGE_OS_HOST_PAGE_SIZE	TEMPLATE
+
+/* ---------------------- fixed size primitive types -----------------------*/
+
+/*
+ * Note:
+ *
+ *	- u## - means ## bits unsigned int/long
+ *      - all names must be preserved since HAL using them.
+ *      - ulong_t is platform specific, i.e. for 64bit - 64bit size, for
+ *        32bit - 32bit size
+ */
+#define TEMPLATE		u8
+#define TEMPLATE		u16
+#define TEMPLATE		u32
+#define TEMPLATE		u64
+#define TEMPLATE		ulong_t
+#define TEMPLATE		ptrdiff_t
+#define TEMPLATE		dma_addr_t
+#define TEMPLATE		spinlock_t
+typedef TEMPLATE		pci_dev_h;
+typedef TEMPLATE		pci_reg_h;
+typedef TEMPLATE		pci_dma_h;
+typedef TEMPLATE		pci_irq_h;
+typedef TEMPLATE		pci_cfg_h;
+typedef TEMPLATE		pci_dma_acc_h;
+
+/* -------------------------- "libc" functionality -------------------------*/
+
+/*
+ * Note:
+ *
+ *	- "libc" functionality maps one-to-one to be posix-like
+ */
+/* Note: use typedef: xge_os_memzero(void* mem, int size); */
+#define xge_os_memzero			TEMPLATE
+
+/* Note: the 1st argument MUST be destination, like in:
+ * void *memcpy(void *dest, const void *src, size_t n);
+ */
+#define xge_os_memcpy			TEMPLATE
+
+/* Note: should accept format (the 1st argument) and a variable
+ * number of arguments thereafter.. */
+#define xge_os_printf(fmt...)		TEMPLATE
+
+#define xge_os_vasprintf(buf, fmt...)	TEMPLATE
+
+#define xge_os_sprintf(buf, fmt, ...)	TEMPLATE
+
+#define xge_os_timestamp(buf)		TEMPLATE
+
+#define xge_os_println			TEMPLATE
+
+/* -------------------- synchronization primitives -------------------------*/
+
+/*
+ * Note:
+ *
+ *	- use spin_lock in interrupts or in threads when there is no races
+ *	  with interrupt
+ *	- use spin_lock_irqsave in threads if there is a race with interrupt
+ *	- use spin_lock_irqsave for nested locks
+ */
+
+/*
+ * Initialize the spin lock.
+ */
+#define xge_os_spin_lock_init(lockp, ctxh)	TEMPLATE
+/*
+ * Initialize the spin lock (IRQ version).
+ */
+#define xge_os_spin_lock_init_irq(lockp, ctxh)	TEMPLATE
+/*
+ * Destroy the lock.
+ */
+#define xge_os_spin_lock_destroy(lockp, ctxh)	TEMPLATE
+
+/*
+ * Destroy the lock (IRQ version).
+ */
+#define xge_os_spin_lock_destroy_irq(lockp, ctxh)	TEMPLATE
+/*
+ * Acquire the lock.
+ */
+#define xge_os_spin_lock(lockp)			TEMPLATE
+/*
+ * Release the lock.
+ */
+#define xge_os_spin_unlock(lockp)		TEMPLATE
+/*
+ * Acquire the lock(IRQ version).
+ */
+#define xge_os_spin_lock_irq(lockp, flags)	TEMPLATE
+/*
+ * Release the lock(IRQ version).
+ */
+#define xge_os_spin_unlock_irq(lockp, flags)	TEMPLATE
+/*
+ * Write memory barrier.
+ */
+#define xge_os_wmb()				TEMPLATE
+/*
+ * Delay (in micro seconds).
+ */
+#define xge_os_udelay(us)			TEMPLATE
+/*
+ * Delay (in milli seconds).
+ */
+#define xge_os_mdelay(ms)			TEMPLATE
+/*
+ * Compare and exchange.
+ */
+#define xge_os_cmpxchg(targetp, cmp, newval)	TEMPLATE
+
+
+
+/* ------------------------- misc primitives -------------------------------*/
+
+#define xge_os_prefetch			TEMPLATE
+#define xge_os_prefetchw		TEMPLATE
+#define xge_os_bug(fmt...)		TEMPLATE
+
+/* -------------------------- compiler stuffs ------------------------------*/
+
+#define __xge_os_attr_cacheline_aligned	TEMPLATE
+
+/* ---------------------- memory primitives --------------------------------*/
+
+/**
+ * xge_os_malloc - Allocate non DMA-able memory.
+ * @pdev: Device context. Some OSs require device context to perform
+ *        operations on memory.
+ * @size: Size to allocate.
+ *
+ * Allocate @size bytes of memory. This allocation can sleep, and
+ * therefore, and therefore it requires process context. In other words,
+ * xge_os_malloc() cannot be called from the interrupt context.
+ * Use xge_os_free() to free the allocated block.
+ *
+ * Returns: Pointer to allocated memory, NULL - on failure.
+ *
+ * See also: xge_os_free().
+ */
+static inline void *xge_os_malloc(IN  pci_dev_h pdev,
+                                IN  unsigned long size)
+{ TEMPLATE; }
+
+/**
+ * xge_os_free - Free non DMA-able memory.
+ * @pdev: Device context. Some OSs require device context to perform
+ *        operations on memory.
+ * @vaddr: Address of the allocated memory block.
+ * @size: Some OS's require to provide size on free
+ *
+ * Free the memory area obtained via xge_os_malloc().
+ * This call may also sleep, and therefore it cannot be used inside
+ * interrupt.
+ *
+ * See also: xge_os_malloc().
+ */
+static inline void xge_os_free(IN  pci_dev_h pdev,
+                             IN  const void *vaddr,
+			     IN unsigned long size)
+{ TEMPLATE; }
+
+/**
+ * xge_os_vaddr - Get Virtual address for the given physical address.
+ * @pdev: Device context. Some OSs require device context to perform
+ *        operations on memory.
+ * @vaddr: Physical Address of the memory block.
+ * @size: Some OS's require to provide size
+ *
+ * Get the virtual address for physical address.
+ * This call may also sleep, and therefore it cannot be used inside
+ * interrupt.
+ *
+ * See also: xge_os_malloc().
+ */
+static inline void xge_os_vaddr(IN  pci_dev_h pdev,
+                             IN  const void *vaddr,
+			     IN unsigned long size)
+{ TEMPLATE; }
+
+/**
+ * xge_os_dma_malloc  -  Allocate DMA-able memory.
+ * @pdev: Device context. Used to allocate/pin/map/unmap DMA-able memory.
+ * @size: Size (in bytes) to allocate.
+ * @dma_flags: XGE_OS_DMA_CACHELINE_ALIGNED,
+ *             XGE_OS_DMA_STREAMING,
+ *             XGE_OS_DMA_CONSISTENT
+ *	 Note that the last two flags are mutually exclusive.
+ * @p_dmah: Handle used to map the memory onto the corresponding device memory
+ *          space. See xge_os_dma_map(). The handle is an out-parameter
+ *          returned by the function.
+ * @p_dma_acch: One more DMA handle used subsequently to free the
+ *              DMA object (via xge_os_dma_free()).
+ *              Note that this and the previous handle have
+ *              physical meaning for Solaris; on Windows and Linux the
+ *              corresponding value will be simply a pointer to PCI device.
+ *              The value is returned by this function.
+ *
+ * Allocate DMA-able contiguous memory block of the specified @size.
+ * This memory can be subsequently freed using xge_os_dma_free().
+ * Note: can be used inside interrupt context.
+ *
+ * Returns: Pointer to allocated memory(DMA-able), NULL on failure.
+ *
+ */
+static inline void *xge_os_dma_malloc(IN  pci_dev_h pdev,
+				    IN  unsigned long size,
+				    IN  int dma_flags,
+				    OUT pci_dma_h *p_dmah,
+				    OUT pci_dma_acc_h *p_dma_acch)
+{ TEMPLATE; }
+
+/**
+ * xge_os_dma_free - Free previously allocated DMA-able memory.
+ * @pdev: Device context. Used to allocate/pin/map/unmap DMA-able memory.
+ * @vaddr: Virtual address of the DMA-able memory.
+ * @p_dma_acch: DMA handle used to free the resource.
+ * @p_dmah: DMA handle used for mapping. See xge_os_dma_malloc().
+ *
+ * Free DMA-able memory originally allocated by xge_os_dma_malloc().
+ * Note: can be used inside interrupt.
+ * See also: xge_os_dma_malloc().
+ */
+static inline void xge_os_dma_free (IN  pci_dev_h pdev,
+                                  IN  const void *vaddr,
+				  IN  pci_dma_acc_h *p_dma_acch,
+				  IN  pci_dma_h *p_dmah)
+{ TEMPLATE; }
+
+/* ----------------------- io/pci/dma primitives ---------------------------*/
+
+#define XGE_OS_DMA_DIR_TODEVICE		TEMPLATE
+#define XGE_OS_DMA_DIR_FROMDEVICE	TEMPLATE
+#define XGE_OS_DMA_DIR_BIDIRECTIONAL	TEMPLATE
+
+/**
+ * xge_os_pci_read8 - Read one byte from device PCI configuration.
+ * @pdev: Device context. Some OSs require device context to perform
+ *        PIO and/or config space IO.
+ * @cfgh: PCI configuration space handle.
+ * @where: Offset in the PCI configuration space.
+ * @val: Address of the result.
+ *
+ * Read byte value from the specified @regh PCI configuration space at the
+ * specified offset = @where.
+ * Returns: 0 - success, non-zero - failure.
+ */
+static inline int xge_os_pci_read8(IN  pci_dev_h pdev,
+				 IN  pci_cfg_h cfgh,
+				 IN  int where,
+				 IN  u8 *val)
+{ TEMPLATE; }
+
+/**
+ * xge_os_pci_write8 - Write one byte into device PCI configuration.
+ * @pdev: Device context. Some OSs require device context to perform
+ *        PIO and/or config space IO.
+ * @cfgh: PCI configuration space handle.
+ * @where: Offset in the PCI configuration space.
+ * @val: Value to write.
+ *
+ * Write byte value into the specified PCI configuration space
+ * Returns: 0 - success, non-zero - failure.
+ */
+static inline int xge_os_pci_write8(IN  pci_dev_h pdev,
+				  IN  pci_cfg_h cfgh,
+				  IN  int where,
+				  IN  u8 val)
+{ TEMPLATE; }
+
+/**
+ * xge_os_pci_read16 - Read 16bit word from device PCI configuration.
+ * @pdev: Device context. Some OSs require device context to perform
+ *        PIO and/or config space IO.
+ * @cfgh: PCI configuration space handle.
+ * @where: Offset in the PCI configuration space.
+ * @val: Address of the 16bit result.
+ *
+ * Read 16bit value from the specified PCI configuration space at the
+ * specified offset.
+ * Returns: 0 - success, non-zero - failure.
+ */
+static inline int xge_os_pci_read16(IN  pci_dev_h pdev,
+				  IN  pci_cfg_h cfgh,
+				  IN  int where,
+				  IN  u16 *val)
+{ TEMPLATE; }
+
+/**
+ * xge_os_pci_write16 - Write 16bit word into device PCI configuration.
+ * @pdev: Device context. Some OSs require device context to perform
+ *        PIO and/or config space IO.
+ * @cfgh: PCI configuration space handle.
+ * @where: Offset in the PCI configuration space.
+ * @val: Value to write.
+ *
+ * Write 16bit value into the specified @offset in PCI
+ * configuration space.
+ * Returns: 0 - success, non-zero - failure.
+ */
+static inline int xge_os_pci_write16(IN  pci_dev_h pdev,
+				   IN  pci_cfg_h cfgh,
+				   IN  int where,
+				   IN  u16 val)
+{ TEMPLATE; }
+
+/**
+ * xge_os_pci_read32 - Read 32bit word from device PCI configuration.
+ * @pdev: Device context. Some OSs require device context to perform
+ *        PIO and/or config space IO.
+ * @cfgh: PCI configuration space handle.
+ * @where: Offset in the PCI configuration space.
+ * @val: Address of 32bit result.
+ *
+ * Read 32bit value from the specified PCI configuration space at the
+ * specified offset.
+ * Returns: 0 - success, non-zero - failure.
+ */
+static inline int xge_os_pci_read32(IN  pci_dev_h pdev,
+				  IN  pci_cfg_h cfgh,
+				  IN  int where,
+				  IN  u32 *val)
+{ TEMPLATE; }
+
+/**
+ * xge_os_pci_write32 - Write 32bit word into device PCI configuration.
+ * @pdev: Device context. Some OSs require device context to perform
+ *        PIO and/or config space IO.
+ * @cfgh: PCI configuration space handle.
+ * @where: Offset in the PCI configuration space.
+ * @val: Value to write.
+ *
+ * Write 32bit value into the specified @offset in PCI
+ * configuration space.
+ * Returns: 0 - success, non-zero - failure.
+ */
+static inline int xge_os_pci_write32(IN  pci_dev_h pdev,
+				   IN  pci_cfg_h cfgh,
+				   IN  int where,
+				   IN  u32 val)
+{ TEMPLATE; }
+
+/**
+ * xge_os_pio_mem_read8 - Read 1 byte from device memory mapped space.
+ * @pdev: Device context. Some OSs require device context to perform
+ *        PIO and/or config space IO..
+ * @regh: PCI configuration space handle.
+ * @addr: Address in device memory space.
+ *
+ * Returns: 1 byte value read from the specified (mapped) memory space address.
+ */
+static inline u8 xge_os_pio_mem_read8(IN  pci_dev_h pdev,
+                                    IN  pci_reg_h regh,
+				    IN void *addr)
+{ TEMPLATE; }
+
+/**
+ * xge_os_pio_mem_write64 - Write 1 byte into device memory mapped
+ * space.
+ * @pdev: Device context. Some OSs require device context to perform
+ *        PIO and/or config space IO..
+ * @regh: PCI configuration space handle.
+ * @val: Value to write.
+ * @addr: Address in device memory space.
+ *
+ * Write byte value into the specified (mapped) device memory space.
+ */
+static inline void xge_os_pio_mem_write8(IN  pci_dev_h pdev,
+                                       IN  pci_reg_h regh,
+				       IN  u8 val,
+				       IN  void *addr)
+{ TEMPLATE; }
+
+/**
+ * xge_os_pio_mem_read16 - Read 16bit from device memory mapped space.
+ * @pdev: Device context. Some OSs require device context to perform
+ *        PIO.
+ * @regh: PCI configuration space handle.
+ * @addr: Address in device memory space.
+ *
+ * Returns: 16bit value read from the specified (mapped) memory space address.
+ */
+static inline u16 xge_os_pio_mem_read16(IN  pci_dev_h pdev,
+                                      IN  pci_reg_h regh,
+				      IN  void *addr)
+{
+TEMPLATE; }
+
+/**
+ * xge_os_pio_mem_write16 - Write 16bit into device memory mapped space.
+ * @pdev: Device context. Some OSs require device context to perform
+ *        PIO.
+ * @regh: PCI configuration space handle.
+ * @val: Value to write.
+ * @addr: Address in device memory space.
+ *
+ * Write 16bit value into the specified (mapped) device memory space.
+ */
+static inline void xge_os_pio_mem_write16(IN  pci_dev_h pdev,
+                                        IN  pci_reg_h regh,
+					IN  u16 val,
+					IN  void *addr)
+{ TEMPLATE; }
+
+/**
+ * xge_os_pio_mem_read32 - Read 32bit from device memory mapped space.
+ * @pdev: Device context. Some OSs require device context to perform
+ *        PIO.
+ * @regh: PCI configuration space handle.
+ * @addr: Address in device memory space.
+ *
+ * Returns: 32bit value read from the specified (mapped) memory space address.
+ */
+static inline u32 xge_os_pio_mem_read32(IN  pci_dev_h pdev,
+                                      IN  pci_reg_h regh,
+				      IN  void *addr)
+{ TEMPLATE; }
+
+/**
+ * xge_os_pio_mem_write32 - Write 32bit into device memory space.
+ * @pdev: Device context. Some OSs require device context to perform
+ *        PIO.
+ * @regh: PCI configuration space handle.
+ * @val: Value to write.
+ * @addr: Address in device memory space.
+ *
+ * Write 32bit value into the specified (mapped) device memory space.
+ */
+static inline void xge_os_pio_mem_write32(IN  pci_dev_h pdev,
+                                        IN  pci_reg_h regh,
+					IN  u32 val,
+					IN  void *addr)
+{ TEMPLATE; }
+
+/**
+ * xge_os_pio_mem_read64 - Read 64bit from device memory mapped space.
+ * @pdev: Device context. Some OSs require device context to perform
+ *        PIO.
+ * @regh: PCI configuration space handle.
+ * @addr: Address in device memory space.
+ *
+ * Returns: 64bit value read from the specified (mapped) memory space address.
+ */
+static inline u64 xge_os_pio_mem_read64(IN  pci_dev_h pdev,
+                                      IN  pci_reg_h regh,
+				      IN  void *addr)
+{ TEMPLATE; }
+
+/**
+ * xge_os_pio_mem_write64 - Write 64bit into device memory space.
+ * @pdev: Device context. Some OSs require device context to perform
+ *        PIO.
+ * @regh: PCI configuration space handle.
+ * @val: Value to write.
+ * @addr: Address in device memory space.
+ *
+ * Write 64bit value into the specified (mapped) device memory space.
+ */
+static inline void xge_os_pio_mem_write64(IN  pci_dev_h pdev,
+                                        IN  pci_reg_h regh,
+					IN  u64 val,
+					IN  void *addr)
+{ TEMPLATE; }
+
+/**
+ * xge_os_flush_bridge - Flush the bridge.
+ * @pdev: Device context. Some OSs require device context to perform
+ *        PIO.
+ * @regh: PCI configuration space handle.
+ * @addr: Address in device memory space.
+ *
+ * Flush the bridge.
+ */
+static inline void xge_os_flush_bridge(IN  pci_dev_h pdev,
+				       IN  pci_reg_h regh,
+				       IN  void *addr)
+{ TEMPLATE; }
+
+/**
+ * xge_os_dma_map - Map DMA-able memory block to, or from, or
+ * to-and-from device.
+ * @pdev: Device context. Used to allocate/pin/map/unmap DMA-able memory.
+ * @dmah: DMA handle used to map the memory block. Obtained via
+ * xge_os_dma_malloc().
+ * @vaddr: Virtual address of the DMA-able memory.
+ * @size: Size (in bytes) to be mapped.
+ * @dir: Direction of this operation (XGE_OS_DMA_DIR_TODEVICE, etc.)
+ * @dma_flags: XGE_OS_DMA_CACHELINE_ALIGNED,
+ *             XGE_OS_DMA_STREAMING,
+ *             XGE_OS_DMA_CONSISTENT
+ *	 Note that the last two flags are mutually exclusive.
+ *
+ * Map a single memory block.
+ *
+ * Returns: DMA address of the memory block,
+ * XGE_OS_INVALID_DMA_ADDR on failure.
+ *
+ * See also: xge_os_dma_malloc(), xge_os_dma_unmap(),
+ * xge_os_dma_sync().
+ */
+static inline dma_addr_t xge_os_dma_map(IN  pci_dev_h pdev,
+				      IN  pci_dma_h dmah,
+				      IN  void *vaddr,
+				      IN  size_t size,
+				      IN  int dir,
+				      IN  int dma_flags)
+{ TEMPLATE; }
+
+/**
+ * xge_os_dma_unmap - Unmap DMA-able memory.
+ * @pdev: Device context. Used to allocate/pin/map/unmap DMA-able memory.
+ * @dmah: DMA handle used to map the memory block. Obtained via
+ * xge_os_dma_malloc().
+ * @dma_addr: DMA address of the block. Obtained via xge_os_dma_map().
+ * @size: Size (in bytes) to be unmapped.
+ * @dir: Direction of this operation (XGE_OS_DMA_DIR_TODEVICE, etc.)
+ *
+ * Unmap a single DMA-able memory block that was previously mapped
+ * using xge_os_dma_map().
+ * See also: xge_os_dma_malloc(), xge_os_dma_map().
+ */
+static inline void xge_os_dma_unmap(IN  pci_dev_h pdev,
+				  IN  pci_dma_h dmah,
+				  IN  dma_addr_t dma_addr,
+				  IN  size_t size,
+				  IN  int dir)
+{ TEMPLATE; }
+
+/**
+ * xge_os_dma_sync - Synchronize mapped memory.
+ * @pdev: Device context. Used to allocate/pin/map/unmap DMA-able memory.
+ * @dmah: DMA handle used to map the memory block. Obtained via
+ * xge_os_dma_malloc().
+ * @dma_addr: DMA address of the block. Obtained via xge_os_dma_map().
+ * @dma_offset: Offset from start of the blocke. Used by Solaris only.
+ * @length: Size of the block.
+ * @dir: Direction of this operation (XGE_OS_DMA_DIR_TODEVICE, etc.)
+ *
+ * Make physical and CPU memory consistent for a single
+ * streaming mode DMA translation.
+ * This API compiles to NOP on cache-coherent platforms.
+ * On non cache-coherent platforms, depending on the direction
+ * of the "sync" operation, this API will effectively
+ * either invalidate CPU cache (that might contain old data),
+ * or  flush CPU cache to update physical memory.
+ * See also: xge_os_dma_malloc(), xge_os_dma_map(),
+ * xge_os_dma_unmap().
+ */
+static inline void xge_os_dma_sync(IN  pci_dev_h pdev,
+				 IN  pci_dma_h dmah,
+				 IN  dma_addr_t dma_addr,
+				 IN  u64 dma_offset,
+				 IN  size_t length,
+				 IN  int dir)
+{ TEMPLATE; }
+
+#endif /* XGE_OS_TEMPLATE_H */
diff --git a/sys/dev/nxge/include/xge-queue.h b/sys/dev/nxge/include/xge-queue.h
new file mode 100644
index 0000000..6745888
--- /dev/null
+++ b/sys/dev/nxge/include/xge-queue.h
@@ -0,0 +1,185 @@
+/*-
+ * Copyright (c) 2002-2007 Neterion, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ *  FileName :    xge-queue.h
+ *
+ *  Description:  serialized event queue
+ *
+ *  Created:      7 June 2004
+ */
+
+#ifndef XGE_QUEUE_H
+#define XGE_QUEUE_H
+
+#include <dev/nxge/include/xge-os-pal.h>
+#include <dev/nxge/include/xge-defs.h>
+#include <dev/nxge/include/xge-list.h>
+#include <dev/nxge/include/xgehal-event.h>
+
+__EXTERN_BEGIN_DECLS
+
+#define XGE_QUEUE_BUF_SIZE		0x1000
+#define XGE_DEFAULT_EVENT_MAX_DATA_SIZE	16
+
+/**
+ * enum xge_queue_status_e - Enumerates return codes of the xge_queue
+ * manipulation APIs.
+ * @XGE_QUEUE_IS_FULL: Queue is full, need to grow.
+ * @XGE_QUEUE_IS_EMPTY: Queue is empty.
+ * @XGE_QUEUE_OUT_OF_MEMORY: Out of memory.
+ * @XGE_QUEUE_NOT_ENOUGH_SPACE: Exceeded specified event size,
+ * see xge_queue_consume().
+ * @XGE_QUEUE_OK: Neither one of the codes listed above.
+ *
+ * Enumerates return codes of xge_queue_consume()
+ * and xge_queue_produce() APIs.
+ */
+typedef enum xge_queue_status_e {
+	XGE_QUEUE_OK			= 0,
+	XGE_QUEUE_IS_FULL		= 1,
+	XGE_QUEUE_IS_EMPTY		= 2,
+	XGE_QUEUE_OUT_OF_MEMORY	        = 3,
+	XGE_QUEUE_NOT_ENOUGH_SPACE	= 4
+} xge_queue_status_e;
+
+typedef void* xge_queue_h;
+
+/**
+ * struct xge_queue_item_t - Queue item.
+ * @item: List item. Note that the queue is "built" on top of
+ *        the bi-directional linked list.
+ * @event_type: Event type. Includes (but is not restricted to)
+ * one of the xge_hal_event_e{} enumerated types.
+ * @data_size: Size of the enqueued user data. Note that xge_queue_t
+ * items are allowed to have variable sizes.
+ * @is_critical: For critical events, e.g. ECC.
+ * @context: Opaque (void*) "context", for instance event producer object.
+ *
+ * Item of the xge_queue_t{}. The queue is protected
+ * in terms of multi-threaded concurrent access.
+ * See also: xge_queue_t{}.
+ */
+typedef struct xge_queue_item_t {
+	xge_list_t			item;
+	xge_hal_event_e		event_type;
+	int					data_size;
+	int					is_critical;
+	void				*context;
+} xge_queue_item_t;
+
+/**
+ * function xge_queued_f - Item-enqueued callback.
+ * @data: Per-queue context independent of the event. E.g., device handle.
+ * @event_type: HAL or ULD-defined event type. Note that HAL own
+ *        events are enumerated by xge_hal_event_e{}.
+ *
+ * Per-queue optional callback. If not NULL, called by HAL each
+ * time an event gets added to the queue.
+ */
+typedef void (*xge_queued_f) (void *data, int event_type);
+
+/**
+ * struct xge_queue_t - Protected dynamic queue of variable-size items.
+ * @start_ptr: Points to the start of the queue.
+ * @end_ptr: Points to the end of the queue.
+ * @head_ptr: Points to the head of the queue. It gets changed during queue
+ *            produce/consume operations.
+ * @tail_ptr: Points to the tail of the queue. It gets changed during queue
+ *            produce/consume operations.
+ * @lock: Lock for queue operations(syncronization purpose).
+ * @pages_initial:Number of pages to be initially allocated at the time
+ *		  of queue creation.
+ * @pages_max: Max number of pages that can be allocated in the queue.
+ * @pages_current: Number of pages currently allocated
+ * @list_head: Points to the list of queue elements that are produced, but yet
+ *             to be consumed.
+ * @signal_callback: (TODO)
+ * @pdev: PCI device handle
+ * @irqh: PCI device IRQ handle.
+ * @queued_func: Optional callback function to be called each time a new
+ * item is added to the queue.
+ * @queued_data: Arguments to the callback function.
+ * @has_critical_event: Non-zero, if the queue contains a critical event,
+ * see xge_hal_event_e{}.
+ * Protected dynamically growing queue. The queue is used to support multiple
+ * producer/consumer type scenarios. The queue is a strict FIFO: first come
+ * first served.
+ * Queue users may "produce" (see xge_queue_produce()) and "consume"
+ * (see xge_queue_consume()) items (a.k.a. events) variable sizes.
+ * See also: xge_queue_item_t{}.
+ */
+typedef struct xge_queue_t {
+	void				*start_ptr;
+	void				*end_ptr;
+	void				*head_ptr;
+	void				*tail_ptr;
+	spinlock_t			lock;
+	unsigned int			pages_initial;
+	unsigned int			pages_max;
+	unsigned int			pages_current;
+	xge_list_t			list_head;
+	pci_dev_h                       pdev;
+	pci_irq_h                       irqh;
+	xge_queued_f			queued_func;
+	void				*queued_data;
+	int				has_critical_event;
+} xge_queue_t;
+
+/* ========================== PUBLIC API ================================= */
+
+xge_queue_h xge_queue_create(pci_dev_h pdev, pci_irq_h irqh, int pages_initial,
+		int pages_max, xge_queued_f queued_func, void *queued_data);
+
+void xge_queue_destroy(xge_queue_h queueh);
+
+void* xge_queue_item_data(xge_queue_item_t *item);
+
+xge_queue_status_e
+xge_queue_produce(xge_queue_h queueh, int event_type, void *context,
+		int is_critical, const int data_size, void *data);
+
+static inline xge_queue_status_e
+xge_queue_produce_context(xge_queue_h queueh, int event_type, void *context) {
+	return xge_queue_produce(queueh, event_type, context, 0, 0, 0);
+}
+
+xge_queue_status_e xge_queue_consume(xge_queue_h queueh, int data_max_size,
+		xge_queue_item_t *item);
+
+void xge_queue_flush(xge_queue_h queueh);
+
+/* ========================== PRIVATE API ================================= */
+
+xge_queue_status_e __io_queue_grow(xge_queue_h qh);
+
+int __queue_get_reset_critical (xge_queue_h qh);
+
+__EXTERN_END_DECLS
+
+#endif /* XGE_QUEUE_H */
diff --git a/sys/dev/nxge/include/xgehal-channel.h b/sys/dev/nxge/include/xgehal-channel.h
new file mode 100644
index 0000000..8d82530
--- /dev/null
+++ b/sys/dev/nxge/include/xgehal-channel.h
@@ -0,0 +1,507 @@
+/*-
+ * Copyright (c) 2002-2007 Neterion, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ *  FileName :    xgehal-channel.h
+ *
+ *  Description:  HAL channel object functionality
+ *
+ *  Created:      19 May 2004
+ */
+
+#ifndef XGE_HAL_CHANNEL_H
+#define XGE_HAL_CHANNEL_H
+
+#include <dev/nxge/include/xge-os-pal.h>
+#include <dev/nxge/include/xge-list.h>
+#include <dev/nxge/include/xgehal-types.h>
+#include <dev/nxge/include/xgehal-stats.h>
+
+__EXTERN_BEGIN_DECLS
+
+/**
+ * enum xge_hal_channel_type_e - Enumerated channel types.
+ * @XGE_HAL_CHANNEL_TYPE_FIFO: fifo.
+ * @XGE_HAL_CHANNEL_TYPE_RING: ring.
+ * @XGE_HAL_CHANNEL_TYPE_SEND_QUEUE: Send Queue
+ * @XGE_HAL_CHANNEL_TYPE_RECEIVE_QUEUE: Receive Queue
+ * @XGE_HAL_CHANNEL_TYPE_COMPLETION_QUEUE: Receive queue completion queue
+ * @XGE_HAL_CHANNEL_TYPE_UP_MESSAGE_QUEUE: Up message queue
+ * @XGE_HAL_CHANNEL_TYPE_DOWN_MESSAGE_QUEUE: Down message queue
+ * @XGE_HAL_CHANNEL_TYPE_MAX: Maximum number of HAL-supported
+ * (and recognized) channel types. Currently: two.
+ *
+ * Enumerated channel types. Currently there are only two link-layer
+ * channels - Xframe fifo and Xframe ring. In the future the list will grow.
+ */
+typedef enum xge_hal_channel_type_e {
+	XGE_HAL_CHANNEL_TYPE_FIFO,
+	XGE_HAL_CHANNEL_TYPE_RING,
+	XGE_HAL_CHANNEL_TYPE_SEND_QUEUE,
+	XGE_HAL_CHANNEL_TYPE_RECEIVE_QUEUE,
+	XGE_HAL_CHANNEL_TYPE_COMPLETION_QUEUE,
+	XGE_HAL_CHANNEL_TYPE_UP_MESSAGE_QUEUE,
+	XGE_HAL_CHANNEL_TYPE_DOWN_MESSAGE_QUEUE,
+	XGE_HAL_CHANNEL_TYPE_MAX
+} xge_hal_channel_type_e;
+
+/**
+ * enum xge_hal_channel_flag_e - Channel flags.
+ * @XGE_HAL_CHANNEL_FLAG_NONE: zero (nil) flag.
+ * @XGE_HAL_CHANNEL_FLAG_USE_TX_LOCK: use lock when posting transmit
+ * descriptor.
+ * @XGE_HAL_CHANNEL_FLAG_FREE_RXD: to-be-defined.
+ *
+ * Channel opening flags. Reserved for future usage.
+ */
+typedef enum xge_hal_channel_flag_e {
+	XGE_HAL_CHANNEL_FLAG_NONE		= 0x0,
+	XGE_HAL_CHANNEL_FLAG_USE_TX_LOCK	= 0x1,
+	XGE_HAL_CHANNEL_FLAG_FREE_RXD	        = 0x2
+} xge_hal_channel_flag_e;
+
+/**
+ * enum xge_hal_dtr_state_e - Descriptor (DTR) state.
+ * @XGE_HAL_DTR_STATE_NONE: Invalid state.
+ * @XGE_HAL_DTR_STATE_AVAIL: Descriptor is available for reservation
+ * (via xge_hal_fifo_dtr_reserve(), xge_hal_ring_dtr_reserve(), etc.).
+ * @XGE_HAL_DTR_STATE_POSTED: Descriptor is posted for processing by the
+ * device.
+ * @XGE_HAL_DTR_STATE_FREED: Descriptor is free and can be reused for
+ * filling-in and posting later.
+ *
+ * Xframe/HAL descriptor states. For more on descriptor states and transitions
+ * please refer to ch_intern{}.
+ *
+ * See also: xge_hal_channel_dtr_term_f{}.
+ */
+typedef enum xge_hal_dtr_state_e {
+	XGE_HAL_DTR_STATE_NONE		= 0,
+	XGE_HAL_DTR_STATE_AVAIL		= 1,
+	XGE_HAL_DTR_STATE_POSTED	= 2,
+	XGE_HAL_DTR_STATE_FREED		= 3
+} xge_hal_dtr_state_e;
+
+/**
+ * enum xge_hal_channel_reopen_e - Channel open, close, or reopen option.
+ * @XGE_HAL_CHANNEL_RESET_ONLY: Do not (de)allocate channel; used with
+ * xge_hal_channel_open(), xge_hal_channel_close().
+ * @XGE_HAL_CHANNEL_OC_NORMAL: Do (de)allocate channel; used with
+ * xge_hal_channel_open(), xge_hal_channel_close().
+ *
+ * Enumerates options used with channel open and close operations.
+ * The @XGE_HAL_CHANNEL_RESET_ONLY can be used when resetting the device;
+ * in this case there is actually no need to free and then again malloc
+ * the memory (including DMA-able memory) used for channel operation.
+ */
+typedef enum xge_hal_channel_reopen_e {
+	XGE_HAL_CHANNEL_RESET_ONLY	= 1,
+	XGE_HAL_CHANNEL_OC_NORMAL	= 2
+} xge_hal_channel_reopen_e;
+
+/**
+ * function xge_hal_channel_callback_f - Channel callback.
+ * @channelh: Channel "containing" 1 or more completed descriptors.
+ * @dtrh: First completed descriptor.
+ * @t_code: Transfer code, as per Xframe User Guide.
+ *          Returned by HAL.
+ * @host_control: Opaque 64bit data stored by ULD inside the Xframe
+ *            descriptor prior to posting the latter on the channel
+ *            via xge_hal_fifo_dtr_post() or xge_hal_ring_dtr_post().
+ *            The @host_control is returned as is to the ULD with each
+ *            completed descriptor.
+ * @userdata: Opaque per-channel data specified at channel open
+ *            time, via xge_hal_channel_open().
+ *
+ * Channel completion callback (type declaration). A single per-channel
+ * callback is specified at channel open time, via
+ * xge_hal_channel_open().
+ * Typically gets called as part of the processing of the Interrupt
+ * Service Routine.
+ *
+ * Channel callback gets called by HAL if, and only if, there is at least
+ * one new completion on a given ring or fifo channel. Upon processing the
+ * first @dtrh ULD is _supposed_ to continue consuming completions
+ * usingáone of the following HAL APIs:
+ *    - xge_hal_fifo_dtr_next_completed()
+ *      or
+ *    - xge_hal_ring_dtr_next_completed().
+ *
+ * Note that failure to process new completions in a timely fashion
+ * leads to XGE_HAL_INF_OUT_OF_DESCRIPTORS condition.
+ *
+ * Non-zero @t_code means failure to process (transmit or receive, depending
+ * on the channel type) the descriptor.
+ *
+ * In the "transmit" case the failure could happen, for instance, when the
+ * link is down, in which case Xframe completes the descriptor because it
+ * is not able to send the data out.
+ *
+ * For details please refer to Xframe User Guide.
+ *
+ * See also: xge_hal_fifo_dtr_next_completed(),
+ * xge_hal_ring_dtr_next_completed(), xge_hal_channel_dtr_term_f{}.
+ */
+typedef xge_hal_status_e (*xge_hal_channel_callback_f)
+				(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
+				 u8 t_code, void *userdata);
+
+/**
+ * function xge_hal_channel_dtr_init_f - Initialize descriptor callback.
+ * @channelh: Channel "containing" the @dtrh descriptor.
+ * @dtrh: Descriptor.
+ * @index: Index of the descriptor in the channel's set of descriptors.
+ * @userdata: Per-channel user data (a.k.a. context) specified at
+ * channel open time, via xge_hal_channel_open().
+ * @reopen: See  xge_hal_channel_reopen_e{}.
+ *
+ * Initialize descriptor callback. Unless NULL is specified in the
+ * xge_hal_channel_attr_t{} structure passed to xge_hal_channel_open()),
+ * HAL invokes the callback as part of the xge_hal_channel_open()
+ * implementation.
+ * For the ring type of channel the ULD is expected to fill in this descriptor
+ * with buffer(s) and control information.
+ * For the fifo type of channel the ULD could use the callback to
+ * pre-set DMA mappings and/or alignment buffers.
+ *
+ * See also: xge_hal_channel_attr_t{}, xge_hal_channel_dtr_term_f{}.
+ */
+typedef xge_hal_status_e (*xge_hal_channel_dtr_init_f)
+				(xge_hal_channel_h channelh,
+				 xge_hal_dtr_h dtrh,
+				 int index,
+				 void *userdata,
+				 xge_hal_channel_reopen_e reopen);
+
+/**
+ * function xge_hal_channel_dtr_term_f - Terminate descriptor callback.
+ * @channelh: Channel "containing" the @dtrh descriptor.
+ * @dtrh: First completed descriptor.
+ * @state: One of the xge_hal_dtr_state_e{} enumerated states.
+ * @userdata: Per-channel user data (a.k.a. context) specified at
+ * channel open time, via xge_hal_channel_open().
+ * @reopen: See  xge_hal_channel_reopen_e{}.
+ *
+ * Terminate descriptor callback. Unless NULL is specified in the
+ * xge_hal_channel_attr_t{} structure passed to xge_hal_channel_open()),
+ * HAL invokes the callback as part of closing the corresponding
+ * channel, prior to de-allocating the channel and associated data
+ * structures (including descriptors).
+ * ULD should utilize the callback to (for instance) unmap
+ * and free DMA data buffers associated with the posted (state =
+ * XGE_HAL_DTR_STATE_POSTED) descriptors,
+ * as well as other relevant cleanup functions.
+ *
+ * See also: xge_hal_channel_attr_t{}, xge_hal_channel_dtr_init_f{}.
+ */
+typedef void (*xge_hal_channel_dtr_term_f) (xge_hal_channel_h channelh,
+					    xge_hal_dtr_h dtrh,
+					    xge_hal_dtr_state_e	state,
+					    void *userdata,
+					    xge_hal_channel_reopen_e reopen);
+
+
+/**
+ * struct xge_hal_channel_attr_t - Channel open "template".
+ * @type: xge_hal_channel_type_e channel type.
+ * @vp_id: Virtual path id
+ * @post_qid: Queue ID to post descriptors. For the link layer this
+ *            number should be in the 0..7 range.
+ * @compl_qid: Completion queue ID. Must be set to zero for the link layer.
+ * @callback: Channel completion callback. HAL invokes the callback when there
+ *            are new completions on that channel. In many implementations
+ *            the @callback executes in the hw interrupt context.
+ * @dtr_init: Channel's descriptor-initialize callback.
+ *            See xge_hal_channel_dtr_init_f{}.
+ *            If not NULL, HAL invokes the callback when opening
+ *            the channel via xge_hal_channel_open().
+ * @dtr_term: Channel's descriptor-terminate callback. If not NULL,
+ *          HAL invokes the callback when closing the corresponding channel.
+ *          See also xge_hal_channel_dtr_term_f{}.
+ * @userdata: User-defined "context" of _that_ channel. Passed back to the
+ *            user as one of the @callback, @dtr_init, and @dtr_term arguments.
+ * @per_dtr_space: If specified (i.e., greater than zero): extra space
+ *              reserved by HAL per each transmit or receive (depending on the
+ *              channel type) descriptor. Can be used to store,
+ *              and retrieve on completion, information specific
+ *              to the upper-layer.
+ * @flags: xge_hal_channel_flag_e enumerated flags.
+ *
+ * Channel open "template". User fills the structure with channel
+ * attributes and passes it to xge_hal_channel_open().
+ * Usage: See ex_open{}.
+ */
+typedef struct xge_hal_channel_attr_t {
+	xge_hal_channel_type_e		type;
+#ifdef XGEHAL_RNIC
+	u32				vp_id;
+#endif
+	int				post_qid;
+	int				compl_qid;
+	xge_hal_channel_callback_f	callback;
+	xge_hal_channel_dtr_init_f	dtr_init;
+	xge_hal_channel_dtr_term_f	dtr_term;
+	void				*userdata;
+	int				per_dtr_space;
+	xge_hal_channel_flag_e		flags;
+} xge_hal_channel_attr_t;
+
+/*
+ * xge_hal_channel_t
+ * ---------- complete/free section ---------------
+ * @item: List item; used to maintain a list of open channels.
+ * @callback: Channel completion callback. See
+ * xge_hal_channel_callback_f.
+ * @compl_index: Completion index. At any point in time points on the
+ *               position in the channel, which will contain next
+ *               to-be-completed descriptor.
+ * @length: Channel length. Currently allocated number of descriptors.
+ *          The channel length "grows" when more descriptors get allocated.
+ *          See _hal_mempool_grow.
+ * @free_arr: Free array. Contains completed descriptors that were freed
+ *            (i.e., handed over back to HAL) by ULD.
+ *            See xge_hal_fifo_dtr_free(), xge_hal_ring_dtr_free().
+ * @free_lock: Lock to protect @free_arr.
+ * ----------- reserve/post section ---------------
+ * @post_index: Post index. At any point in time points on the
+ *              position in the channel, which'll contain next to-be-posted
+ *              descriptor.
+ * @post_lock: Lock to serialize multiple concurrent "posters" of descriptors
+ *             on the given channel.
+ * @reserve_arr: Reserve array. Contains descriptors that can be reserved
+ *               by ULD for the subsequent send or receive operation.
+ *               See xge_hal_fifo_dtr_reserve(),
+ *               xge_hal_ring_dtr_reserve().
+ * @reserve_length: Length of the @reserve_arr. The length dynamically
+ *                  changes: it decrements each time descriptor is reserved.
+ * @reserve_lock: Lock to serialize multiple concurrent threads accessing
+ *                @reserve_arr.
+ * @reserve_threshold: Reserve threshold. Minimal number of free descriptors
+ *                     that ought to be preserved in the channel at all times.
+ *                     Note that @reserve_threshold >= 0 &&
+ *                     @reserve_threshold < @reserve_max.
+ * ------------ common section --------------------
+ * @devh: Device handle. HAL device object that contains _this_ channel.
+ * @dmah: Channel's DMA address. Used to synchronize (to/from device)
+ *        descriptors.
+ * @regh0: Base address of the device memory space handle. Copied from HAL device
+ *         at channel open time.
+ * @regh1: Base address of the device memory space handle. Copied from HAL device
+ *         at channel open time.
+ * @userdata: Per-channel opaque (void*) user-defined context, which may be
+ *            upper-layer driver object, ULP connection, etc.
+ *            Once channel is open, @userdata is passed back to user via
+ *            xge_hal_channel_callback_f.
+ * @work_arr: Work array. Contains descriptors posted to the channel.
+ *            Note that at any point in time @work_arr contains 3 types of
+ *            descriptors:
+ *            1) posted but not yet consumed by Xframe device;
+ *            2) consumed but not yet completed;
+ *            3) completed but not yet freed
+ *            (via xge_hal_fifo_dtr_free() or xge_hal_ring_dtr_free())
+ * @saved_arr: Array used internally to optimize channel full-duplex
+ *             operation.
+ * @stats: Channel statistcis. Includes HAL internal counters, including
+ *         for instance, number of times out-of-descriptors
+ *         (see XGE_HAL_INF_OUT_OF_DESCRIPTORS) condition happened.
+ * ------------- "slow" section  ------------------
+ * @type: Channel type. See xge_hal_channel_type_e{}.
+ * @vp_id: Virtual path id
+ * @post_qid: Identifies Xframe queue used for posting descriptors.
+ * @compl_qid: Identifies Xframe completion queue.
+ * @flags: Channel flags. See xge_hal_channel_flag_e{}.
+ * @reserve_initial: Initial number of descriptors allocated at channel open
+ *                   time (see xge_hal_channel_open()). The number of
+ *                   channel descriptors can grow at runtime
+ *                   up to @reserve_max value.
+ * @reserve_max: Maximum number of channel descriptors. See @reserve_initial.
+ * @is_open: True, if channel is open; false - otherwise.
+ * @per_dtr_space: Per-descriptor space (in bytes) that channel user can utilize
+ *                 to store per-operation control information.
+ * HAL channel object. HAL devices (see xge_hal_device_t{}) contains
+ * zero or more channels. HAL channel contains zero or more descriptors. The
+ * latter are used by ULD(s) to manage the device and/or send and receive data
+ * to remote peer(s) via the channel.
+ *
+ * See also: xge_hal_channel_type_e{}, xge_hal_channel_flag_e,
+ * xge_hal_channel_callback_f{}
+ */
+typedef struct {
+	/* complete/free section */
+	xge_list_t			item;
+	xge_hal_channel_callback_f	callback;
+	void				**free_arr;
+	int				length;
+	int				free_length;
+#if defined(XGE_HAL_RX_MULTI_FREE_IRQ) || defined(XGE_HAL_TX_MULTI_FREE_IRQ) || \
+    defined(XGE_HAL_RX_MULTI_FREE) || defined(XGE_HAL_TX_MULTI_FREE)
+	spinlock_t			free_lock;
+#endif
+	int				compl_index;
+	unsigned int			usage_cnt;
+	unsigned int			poll_bytes;
+	int				unused0;
+
+	/* reserve/post data path section */
+#ifdef __XGE_WIN__
+	int				__xge_os_attr_cacheline_aligned
+					post_index;
+#else
+	int				post_index
+					__xge_os_attr_cacheline_aligned;
+#endif
+	spinlock_t			reserve_lock;
+	spinlock_t			post_lock;
+
+	void				**reserve_arr;
+	int				reserve_length;
+	int				reserve_threshold;
+	int				reserve_top;
+	int                             unused1;
+
+	/* common section */
+	xge_hal_device_h		devh;
+	pci_dev_h                       pdev;
+	pci_reg_h			regh0;
+	pci_reg_h			regh1;
+	void				*userdata;
+	void				**work_arr;
+	void				**saved_arr;
+	void				**orig_arr;
+	xge_hal_stats_channel_info_t	stats;
+
+	/* slow section */
+	xge_hal_channel_type_e		type;
+#ifdef XGEHAL_RNIC
+	u32				vp_id;
+#endif
+	int				post_qid;
+	int				compl_qid;
+	xge_hal_channel_flag_e		flags;
+	int				reserve_initial;
+	int				reserve_max;
+	int				is_open;
+	int				per_dtr_space;
+	xge_hal_channel_dtr_term_f	dtr_term;
+	xge_hal_channel_dtr_init_f	dtr_init;
+	/* MSI stuff */
+	u32				msi_msg;
+	u8				rti;
+	u8				tti;
+	u16                             unused2;
+	/* MSI-X stuff */
+	u64				msix_address;
+	u32				msix_data;
+	int				msix_idx;
+	volatile int			in_interrupt;
+        unsigned int			magic;
+#ifdef __XGE_WIN__
+} __xge_os_attr_cacheline_aligned xge_hal_channel_t ;
+#else
+} xge_hal_channel_t __xge_os_attr_cacheline_aligned;
+#endif
+
+/* ========================== CHANNEL PRIVATE API ========================= */
+
+xge_hal_status_e
+__hal_channel_initialize(xge_hal_channel_h channelh,
+		xge_hal_channel_attr_t *attr, void **reserve_arr,
+		int reserve_initial, int reserve_max, int reserve_threshold);
+
+void __hal_channel_terminate(xge_hal_channel_h channelh);
+
+xge_hal_channel_t*
+__hal_channel_allocate(xge_hal_device_h devh, int post_qid,
+#ifdef XGEHAL_RNIC
+		u32 vp_id,
+#endif
+		xge_hal_channel_type_e	type);
+
+void __hal_channel_free(xge_hal_channel_t *channel);
+
+#if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_CHANNEL)
+#define __HAL_STATIC_CHANNEL
+#define __HAL_INLINE_CHANNEL
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
+__hal_channel_dtr_alloc(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
+__hal_channel_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
+__hal_channel_dtr_try_complete(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
+__hal_channel_dtr_complete(xge_hal_channel_h channelh);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
+__hal_channel_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
+__hal_channel_dtr_dealloc(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
+__hal_channel_dtr_restore(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
+			  int offset);
+
+/* ========================== CHANNEL PUBLIC API ========================= */
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int
+xge_hal_channel_dtr_count(xge_hal_channel_h channelh);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void*
+xge_hal_channel_userdata(xge_hal_channel_h channelh);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int
+xge_hal_channel_id(xge_hal_channel_h channelh);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int
+xge_hal_check_alignment(dma_addr_t dma_pointer, int size, int alignment,
+		int copy_size);
+
+#else /* XGE_FASTPATH_EXTERN */
+#define __HAL_STATIC_CHANNEL static
+#define __HAL_INLINE_CHANNEL inline
+#include <dev/nxge/xgehal/xgehal-channel-fp.c>
+#endif /* XGE_FASTPATH_INLINE */
+
+xge_hal_status_e
+xge_hal_channel_open(xge_hal_device_h hldev, xge_hal_channel_attr_t *attr,
+		     xge_hal_channel_h *channel,
+		     xge_hal_channel_reopen_e reopen);
+
+void xge_hal_channel_close(xge_hal_channel_h channelh,
+                           xge_hal_channel_reopen_e reopen);
+
+void xge_hal_channel_abort(xge_hal_channel_h channelh,
+                           xge_hal_channel_reopen_e reopen);
+
+__EXTERN_END_DECLS
+
+#endif /* XGE_HAL_CHANNEL_H */
diff --git a/sys/dev/nxge/include/xgehal-config.h b/sys/dev/nxge/include/xgehal-config.h
new file mode 100644
index 0000000..c7bde29
--- /dev/null
+++ b/sys/dev/nxge/include/xgehal-config.h
@@ -0,0 +1,1012 @@
+/*-
+ * Copyright (c) 2002-2007 Neterion, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ *  FileName :    xgehal-config.h
+ *
+ *  Description:  Xframe configuration.
+ *
+ *  Created:      14 May 2004
+ */
+
+#ifndef XGE_HAL_CONFIG_H
+#define XGE_HAL_CONFIG_H
+
+#include <dev/nxge/include/xge-os-pal.h>
+#include <dev/nxge/include/xgehal-types.h>
+#include <dev/nxge/include/xge-queue.h>
+
+__EXTERN_BEGIN_DECLS
+
+#define	XGE_HAL_DEFAULT_USE_HARDCODE		-1
+
+#ifdef XGEHAL_RNIC
+#define	XGE_HAL_MAX_VIRTUAL_PATHS		17
+#else
+#define	XGE_HAL_MAX_VIRTUAL_PATHS		8
+#endif
+#define	XGE_HAL_MAX_INTR_PER_VP			4
+
+
+/**
+ * struct xge_hal_tti_config_t - Xframe Tx interrupt configuration.
+ * @enabled: Set to 1, if TTI feature is enabled.
+ * @urange_a: Link utilization range A. The value from 0 to 100%.
+ * @ufc_a: Frame count for the utilization range A. Interrupt will be generated
+ *         each time when (and only when) the line is utilized no more
+ *         than @urange_a percent in the transmit direction,
+ *         and number of transmitted frames is greater or equal @ufc_a.
+ * @urange_b: Link utilization range B.
+ * @ufc_b: Frame count for the utilization range B.
+ * @urange_c: Link utilization range C.
+ * @ufc_c: Frame count for the utilization range C.
+ * @urange_d: Link utilization range D.
+ * @ufc_d: Frame count for the utilization range D.
+ * @timer_val_us: Interval of time, in microseconds, at which transmit timer
+ *             interrupt is to be generated. Note that unless @timer_ci_en
+ *             is set, the timer interrupt is generated only in presence
+ *             of the transmit traffic. Note also that timer interrupt
+ *             and utilization interrupt are two separate interrupt
+ *             sources.
+ * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization
+ *               interrupt was generated during the interval.
+ * @timer_ci_en: Enable/disable continuous interrupt. Set this value
+ *               to 1 in order to generate continuous interrupt
+ *               at fixed @timer_val intervals of time, independently
+ *               of whether there is transmit traffic or not.
+ * @enabled: Set to 1, if TTI feature is enabled.
+ *
+ * Xframe transmit interrupt configuration.
+ * See Xframe User Guide, Section 3.5 "Device Interrupts"
+ * for more details. Note also (min, max)
+ * ranges in the body of the xge_hal_tx_intr_config_t structure.
+ * Note: Valid (min, max) range for each attribute is specified in the body of
+ * the xge_hal_tti_config_t{} structure. Please refer to the
+ * corresponding header file.
+ */
+typedef struct xge_hal_tti_config_t {
+
+	int				enabled;
+#define XGE_HAL_TTI_ENABLE			1
+#define XGE_HAL_TTI_DISABLE			0
+
+	/* Line utilization interrupts */
+
+	int				urange_a;
+#define XGE_HAL_MIN_TX_URANGE_A			0
+#define XGE_HAL_MAX_TX_URANGE_A			100
+
+	int				ufc_a;
+#define XGE_HAL_MIN_TX_UFC_A			0
+#define XGE_HAL_MAX_TX_UFC_A			65535
+
+	int				urange_b;
+#define XGE_HAL_MIN_TX_URANGE_B			0
+#define XGE_HAL_MAX_TX_URANGE_B			100
+
+	int				ufc_b;
+#define XGE_HAL_MIN_TX_UFC_B			0
+#define XGE_HAL_MAX_TX_UFC_B			65535
+
+	int				urange_c;
+#define XGE_HAL_MIN_TX_URANGE_C			0
+#define XGE_HAL_MAX_TX_URANGE_C			100
+
+	int				ufc_c;
+#define XGE_HAL_MIN_TX_UFC_C			0
+#define XGE_HAL_MAX_TX_UFC_C			65535
+
+	int				ufc_d;
+#define XGE_HAL_MIN_TX_UFC_D			0
+#define XGE_HAL_MAX_TX_UFC_D			65535
+
+	int				timer_val_us;
+#define XGE_HAL_MIN_TX_TIMER_VAL		0
+#define XGE_HAL_MAX_TX_TIMER_VAL		65535
+
+	int				timer_ac_en;
+#define XGE_HAL_MIN_TX_TIMER_AC_EN		0
+#define XGE_HAL_MAX_TX_TIMER_AC_EN		1
+
+	int				timer_ci_en;
+#define XGE_HAL_MIN_TX_TIMER_CI_EN		0
+#define XGE_HAL_MAX_TX_TIMER_CI_EN		1
+
+
+} xge_hal_tti_config_t;
+
+/**
+ * struct xge_hal_rti_config_t - Xframe Rx interrupt configuration.
+ * @urange_a: Link utilization range A. The value from 0 to 100%.
+ * @ufc_a: Frame count for the utilization range A. Interrupt will be generated
+ *         each time when (and only when) the line is utilized no more
+ *         than @urange_a percent inbound,
+ *         and number of received frames is greater or equal @ufc_a.
+ * @urange_b: Link utilization range B.
+ * @ufc_b: Frame count for the utilization range B.
+ * @urange_c: Link utilization range C.
+ * @ufc_c: Frame count for the utilization range C.
+ * @urange_d: Link utilization range D.
+ * @ufc_d: Frame count for the utilization range D.
+ * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization
+ *               interrupt was generated during the interval.
+ * @timer_val_us: Interval of time, in microseconds, at which receive timer
+ *             interrupt is to be generated. The timer interrupt is generated
+ *             only in presence of the inbound traffic. Note also that timer
+ *             interrupt and utilization interrupt are two separate interrupt
+ *             sources.
+ *
+ * Xframe receive interrupt configuration.
+ * See Xframe User Guide, Section 3.5 "Device Interrupts"
+ * for more details. Note also (min, max)
+ * ranges in the body of the xge_hal_intr_config_t structure.
+ * Note: Valid (min, max) range for each attribute is specified in the body of
+ * the xge_hal_rti_config_t{} structure. Please refer to the
+ * corresponding header file.
+ */
+typedef struct xge_hal_rti_config_t {
+
+	int				urange_a;
+#define XGE_HAL_MIN_RX_URANGE_A			0
+#define XGE_HAL_MAX_RX_URANGE_A			127
+
+	int				ufc_a;
+#define XGE_HAL_MIN_RX_UFC_A			0
+#define XGE_HAL_MAX_RX_UFC_A			65535
+
+	int				urange_b;
+#define XGE_HAL_MIN_RX_URANGE_B			0
+#define XGE_HAL_MAX_RX_URANGE_B			127
+
+	int				ufc_b;
+#define XGE_HAL_MIN_RX_UFC_B			0
+#define XGE_HAL_MAX_RX_UFC_B			65535
+
+	int				urange_c;
+#define XGE_HAL_MIN_RX_URANGE_C			0
+#define XGE_HAL_MAX_RX_URANGE_C			127
+
+	int				ufc_c;
+#define XGE_HAL_MIN_RX_UFC_C			0
+#define XGE_HAL_MAX_RX_UFC_C			65535
+
+	int				ufc_d;
+#define XGE_HAL_MIN_RX_UFC_D			0
+#define XGE_HAL_MAX_RX_UFC_D			65535
+
+	int				timer_ac_en;
+#define XGE_HAL_MIN_RX_TIMER_AC_EN		0
+#define XGE_HAL_MAX_RX_TIMER_AC_EN		1
+
+	int				timer_val_us;
+#define XGE_HAL_MIN_RX_TIMER_VAL		0
+#define XGE_HAL_MAX_RX_TIMER_VAL		65535
+
+} xge_hal_rti_config_t;
+
+/**
+ * struct xge_hal_fifo_queue_t - Single fifo configuration.
+ * @max: Max numbers of TxDLs (that is, lists of Tx descriptors) per queue.
+ * @initial: Initial numbers of TxDLs per queue (can grow up to @max).
+ * @intr: Boolean. Use 1 to generate interrupt for  each completed TxDL.
+ *        Use 0 otherwise.
+ * @intr_vector: TBD
+ * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation,
+ *              which generally improves latency of the host bridge operation
+ *              (see PCI specification). For valid values please refer
+ *              to xge_hal_fifo_queue_t{} in the driver sources.
+ * @priority: TBD
+ * @configured: Boolean. Use 1 to specify that the fifo is configured.
+ *              Only "configured" fifos can be activated and used to post
+ *              Tx descriptors. Any subset of 8 available fifos can be
+ *              "configured".
+ * @tti: TBD
+ *
+ * Single fifo configuration.
+ * Note: Valid (min, max) range for each attribute is specified in the body of
+ * the xge_hal_fifo_queue_t{} structure. Please refer to the
+ * corresponding header file.
+ * See also: xge_hal_fifo_config_t{}
+ */
+typedef struct xge_hal_fifo_queue_t {
+	int				max;
+	int				initial;
+#define XGE_HAL_MIN_FIFO_QUEUE_LENGTH		2
+#define XGE_HAL_MAX_FIFO_QUEUE_LENGTH		8192
+
+	int		                intr;
+#define XGE_HAL_MIN_FIFO_QUEUE_INTR		0
+#define XGE_HAL_MAX_FIFO_QUEUE_INTR		1
+
+	int				intr_vector;
+#define	XGE_HAL_MIN_FIFO_QUEUE_INTR_VECTOR	0
+#define	XGE_HAL_MAX_FIFO_QUEUE_INTR_VECTOR	64
+
+	int				no_snoop_bits;
+#define XGE_HAL_MIN_FIFO_QUEUE_NO_SNOOP_DISABLED	0
+#define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_TXD	1
+#define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_BUFFER	2
+#define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_ALL	3
+
+	int				priority;
+#define XGE_HAL_MIN_FIFO_PRIORITY		0
+#define XGE_HAL_MAX_FIFO_PRIORITY		63
+
+	int				configured;
+#define XGE_HAL_MIN_FIFO_CONFIGURED		0
+#define XGE_HAL_MAX_FIFO_CONFIGURED		1
+
+#define XGE_HAL_MAX_FIFO_TTI_NUM		7
+#define XGE_HAL_MAX_FIFO_TTI_RING_0		56
+	xge_hal_tti_config_t		tti[XGE_HAL_MAX_FIFO_TTI_NUM];
+
+} xge_hal_fifo_queue_t;
+
+/**
+ * struct xge_hal_fifo_config_t - Configuration of all 8 fifos.
+ * @max_frags: Max number of Tx buffers per TxDL (that is, per single
+ *             transmit operation).
+ *             No more than 256 transmit buffers can be specified.
+ * @max_aligned_frags: Number of fragments to be aligned out of
+ *             maximum fragments (see @max_frags).
+ * @reserve_threshold: Descriptor reservation threshold.
+ *                     At least @reserve_threshold descriptors will remain
+ *                     unallocated at all times.
+ * @memblock_size: Fifo descriptors are allocated in blocks of @mem_block_size
+ *                 bytes. Setting @memblock_size to page size ensures
+ *                 by-page allocation of descriptors. 128K bytes is the
+ *                 maximum supported block size.
+ * @queue: Array of per-fifo configurations.
+ * @alignment_size: per Tx fragment DMA-able memory used to align transmit data
+ *                  (e.g., to align on a cache line).
+ *
+ * Configuration of all Xframe fifos. Includes array of xge_hal_fifo_queue_t
+ * structures.
+ * Note: Valid (min, max) range for each attribute is specified in the body of
+ * the xge_hal_fifo_config_t{} structure. Please refer to the
+ * corresponding header file.
+ * See also: xge_hal_ring_queue_t{}.
+ */
+typedef struct xge_hal_fifo_config_t {
+	int				max_frags;
+#define XGE_HAL_MIN_FIFO_FRAGS			1
+#define XGE_HAL_MAX_FIFO_FRAGS			256
+
+	int				reserve_threshold;
+#define XGE_HAL_MIN_FIFO_RESERVE_THRESHOLD	0
+#define XGE_HAL_MAX_FIFO_RESERVE_THRESHOLD	8192
+
+	int				memblock_size;
+#define XGE_HAL_MIN_FIFO_MEMBLOCK_SIZE		4096
+#define XGE_HAL_MAX_FIFO_MEMBLOCK_SIZE		131072
+
+	int		                alignment_size;
+#define XGE_HAL_MIN_ALIGNMENT_SIZE		0
+#define XGE_HAL_MAX_ALIGNMENT_SIZE		65536
+
+	int				max_aligned_frags;
+	/* range: (1, @max_frags) */
+
+#define XGE_HAL_MIN_FIFO_NUM			1
+#define XGE_HAL_MAX_FIFO_NUM_HERC		8
+#define XGE_HAL_MAX_FIFO_NUM_TITAN		(XGE_HAL_MAX_VIRTUAL_PATHS - 1)
+#define XGE_HAL_MAX_FIFO_NUM			(XGE_HAL_MAX_VIRTUAL_PATHS)
+	xge_hal_fifo_queue_t		queue[XGE_HAL_MAX_FIFO_NUM];
+} xge_hal_fifo_config_t;
+
+/**
+ * struct xge_hal_rts_port_t - RTS port entry
+ * @num: Port number
+ * @udp: Port is UDP (default TCP)
+ * @src: Port is Source (default Destination)
+ */
+typedef struct xge_hal_rts_port_t {
+	int				num;
+	int				udp;
+	int				src;
+} xge_hal_rts_port_t;
+
+/**
+ * struct xge_hal_ring_queue_t - Single ring configuration.
+ * @max: Max numbers of RxD blocks per queue
+ * @initial: Initial numbers of RxD blocks per queue
+ *           (can grow up to @max)
+ * @buffer_mode: Receive buffer mode (1, 2, 3, or 5); for details please refer
+ *               to Xframe User Guide.
+ * @dram_size_mb: Size (in MB) of Xframe DRAM used for _that_ ring.
+ *                Note that 64MB of available
+ *                on-board DRAM is shared between receive rings.
+ *                If a single ring is used, @dram_size_mb can be set to 64.
+ *                Sum of all rings' @dram_size_mb cannot exceed 64.
+ * @intr_vector: TBD
+ * @backoff_interval_us: Time (in microseconds), after which Xframe
+ *      tries to download RxDs posted by the host.
+ *      Note that the "backoff" does not happen if host posts receive
+ *      descriptors in the timely fashion.
+ * @max_frm_len: Maximum frame length that can be received on _that_ ring.
+ *               Setting this field to -1 ensures that the ring will
+ *               "accept" MTU-size frames (note that MTU can be changed at
+ *               runtime).
+ *               Any value other than (-1) specifies a certain "hard"
+ *               limit on the receive frame sizes.
+ *               The field can be used to activate receive frame-length based
+ *               steering.
+ * @priority:    Ring priority. 0 - highest, 7 - lowest. The value is used
+ *               to give prioritized access to PCI-X. See Xframe documentation
+ *               for details.
+ * @rth_en: Enable Receive Traffic Hashing (RTH).
+ * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation,
+ *              which generally improves latency of the host bridge operation
+ *              (see PCI specification). For valid values please refer
+ *              to xge_hal_ring_queue_t{} in the driver sources.
+ * @indicate_max_pkts: Sets maximum number of received frames to be processed
+ *              within single interrupt.
+ * @configured: Boolean. Use 1 to specify that the ring is configured.
+ *              Only "configured" rings can be activated and used to post
+ *              Rx descriptors. Any subset of 8 available rings can be
+ *              "configured".
+ * @rts_mac_en: 1 - To enable Receive MAC address steering.
+ *		0 - To disable Receive MAC address steering.
+ * @rth_en: TBD
+ * @rts_port_en: TBD
+ * @rts_ports: TBD
+ * @rti: Xframe receive interrupt configuration.
+ *
+ * Single ring configuration.
+ * Note: Valid (min, max) range for each attribute is specified in the body of
+ * the xge_hal_ring_queue_t{} structure. Please refer to the
+ * corresponding header file.
+ * See also: xge_hal_fifo_config_t{}.
+ */
+typedef struct xge_hal_ring_queue_t {
+	int				max;
+	int				initial;
+#define XGE_HAL_MIN_RING_QUEUE_BLOCKS		1
+#define XGE_HAL_MAX_RING_QUEUE_BLOCKS		64
+
+	int				buffer_mode;
+#define XGE_HAL_RING_QUEUE_BUFFER_MODE_1	1
+#define XGE_HAL_RING_QUEUE_BUFFER_MODE_2	2
+#define XGE_HAL_RING_QUEUE_BUFFER_MODE_3	3
+#define XGE_HAL_RING_QUEUE_BUFFER_MODE_5	5
+
+	int				dram_size_mb;
+#define XGE_HAL_MIN_RING_QUEUE_SIZE		0
+#define XGE_HAL_MAX_RING_QUEUE_SIZE_XENA	64
+#define XGE_HAL_MAX_RING_QUEUE_SIZE_HERC	32
+
+	int				intr_vector;
+#define	XGE_HAL_MIN_RING_QUEUE_INTR_VECTOR	0
+#define	XGE_HAL_MAX_RING_QUEUE_INTR_VECTOR	64
+
+	int				backoff_interval_us;
+#define XGE_HAL_MIN_BACKOFF_INTERVAL_US		1
+#define XGE_HAL_MAX_BACKOFF_INTERVAL_US		125000
+
+	int				max_frm_len;
+#define XGE_HAL_MIN_MAX_FRM_LEN			-1
+#define XGE_HAL_MAX_MAX_FRM_LEN			9622
+
+	int				priority;
+#define XGE_HAL_MIN_RING_PRIORITY		0
+#define XGE_HAL_MAX_RING_PRIORITY		7
+
+	int				no_snoop_bits;
+#define XGE_HAL_MIN_RING_QUEUE_NO_SNOOP_DISABLED	0
+#define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_RXD	1
+#define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_BUFFER	2
+#define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_ALL	3
+
+	int				indicate_max_pkts;
+#define XGE_HAL_MIN_RING_INDICATE_MAX_PKTS	1
+#define XGE_HAL_MAX_RING_INDICATE_MAX_PKTS	65536
+
+	int				configured;
+#define XGE_HAL_MIN_RING_CONFIGURED		0
+#define XGE_HAL_MAX_RING_CONFIGURED		1
+
+	int				rts_mac_en;
+#define XGE_HAL_MIN_RING_RTS_MAC_EN		0
+#define XGE_HAL_MAX_RING_RTS_MAC_EN		1
+
+	int				rth_en;
+#define XGE_HAL_MIN_RING_RTH_EN			0
+#define XGE_HAL_MAX_RING_RTH_EN			1
+
+	int				rts_port_en;
+#define XGE_HAL_MIN_RING_RTS_PORT_EN		0
+#define XGE_HAL_MAX_RING_RTS_PORT_EN		1
+
+#define XGE_HAL_MAX_STEERABLE_PORTS		32
+	xge_hal_rts_port_t			rts_ports[XGE_HAL_MAX_STEERABLE_PORTS];
+
+	xge_hal_rti_config_t		rti;
+
+} xge_hal_ring_queue_t;
+
+/**
+ * struct xge_hal_ring_config_t - Array of ring configurations.
+ * @memblock_size: Ring descriptors are allocated in blocks of @mem_block_size
+ *                 bytes. Setting @memblock_size to page size ensures
+ *                 by-page allocation of descriptors. 128K bytes is the
+ *                 upper limit.
+ * @scatter_mode: Xframe supports two receive scatter modes: A and B.
+ *                For details please refer to Xframe User Guide.
+ * @strip_vlan_tag: TBD
+ * @queue: Array of all Xframe ring configurations.
+ *
+ * Array of ring configurations.
+ * See also: xge_hal_ring_queue_t{}.
+ */
+typedef struct xge_hal_ring_config_t {
+
+	int				memblock_size;
+#define XGE_HAL_MIN_RING_MEMBLOCK_SIZE		4096
+#define XGE_HAL_MAX_RING_MEMBLOCK_SIZE		131072
+
+	int				scatter_mode;
+#define XGE_HAL_RING_QUEUE_SCATTER_MODE_A		0
+#define XGE_HAL_RING_QUEUE_SCATTER_MODE_B		1
+
+	int				strip_vlan_tag;
+#define XGE_HAL_RING_DONOT_STRIP_VLAN_TAG	0
+#define XGE_HAL_RING_STRIP_VLAN_TAG		1
+
+#define XGE_HAL_MIN_RING_NUM			1
+#define XGE_HAL_MAX_RING_NUM_HERC		8
+#define XGE_HAL_MAX_RING_NUM_TITAN		(XGE_HAL_MAX_VIRTUAL_PATHS - 1)
+#define XGE_HAL_MAX_RING_NUM			(XGE_HAL_MAX_VIRTUAL_PATHS)
+	xge_hal_ring_queue_t		queue[XGE_HAL_MAX_RING_NUM];
+
+} xge_hal_ring_config_t;
+
+/**
+ * struct xge_hal_mac_config_t - MAC configuration.
+ * @media: Transponder type.
+ * @tmac_util_period: The sampling period over which the transmit utilization
+ *                    is calculated.
+ * @rmac_util_period: The sampling period over which the receive utilization
+ *                    is calculated.
+ * @rmac_strip_pad: Determines whether padding of received frames is removed by
+ *                  the MAC or sent to the host.
+ * @rmac_bcast_en: Enable frames containing broadcast address to be
+ *                 passed to the host.
+ * @rmac_pause_gen_en: Received pause generation enable.
+ * @rmac_pause_rcv_en: Receive pause enable.
+ * @rmac_pause_time: The value to be inserted in outgoing pause frames.
+ *             Has units of pause quanta (one pause quanta = 512 bit times).
+ * @mc_pause_threshold_q0q3: Contains thresholds for pause frame generation
+ *     for queues 0 through 3. The threshold value indicates portion of the
+ *     individual receive buffer queue size. Thresholds have a range of 0 to
+ *     255, allowing 256 possible watermarks in a queue.
+ * @mc_pause_threshold_q4q7: Contains thresholds for pause frame generation
+ *     for queues 4 through 7. The threshold value indicates portion of the
+ *     individual receive buffer queue size. Thresholds have a range of 0 to
+ *     255, allowing 256 possible watermarks in a queue.
+ *
+ * MAC configuration. This includes various aspects of configuration, including:
+ * - Pause frame threshold;
+ * - sampling rate to calculate link utilization;
+ * - enabling/disabling broadcasts.
+ *
+ * See Xframe User Guide for more details.
+ * Note: Valid (min, max) range for each attribute is specified in the body of
+ * the xge_hal_mac_config_t{} structure. Please refer to the
+ * corresponding include file.
+ */
+typedef struct xge_hal_mac_config_t {
+	int				media;
+#define XGE_HAL_MIN_MEDIA			0
+#define XGE_HAL_MEDIA_SR			0
+#define XGE_HAL_MEDIA_SW			1
+#define XGE_HAL_MEDIA_LR			2
+#define XGE_HAL_MEDIA_LW			3
+#define XGE_HAL_MEDIA_ER			4
+#define XGE_HAL_MEDIA_EW			5
+#define XGE_HAL_MAX_MEDIA			5
+
+	int				tmac_util_period;
+#define XGE_HAL_MIN_TMAC_UTIL_PERIOD		0
+#define XGE_HAL_MAX_TMAC_UTIL_PERIOD		15
+
+	int				rmac_util_period;
+#define XGE_HAL_MIN_RMAC_UTIL_PERIOD		0
+#define XGE_HAL_MAX_RMAC_UTIL_PERIOD		15
+
+	int				rmac_bcast_en;
+#define XGE_HAL_MIN_RMAC_BCAST_EN		0
+#define XGE_HAL_MAX_RMAC_BCAST_EN		1
+
+	int				rmac_pause_gen_en;
+#define XGE_HAL_MIN_RMAC_PAUSE_GEN_EN		0
+#define XGE_HAL_MAX_RMAC_PAUSE_GEN_EN		1
+
+	int				rmac_pause_rcv_en;
+#define XGE_HAL_MIN_RMAC_PAUSE_RCV_EN		0
+#define XGE_HAL_MAX_RMAC_PAUSE_RCV_EN		1
+
+	int				rmac_pause_time;
+#define XGE_HAL_MIN_RMAC_HIGH_PTIME		16
+#define XGE_HAL_MAX_RMAC_HIGH_PTIME		65535
+
+	int				mc_pause_threshold_q0q3;
+#define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q0Q3	0
+#define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q0Q3	254
+
+	int				mc_pause_threshold_q4q7;
+#define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q4Q7	0
+#define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q4Q7	254
+
+} xge_hal_mac_config_t;
+
+#ifdef XGEHAL_RNIC
+
+/*
+ * struct xge_hal_vp_config_t - Configuration of virtual path
+ * @vp_id: Virtual Path Id
+ * @vp_valid: Flag specifies if the configuration is valid
+ * @bitmap_intr_num: Interrupt Number associated with the bitmap
+ * @nce_oid_start: The start of the NCE ID range
+ * @nce_oid_end: The end of the NCE ID range
+ * @session_oid_start: The start of the Session ID range
+ * @session_oid_end: The end of the Session ID range
+ * @srq_oid_start: The start of the HSRQ ID range
+ * @srq_oid_end: The end of the SRQ ID range
+ * @cqrq_oid_start: The start of the CQRQ range
+ * @cqrq_oid_end: The end of the CQRQ range
+ * @umq_length: Length of up message queue
+ * @umq_int_ctrl: Interrupt control for up Message queue
+ * @umq_gen_compl: Generate completion for up message queue
+ * @dmq_length: Length of down message queue
+ * @dmq_int_ctrl: Interrupt control for down Message queue
+ * @dmq_gen_compl: Generate completion for up message queue
+ *
+ * This structure is used by the driver to pass the configuration parameters to
+ * configure Virtual Path.
+ */
+typedef struct xge_hal_vp_config_t{
+	u32				vp_id;
+	u32				vp_valid;
+#define XGE_HAL_VP_CONFIG_INVALID	0
+#define XGE_HAL_VP_CONFIG_VALID		1
+
+	int				bitmap_intr_num;
+#define XGE_HAL_BITMAP_INTR_NUM_MIN	0
+#define XGE_HAL_BITMAP_INTR_NUM_MAX	3
+
+	u32				nce_oid_start;
+	u32				nce_oid_end;
+	u32				session_oid_start;
+	u32				session_oid_end;
+	u32				srq_oid_start;
+	u32				srq_oid_end;
+	u32				cqrq_oid_start;
+	u32				cqrq_oid_end;
+	u32				umq_length;
+	u32				umq_int_ctrl;
+	u32				umq_gen_compl;
+	u32				dmq_length;
+	u32				dmq_int_ctrl;
+	u32				dmq_gen_compl;
+}xge_hal_vp_config_t;
+
+#endif
+
+/**
+ * struct xge_hal_device_config_t - Device configuration.
+ * @mtu: Current mtu size.
+ * @isr_polling_cnt: Maximum number of times to "poll" for Tx and Rx
+ *                   completions. Used in xge_hal_device_handle_irq().
+ * @latency_timer: Specifies, in units of PCI bus clocks, and in conformance
+ *                 with the PCI Specification, the value of the Latency Timer
+ *                 for this PCI bus master.
+ * Specify either zero or -1 to use BIOS default.
+ * @napi_weight: (TODO)
+ * @max_splits_trans: Maximum number of PCI-X split transactions.
+ * Specify (-1) to use BIOS default.
+ * @mmrb_count: Maximum Memory Read Byte Count. Use (-1) to use default
+ *              BIOS value. Otherwise: mmrb_count = 0 corresponds to 512B;
+ *              1 - 1KB, 2 - 2KB, and 3 - 4KB.
+ * @shared_splits: The number of Outstanding Split Transactions that is
+ *              shared by Tx and Rx requests. The device stops issuing Tx
+ *              requests once the number of Outstanding Split Transactions is
+ *              equal to the value of Shared_Splits.
+ *              A value of zero indicates that the Tx and Rx share all allocated
+ *              Split Requests, i.e. the device can issue both types (Tx and Rx)
+ *              of read requests until the number of Maximum Outstanding Split
+ *              Transactions is reached.
+ * @stats_refresh_time_sec: Sets the default interval for automatic stats transfer
+ *              to the host. This includes MAC stats as well as PCI stats.
+ *              See xge_hal_stats_hw_info_t{}.
+ * @pci_freq_mherz: PCI clock frequency, e.g.: 133 for 133MHz.
+ * @intr_mode: Line, MSI, or MSI-X interrupt.
+ * @sched_timer_us: If greater than zero, specifies time interval
+ *              (in microseconds) for the device to generate
+ *              interrupt. Note that unlike tti and rti interrupts,
+ *              the scheduled interrupt is generated independently of
+ *              whether there is transmit or receive traffic, respectively.
+ * @sched_timer_one_shot: 1 - generate scheduled interrupt only once.
+ *              0 - generate scheduled interrupt periodically at the specified
+ *              @sched_timer_us interval.
+ *
+ * @ring: See xge_hal_ring_config_t{}.
+ * @mac: See xge_hal_mac_config_t{}.
+ * @tti: See xge_hal_tti_config_t{}.
+ * @fifo: See xge_hal_fifo_config_t{}.
+ *
+ * @dump_on_serr: Dump adapter state ("about", statistics, registers) on SERR#.
+ * @dump_on_eccerr: Dump adapter state ("about", statistics, registers) on
+ *                  ECC error.
+ * @dump_on_parityerr: Dump adapter state ("about", statistics, registers) on
+ *                     parity error.
+ * @rth_en: Enable Receive Traffic Hashing(RTH) using IT(Indirection Table).
+ * @rth_bucket_size: RTH bucket width (in bits). For valid range please see
+ *                   xge_hal_device_config_t{} in the driver sources.
+ * @rth_spdm_en: Enable Receive Traffic Hashing(RTH) using SPDM(Socket Pair
+ *		Direct Match).
+ * @rth_spdm_use_l4: Set to 1, if the L4 ports are used in the calculation of
+ *	hash value in the RTH SPDM based steering.
+ * @rxufca_intr_thres: (TODO)
+ * @rxufca_lo_lim: (TODO)
+ * @rxufca_hi_lim: (TODO)
+ * @rxufca_lbolt_period: (TODO)
+ * @link_valid_cnt: link-valid counting is done only at device-open time,
+ * to determine with the specified certainty that the link is up. See also
+ * @link_retry_cnt.
+ * @link_retry_cnt: Max number of polls for link-up. Done only at device
+ * open time. Reducing this value as well as the previous @link_valid_cnt,
+ * speeds up device startup, which may be important if the driver
+ * is compiled into OS.
+ * @link_stability_period: Specify the period for which the link must be
+ * stable in order for the adapter to declare "LINK UP".
+ * The enumerated settings (see Xframe-II UG) are:
+ *      0 ........... instantaneous
+ *      1 ........... 500 ´s
+ *      2 ........... 1 ms
+ *      3 ........... 64 ms
+ *      4 ........... 256 ms
+ *      5 ........... 512 ms
+ *      6 ........... 1 s
+ *      7 ........... 2 s
+ * @device_poll_millis: Specify the interval (in mulliseconds) between
+ * successive xge_hal_device_poll() runs.
+ * stable in order for the adapter to declare "LINK UP".
+ * @no_isr_events: TBD
+ * @lro_sg_size: TBD
+ * @lro_frm_len: TBD
+ * @bimodal_interrupts: Enable bimodal interrupts in device
+ * @bimodal_timer_lo_us: TBD
+ * @bimodal_timer_hi_us: TBD
+ * @rts_mac_en: Enable Receive Traffic Steering using MAC destination address
+ * @rts_qos_en: TBD
+ * @rts_port_en: TBD
+ * @vp_config: Configuration for virtual paths
+ * @max_cqe_groups:  The maximum number of adapter CQE group blocks a CQRQ
+ * can own at any one time.
+ * @max_num_wqe_od_groups: The maximum number of WQE Headers/OD Groups that
+ * this S-RQ can own at any one time.
+ * @no_wqe_threshold: Maximum number of times adapter polls WQE Hdr blocks for
+ * WQEs before generating a message or interrupt.
+ * @refill_threshold_high:This field provides a hysteresis upper bound for
+ * automatic adapter refill operations.
+ * @refill_threshold_low:This field provides a hysteresis lower bound for
+ * automatic adapter refill operations.
+ * @eol_policy:This field sets the policy for handling the end of list condition.

+ * 2'b00 - When EOL is reached,poll until last block wrapper size is no longer 0.

+ * 2'b01 - Send UMQ message when EOL is reached.

+ * 2'b1x - Poll until the poll_count_max is reached and if still EOL,send UMQ message
+ * @eol_poll_count_max:sets the maximum number of times the queue manager will poll for
+ * a non-zero block wrapper before giving up and sending a UMQ message
+ * @ack_blk_limit: Limit on the maximum number of ACK list blocks that can be held
+ * by a session at any one time.
+ * @poll_or_doorbell: TBD
+ *
+ * Xframe configuration.
+ * Contains per-device configuration parameters, including:
+ * - latency timer (settable via PCI configuration space);
+ * - maximum number of split transactions;
+ * - maximum number of shared splits;
+ * - stats sampling interval, etc.
+ *
+ * In addition, xge_hal_device_config_t{} includes "subordinate"
+ * configurations, including:
+ * - fifos and rings;
+ * - MAC (see xge_hal_mac_config_t{}).
+ *
+ * See Xframe User Guide for more details.
+ * Note: Valid (min, max) range for each attribute is specified in the body of
+ * the xge_hal_device_config_t{} structure. Please refer to the
+ * corresponding include file.
+ * See also: xge_hal_tti_config_t{}, xge_hal_stats_hw_info_t{},
+ * xge_hal_mac_config_t{}.
+ */
+typedef struct xge_hal_device_config_t {
+	int				mtu;
+#define XGE_HAL_MIN_INITIAL_MTU		XGE_HAL_MIN_MTU
+#define XGE_HAL_MAX_INITIAL_MTU		XGE_HAL_MAX_MTU
+
+	int				isr_polling_cnt;
+#define XGE_HAL_MIN_ISR_POLLING_CNT		0
+#define XGE_HAL_MAX_ISR_POLLING_CNT		65536
+
+	int				latency_timer;
+#define	XGE_HAL_USE_BIOS_DEFAULT_LATENCY	-1
+#define XGE_HAL_MIN_LATENCY_TIMER		8
+#define XGE_HAL_MAX_LATENCY_TIMER		255
+
+	int				napi_weight;
+#define	XGE_HAL_DEF_NAPI_WEIGHT			64
+
+	int				max_splits_trans;
+#define	XGE_HAL_USE_BIOS_DEFAULT_SPLITS		-1
+#define	XGE_HAL_ONE_SPLIT_TRANSACTION		0
+#define	XGE_HAL_TWO_SPLIT_TRANSACTION		1
+#define	XGE_HAL_THREE_SPLIT_TRANSACTION		2
+#define	XGE_HAL_FOUR_SPLIT_TRANSACTION		3
+#define	XGE_HAL_EIGHT_SPLIT_TRANSACTION		4
+#define	XGE_HAL_TWELVE_SPLIT_TRANSACTION	5
+#define	XGE_HAL_SIXTEEN_SPLIT_TRANSACTION	6
+#define	XGE_HAL_THIRTYTWO_SPLIT_TRANSACTION	7
+
+	int				mmrb_count;
+#define XGE_HAL_DEFAULT_BIOS_MMRB_COUNT		-1
+#define XGE_HAL_MIN_MMRB_COUNT			0 /* 512b */
+#define XGE_HAL_MAX_MMRB_COUNT			3 /* 4k */
+
+	int				shared_splits;
+#define XGE_HAL_MIN_SHARED_SPLITS		0
+#define XGE_HAL_MAX_SHARED_SPLITS		31
+
+	int				stats_refresh_time_sec;
+#define XGE_HAL_STATS_REFRESH_DISABLE		0
+#define XGE_HAL_MIN_STATS_REFRESH_TIME		1
+#define XGE_HAL_MAX_STATS_REFRESH_TIME		300
+
+	int				pci_freq_mherz;
+#define XGE_HAL_PCI_FREQ_MHERZ_33		33
+#define XGE_HAL_PCI_FREQ_MHERZ_66		66
+#define XGE_HAL_PCI_FREQ_MHERZ_100		100
+#define XGE_HAL_PCI_FREQ_MHERZ_133		133
+#define XGE_HAL_PCI_FREQ_MHERZ_266		266
+
+	int				intr_mode;
+#define XGE_HAL_INTR_MODE_IRQLINE		0
+#define XGE_HAL_INTR_MODE_MSI			1
+#define XGE_HAL_INTR_MODE_MSIX			2
+
+	int				sched_timer_us;
+#define XGE_HAL_SCHED_TIMER_DISABLED		0
+#define XGE_HAL_SCHED_TIMER_MIN			0
+#define XGE_HAL_SCHED_TIMER_MAX			0xFFFFF
+
+	int				sched_timer_one_shot;
+#define XGE_HAL_SCHED_TIMER_ON_SHOT_DISABLE	0
+#define XGE_HAL_SCHED_TIMER_ON_SHOT_ENABLE	1
+
+	xge_hal_ring_config_t		ring;
+	xge_hal_mac_config_t		mac;
+	xge_hal_fifo_config_t		fifo;
+
+	int				dump_on_serr;
+#define XGE_HAL_DUMP_ON_SERR_DISABLE		0
+#define XGE_HAL_DUMP_ON_SERR_ENABLE		1
+
+	int				dump_on_eccerr;
+#define XGE_HAL_DUMP_ON_ECCERR_DISABLE		0
+#define XGE_HAL_DUMP_ON_ECCERR_ENABLE		1
+
+	int				dump_on_parityerr;
+#define XGE_HAL_DUMP_ON_PARITYERR_DISABLE	0
+#define XGE_HAL_DUMP_ON_PARITYERR_ENABLE	1
+
+	int				rth_en;
+#define XGE_HAL_RTH_DISABLE			0
+#define XGE_HAL_RTH_ENABLE			1
+
+	int				rth_bucket_size;
+#define XGE_HAL_MIN_RTH_BUCKET_SIZE		1
+#define XGE_HAL_MAX_RTH_BUCKET_SIZE		8
+
+	int				rth_spdm_en;
+#define XGE_HAL_RTH_SPDM_DISABLE		0
+#define XGE_HAL_RTH_SPDM_ENABLE			1
+
+	int				rth_spdm_use_l4;
+#define XGE_HAL_RTH_SPDM_USE_L4			1
+
+	int				rxufca_intr_thres;
+#define XGE_HAL_RXUFCA_INTR_THRES_MIN		1
+#define XGE_HAL_RXUFCA_INTR_THRES_MAX		4096
+
+	int				rxufca_lo_lim;
+#define XGE_HAL_RXUFCA_LO_LIM_MIN		1
+#define XGE_HAL_RXUFCA_LO_LIM_MAX		16
+
+	int				rxufca_hi_lim;
+#define XGE_HAL_RXUFCA_HI_LIM_MIN		1
+#define XGE_HAL_RXUFCA_HI_LIM_MAX		256
+
+	int				rxufca_lbolt_period;
+#define XGE_HAL_RXUFCA_LBOLT_PERIOD_MIN		1
+#define XGE_HAL_RXUFCA_LBOLT_PERIOD_MAX		1024
+
+	int				link_valid_cnt;
+#define XGE_HAL_LINK_VALID_CNT_MIN		0
+#define XGE_HAL_LINK_VALID_CNT_MAX		127
+
+	int				link_retry_cnt;
+#define XGE_HAL_LINK_RETRY_CNT_MIN		0
+#define XGE_HAL_LINK_RETRY_CNT_MAX		127
+
+	int				link_stability_period;
+#define XGE_HAL_DEFAULT_LINK_STABILITY_PERIOD	2 /* 1ms */
+#define XGE_HAL_MIN_LINK_STABILITY_PERIOD	0 /* instantaneous */
+#define XGE_HAL_MAX_LINK_STABILITY_PERIOD	7 /* 2s */
+
+	int				device_poll_millis;
+#define XGE_HAL_DEFAULT_DEVICE_POLL_MILLIS	1000
+#define XGE_HAL_MIN_DEVICE_POLL_MILLIS		1
+#define XGE_HAL_MAX_DEVICE_POLL_MILLIS		100000
+
+	int				no_isr_events;
+#define XGE_HAL_NO_ISR_EVENTS_MIN		0
+#define XGE_HAL_NO_ISR_EVENTS_MAX		1
+
+	int				lro_sg_size;
+#define XGE_HAL_LRO_DEFAULT_SG_SIZE		10
+#define XGE_HAL_LRO_MIN_SG_SIZE			1
+#define XGE_HAL_LRO_MAX_SG_SIZE			64
+
+	int				lro_frm_len;
+#define XGE_HAL_LRO_DEFAULT_FRM_LEN		65536
+#define XGE_HAL_LRO_MIN_FRM_LEN			4096
+#define XGE_HAL_LRO_MAX_FRM_LEN			65536
+
+	int				bimodal_interrupts;
+#define XGE_HAL_BIMODAL_INTR_MIN		-1
+#define XGE_HAL_BIMODAL_INTR_MAX		1
+
+	int				bimodal_timer_lo_us;
+#define XGE_HAL_BIMODAL_TIMER_LO_US_MIN		1
+#define XGE_HAL_BIMODAL_TIMER_LO_US_MAX		127
+
+	int				bimodal_timer_hi_us;
+#define XGE_HAL_BIMODAL_TIMER_HI_US_MIN		128
+#define XGE_HAL_BIMODAL_TIMER_HI_US_MAX		65535
+
+	int				rts_mac_en;
+#define XGE_HAL_RTS_MAC_DISABLE			0
+#define XGE_HAL_RTS_MAC_ENABLE			1
+
+	int				rts_qos_en;
+#define XGE_HAL_RTS_QOS_DISABLE			0
+#define XGE_HAL_RTS_QOS_ENABLE			1
+
+	int				rts_port_en;
+#define XGE_HAL_RTS_PORT_DISABLE		0
+#define XGE_HAL_RTS_PORT_ENABLE			1
+
+#ifdef XGEHAL_RNIC
+
+	xge_hal_vp_config_t		vp_config[XGE_HAL_MAX_VIRTUAL_PATHS];
+
+	int				max_cqe_groups;
+#define XGE_HAL_MAX_CQE_GROUPS_MIN		1
+#define XGE_HAL_MAX_CQE_GROUPS_MAX		16
+
+	int				max_num_wqe_od_groups;
+#define XGE_HAL_MAX_NUM_OD_GROUPS_MIN		1
+#define XGE_HAL_MAX_NUM_OD_GROUPS_MAX		16
+
+	int				no_wqe_threshold;
+#define XGE_HAL_NO_WQE_THRESHOLD_MIN		1
+#define XGE_HAL_NO_WQE_THRESHOLD_MAX		16
+
+	int				refill_threshold_high;
+#define XGE_HAL_REFILL_THRESHOLD_HIGH_MIN	1
+#define XGE_HAL_REFILL_THRESHOLD_HIGH_MAX	16
+
+	int				refill_threshold_low;
+#define XGE_HAL_REFILL_THRESHOLD_LOW_MIN	1
+#define XGE_HAL_REFILL_THRESHOLD_LOW_MAX	16
+
+	int				ack_blk_limit;
+#define XGE_HAL_ACK_BLOCK_LIMIT_MIN		1
+#define XGE_HAL_ACK_BLOCK_LIMIT_MAX		16
+
+	int				poll_or_doorbell;
+#define XGE_HAL_POLL_OR_DOORBELL_POLL		1
+#define XGE_HAL_POLL_OR_DOORBELL_DOORBELL	0
+
+
+#endif
+
+} xge_hal_device_config_t;
+
+/**
+ * struct xge_hal_driver_config_t - HAL (layer) configuration.
+ * @periodic_poll_interval_millis: Interval, in milliseconds, which is used to
+ *                                 periodically poll HAL, i.e, invoke
+ *                                 xge_hal_device_poll().
+ *                                 Note that HAL does not maintain its own
+ *                                 polling context. HAL relies on ULD to
+ *                                 provide one.
+ * @queue_size_initial: Initial size of the HAL protected event queue.
+ *                      The queue is shared by HAL and upper-layer drivers.
+ *                      The queue is used to exchange and process slow-path
+ *                      events. See xge_hal_event_e.
+ * @queue_size_max: Maximum size of the HAL queue. Depending on the load,
+ *                  the queue may grow at run-time up to @queue_max_size.
+ * @tracebuf_size: Size of the trace buffer. Set it to '0' to disable.
+ * HAL configuration. (Note: do not confuse HAL layer with (possibly multiple)
+ * HAL devices.)
+ * Currently this structure contains just a few basic values.
+ * Note: Valid (min, max) range for each attribute is specified in the body of
+ * the structure. Please refer to the corresponding header file.
+ * See also: xge_hal_device_poll()
+ */
+typedef struct xge_hal_driver_config_t {
+	int				queue_size_initial;
+#define XGE_HAL_MIN_QUEUE_SIZE_INITIAL		1
+#define XGE_HAL_MAX_QUEUE_SIZE_INITIAL		16
+
+	int				queue_size_max;
+#define XGE_HAL_MIN_QUEUE_SIZE_MAX		1
+#define XGE_HAL_MAX_QUEUE_SIZE_MAX		16
+
+#ifdef XGE_TRACE_INTO_CIRCULAR_ARR
+	int				tracebuf_size;
+#define XGE_HAL_MIN_CIRCULAR_ARR                4096
+#define XGE_HAL_MAX_CIRCULAR_ARR                1048576
+#define XGE_HAL_DEF_CIRCULAR_ARR                XGE_OS_HOST_PAGE_SIZE
+
+	int				tracebuf_timestamp_en;
+#define XGE_HAL_MIN_TIMESTAMP_EN                0
+#define XGE_HAL_MAX_TIMESTAMP_EN                1
+#endif
+
+} xge_hal_driver_config_t;
+
+
+/* ========================== PRIVATE API ================================= */
+
+xge_hal_status_e
+__hal_device_config_check_common (xge_hal_device_config_t *new_config);
+
+xge_hal_status_e
+__hal_device_config_check_xena (xge_hal_device_config_t *new_config);
+
+xge_hal_status_e
+__hal_device_config_check_herc (xge_hal_device_config_t *new_config);
+
+xge_hal_status_e
+__hal_driver_config_check (xge_hal_driver_config_t *new_config);
+
+__EXTERN_END_DECLS
+
+#endif /* XGE_HAL_CONFIG_H */
diff --git a/sys/dev/nxge/include/xgehal-device.h b/sys/dev/nxge/include/xgehal-device.h
new file mode 100644
index 0000000..22bc792
--- /dev/null
+++ b/sys/dev/nxge/include/xgehal-device.h
@@ -0,0 +1,1036 @@
+/*-
+ * Copyright (c) 2002-2007 Neterion, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ *  FileName :    xgehal-device.h
+ *
+ *  Description:  HAL device object functionality
+ *
+ *  Created:      14 May 2004
+ */
+
+#ifndef XGE_HAL_DEVICE_H
+#define XGE_HAL_DEVICE_H
+
+#include <dev/nxge/include/xge-os-pal.h>
+#include <dev/nxge/include/xge-queue.h>
+#include <dev/nxge/include/xgehal-event.h>
+#include <dev/nxge/include/xgehal-config.h>
+#include <dev/nxge/include/xgehal-regs.h>
+#include <dev/nxge/include/xgehal-channel.h>
+#include <dev/nxge/include/xgehal-stats.h>
+#include <dev/nxge/include/xgehal-ring.h>
+#ifdef XGEHAL_RNIC
+#include "xgehal-common-regs.h"
+#include "xgehal-pcicfg-mgmt-regs.h"
+#include "xgehal-mrpcim-regs.h"
+#include "xgehal-srpcim-regs.h"
+#include "xgehal-vpath-regs.h"
+#include "xgehal-bitmap.h"
+#include "xgehal-virtualpath.h"
+#include "xgehal-lbwrapper.h"
+#include "xgehal-blockpool.h"
+#include "xgehal-regpool.h"
+#endif
+
+__EXTERN_BEGIN_DECLS
+
+#define XGE_HAL_VPD_LENGTH                              80
+#define XGE_HAL_CARD_XENA_VPD_ADDR                      0x50
+#define XGE_HAL_CARD_HERC_VPD_ADDR                      0x80
+#define XGE_HAL_VPD_READ_COMPLETE                       0x80
+#define XGE_HAL_VPD_BUFFER_SIZE                         128
+#define XGE_HAL_DEVICE_XMSI_WAIT_MAX_MILLIS		500
+#define XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS		500
+#define XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS	500
+#define XGE_HAL_DEVICE_FAULT_WAIT_MAX_MILLIS		50
+#define XGE_HAL_DEVICE_RESET_WAIT_MAX_MILLIS		250
+#define XGE_HAL_DEVICE_SPDM_READY_WAIT_MAX_MILLIS	250  /* TODO */
+
+#define XGE_HAL_MAGIC					0x12345678
+#define XGE_HAL_DEAD					0xDEADDEAD
+#define XGE_HAL_DUMP_BUF_SIZE                           0x4000
+
+#define XGE_HAL_LRO_MAX_BUCKETS				32
+
+/**
+ * enum xge_hal_card_e - Xframe adapter type.
+ * @XGE_HAL_CARD_UNKNOWN: Unknown device.
+ * @XGE_HAL_CARD_XENA: Xframe I device.
+ * @XGE_HAL_CARD_HERC: Xframe II (PCI-266Mhz) device.
+ * @XGE_HAL_CARD_TITAN: Xframe ER (PCI-266Mhz) device.
+ *
+ * Enumerates Xframe adapter types. The corresponding PCI device
+ * IDs are listed in the file xgehal-defs.h.
+ * (See XGE_PCI_DEVICE_ID_XENA_1, etc.)
+ *
+ * See also: xge_hal_device_check_id().
+ */
+typedef enum xge_hal_card_e {
+	XGE_HAL_CARD_UNKNOWN	= 0,
+	XGE_HAL_CARD_XENA	= 1,
+	XGE_HAL_CARD_HERC	= 2,
+	XGE_HAL_CARD_TITAN	= 3,
+} xge_hal_card_e;
+
+/**
+ * struct xge_hal_device_attr_t - Device memory spaces.
+ * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev
+ *         (Linux and the rest.)
+ * @regh1: BAR1 mapped memory handle. Same comment as above.
+ * @bar0: BAR0 virtual address.
+ * @bar1: BAR1 virtual address.
+ * @irqh: IRQ handle (Solaris).
+ * @cfgh: Configuration space handle (Solaris), or PCI device @pdev (Linux).
+ * @pdev: PCI device object.
+ *
+ * Device memory spaces. Includes configuration, BAR0, BAR1, etc. per device
+ * mapped memories. Also, includes a pointer to OS-specific PCI device object.
+ */
+typedef struct xge_hal_device_attr_t {
+	pci_reg_h		regh0;
+	pci_reg_h		regh1;
+	pci_reg_h		regh2;
+	char			*bar0;
+	char			*bar1;
+	char			*bar2;
+	pci_irq_h		irqh;
+	pci_cfg_h		cfgh;
+	pci_dev_h		pdev;
+} xge_hal_device_attr_t;
+
+/**
+ * enum xge_hal_device_link_state_e - Link state enumeration.
+ * @XGE_HAL_LINK_NONE: Invalid link state.
+ * @XGE_HAL_LINK_DOWN: Link is down.
+ * @XGE_HAL_LINK_UP: Link is up.
+ *
+ */
+typedef enum xge_hal_device_link_state_e {
+	XGE_HAL_LINK_NONE,
+	XGE_HAL_LINK_DOWN,
+	XGE_HAL_LINK_UP
+} xge_hal_device_link_state_e;
+
+
+/**
+ * enum xge_hal_pci_mode_e - PIC bus speed and mode specific enumeration.
+ * @XGE_HAL_PCI_33MHZ_MODE:		33 MHZ pci mode.
+ * @XGE_HAL_PCI_66MHZ_MODE:		66 MHZ pci mode.
+ * @XGE_HAL_PCIX_M1_66MHZ_MODE:		PCIX M1 66MHZ mode.
+ * @XGE_HAL_PCIX_M1_100MHZ_MODE:	PCIX M1 100MHZ mode.
+ * @XGE_HAL_PCIX_M1_133MHZ_MODE:	PCIX M1 133MHZ mode.
+ * @XGE_HAL_PCIX_M2_66MHZ_MODE:		PCIX M2 66MHZ mode.
+ * @XGE_HAL_PCIX_M2_100MHZ_MODE:	PCIX M2 100MHZ mode.
+ * @XGE_HAL_PCIX_M2_133MHZ_MODE:	PCIX M3 133MHZ mode.
+ * @XGE_HAL_PCIX_M1_RESERVED:		PCIX M1 reserved mode.
+ * @XGE_HAL_PCIX_M1_66MHZ_NS:		PCIX M1 66MHZ mode not supported.
+ * @XGE_HAL_PCIX_M1_100MHZ_NS:		PCIX M1 100MHZ mode not supported.
+ * @XGE_HAL_PCIX_M1_133MHZ_NS:		PCIX M1 133MHZ not supported.
+ * @XGE_HAL_PCIX_M2_RESERVED:		PCIX M2 reserved.
+ * @XGE_HAL_PCIX_533_RESERVED:		PCIX 533 reserved.
+ * @XGE_HAL_PCI_BASIC_MODE:		PCI basic mode, XENA specific value.
+ * @XGE_HAL_PCIX_BASIC_MODE:		PCIX basic mode, XENA specific value.
+ * @XGE_HAL_PCI_INVALID_MODE:		Invalid PCI or PCIX mode.
+ *
+ */
+typedef enum xge_hal_pci_mode_e {
+	XGE_HAL_PCI_33MHZ_MODE		= 0x0,
+	XGE_HAL_PCI_66MHZ_MODE		= 0x1,
+	XGE_HAL_PCIX_M1_66MHZ_MODE	= 0x2,
+	XGE_HAL_PCIX_M1_100MHZ_MODE	= 0x3,
+	XGE_HAL_PCIX_M1_133MHZ_MODE	= 0x4,
+	XGE_HAL_PCIX_M2_66MHZ_MODE	= 0x5,
+	XGE_HAL_PCIX_M2_100MHZ_MODE	= 0x6,
+	XGE_HAL_PCIX_M2_133MHZ_MODE	= 0x7,
+	XGE_HAL_PCIX_M1_RESERVED	= 0x8,
+	XGE_HAL_PCIX_M1_66MHZ_NS	= 0xA,
+	XGE_HAL_PCIX_M1_100MHZ_NS	= 0xB,
+	XGE_HAL_PCIX_M1_133MHZ_NS	= 0xC,
+	XGE_HAL_PCIX_M2_RESERVED	= 0xD,
+	XGE_HAL_PCIX_533_RESERVED	= 0xE,
+	XGE_HAL_PCI_BASIC_MODE		= 0x10,
+	XGE_HAL_PCIX_BASIC_MODE		= 0x11,
+	XGE_HAL_PCI_INVALID_MODE	= 0x12,
+} xge_hal_pci_mode_e;
+
+/**
+ * enum xge_hal_pci_bus_frequency_e - PCI bus frequency enumeration.
+ * @XGE_HAL_PCI_BUS_FREQUENCY_33MHZ:	PCI bus frequency 33MHZ
+ * @XGE_HAL_PCI_BUS_FREQUENCY_66MHZ:	PCI bus frequency 66MHZ
+ * @XGE_HAL_PCI_BUS_FREQUENCY_100MHZ:	PCI bus frequency 100MHZ
+ * @XGE_HAL_PCI_BUS_FREQUENCY_133MHZ:	PCI bus frequency 133MHZ
+ * @XGE_HAL_PCI_BUS_FREQUENCY_200MHZ:	PCI bus frequency 200MHZ
+ * @XGE_HAL_PCI_BUS_FREQUENCY_250MHZ:	PCI bus frequency 250MHZ
+ * @XGE_HAL_PCI_BUS_FREQUENCY_266MHZ:	PCI bus frequency 266MHZ
+ * @XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN:	Unrecognized PCI bus frequency value.
+ *
+ */
+typedef enum xge_hal_pci_bus_frequency_e {
+	XGE_HAL_PCI_BUS_FREQUENCY_33MHZ		= 33,
+	XGE_HAL_PCI_BUS_FREQUENCY_66MHZ		= 66,
+	XGE_HAL_PCI_BUS_FREQUENCY_100MHZ	= 100,
+	XGE_HAL_PCI_BUS_FREQUENCY_133MHZ	= 133,
+	XGE_HAL_PCI_BUS_FREQUENCY_200MHZ	= 200,
+	XGE_HAL_PCI_BUS_FREQUENCY_250MHZ	= 250,
+	XGE_HAL_PCI_BUS_FREQUENCY_266MHZ	= 266,
+	XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN	= 0
+} xge_hal_pci_bus_frequency_e;
+
+/**
+ * enum xge_hal_pci_bus_width_e - PCI bus width enumeration.
+ * @XGE_HAL_PCI_BUS_WIDTH_64BIT:	64 bit bus width.
+ * @XGE_HAL_PCI_BUS_WIDTH_32BIT:	32 bit bus width.
+ * @XGE_HAL_PCI_BUS_WIDTH_UNKNOWN:  unknown bus width.
+ *
+ */
+typedef enum xge_hal_pci_bus_width_e {
+	XGE_HAL_PCI_BUS_WIDTH_64BIT	= 0,
+	XGE_HAL_PCI_BUS_WIDTH_32BIT	= 1,
+	XGE_HAL_PCI_BUS_WIDTH_UNKNOWN	= 2,
+} xge_hal_pci_bus_width_e;
+
+#if defined (XGE_HAL_CONFIG_LRO)
+
+#define IP_TOTAL_LENGTH_OFFSET			2
+#define IP_FAST_PATH_HDR_MASK			0x45
+#define TCP_FAST_PATH_HDR_MASK1			0x50
+#define TCP_FAST_PATH_HDR_MASK2			0x10
+#define TCP_FAST_PATH_HDR_MASK3			0x18
+#define IP_SOURCE_ADDRESS_OFFSET		12
+#define IP_DESTINATION_ADDRESS_OFFSET		16
+#define TCP_DESTINATION_PORT_OFFSET		2
+#define TCP_SOURCE_PORT_OFFSET			0
+#define TCP_DATA_OFFSET_OFFSET			12
+#define TCP_WINDOW_OFFSET			14
+#define TCP_SEQUENCE_NUMBER_OFFSET		4
+#define TCP_ACKNOWLEDGEMENT_NUMBER_OFFSET	8
+
+typedef struct tcplro {
+	u16   source;
+	u16   dest;
+	u32   seq;
+	u32   ack_seq;
+	u8    doff_res;
+	u8    ctrl;
+	u16   window;
+	u16   check;
+	u16   urg_ptr;
+} tcplro_t;
+
+typedef struct iplro {
+	u8    version_ihl;
+	u8    tos;
+	u16   tot_len;
+	u16   id;
+	u16   frag_off;
+	u8    ttl;
+	u8    protocol;
+	u16   check;
+	u32   saddr;
+	u32   daddr;
+	/*The options start here. */
+} iplro_t;
+
+/*
+ * LRO object, one per each LRO session.
+*/
+typedef struct lro {
+	/* non-linear: contains scatter-gather list of
+	xframe-mapped received buffers */
+	OS_NETSTACK_BUF		os_buf;
+	OS_NETSTACK_BUF		os_buf_end;
+
+	/* link layer header of the first frame;
+	remains intack throughout the processing */
+	u8			*ll_hdr;
+
+	/* IP header - gets _collapsed_ */
+	iplro_t			*ip_hdr;
+
+	/* transport header - gets _collapsed_ */
+	tcplro_t		*tcp_hdr;
+
+	/* Next tcp sequence number */
+	u32			tcp_next_seq_num;
+	/* Current tcp seq & ack */
+	u32			tcp_seq_num;
+	u32			tcp_ack_num;
+
+	/* total number of accumulated (so far) frames */
+	int			sg_num;
+
+	/* total data length */
+	int			total_length;
+
+	/* receive side hash value, available from Hercules */
+	u32			rth_value;
+
+	/* In use */
+	u8			in_use;
+
+	/* Total length of the fragments clubbed with the inital frame */
+	u32			frags_len;
+
+	/* LRO frame contains time stamp, if (ts_off != -1) */
+	int 			ts_off;
+		
+} lro_t;
+#endif
+
+/*
+ * xge_hal_spdm_entry_t
+ *
+ * Represents a single spdm entry in the SPDM table.
+ */
+typedef struct xge_hal_spdm_entry_t {
+	xge_hal_ipaddr_t  src_ip;
+	xge_hal_ipaddr_t  dst_ip;
+	u32 jhash_value;
+	u16 l4_sp;
+	u16 l4_dp;
+	u16 spdm_entry;
+	u8  in_use;
+	u8  is_tcp;
+	u8  is_ipv4;
+	u8  tgt_queue;
+} xge_hal_spdm_entry_t;
+
+#if defined(XGE_HAL_CONFIG_LRO)
+typedef struct {
+	lro_t			lro_pool[XGE_HAL_LRO_MAX_BUCKETS];
+	int			lro_next_idx;
+	lro_t			*lro_recent;
+} xge_hal_lro_desc_t;
+#endif
+/*
+ * xge_hal_vpd_data_t
+ * 
+ * Represents vpd capabilty structure
+ */
+typedef struct xge_hal_vpd_data_t {
+        u8      product_name[XGE_HAL_VPD_LENGTH];
+        u8      serial_num[XGE_HAL_VPD_LENGTH];
+} xge_hal_vpd_data_t;
+
+/*
+ * xge_hal_device_t
+ *
+ * HAL device object. Represents Xframe.
+ */
+typedef struct {
+	unsigned int		magic;
+	pci_reg_h		regh0;
+	pci_reg_h		regh1;
+	pci_reg_h		regh2;
+	char			*bar0;
+	char			*isrbar0;
+	char			*bar1;
+	char			*bar2;
+	pci_irq_h		irqh;
+	pci_cfg_h		cfgh;
+	pci_dev_h		pdev;
+	xge_hal_pci_config_t	pci_config_space;
+	xge_hal_pci_config_t	pci_config_space_bios;
+	xge_hal_device_config_t	config;
+	xge_list_t		free_channels;
+	xge_list_t		fifo_channels;
+	xge_list_t		ring_channels;
+#ifdef XGEHAL_RNIC
+	__hal_bitmap_entry_t	bitmap_table[XGE_HAL_MAX_BITMAP_BITS];
+	__hal_virtualpath_t	virtual_paths[XGE_HAL_MAX_VIRTUAL_PATHS];
+	__hal_blockpool_t	block_pool;
+	__hal_regpool_t		reg_pool;
+#endif
+	volatile int		is_initialized;
+	volatile int		terminating;
+	xge_hal_stats_t		stats;
+	macaddr_t		macaddr[1];
+	xge_queue_h		queueh;
+	volatile int		mcast_refcnt;
+	int			is_promisc;
+	volatile xge_hal_device_link_state_e	link_state;
+	void			*upper_layer_info;
+	xge_hal_device_attr_t	orig_attr;
+	u16			device_id;
+	u8			revision;
+	int			msi_enabled;
+	int			hw_is_initialized;
+	u64			inject_serr;
+	u64			inject_ecc;
+	u8			inject_bad_tcode;
+	int			inject_bad_tcode_for_chan_type;
+        int                     reset_needed_after_close;
+	int			tti_enabled;
+	xge_hal_tti_config_t	bimodal_tti[XGE_HAL_MAX_RING_NUM];
+	int			bimodal_timer_val_us;
+	int			bimodal_urange_a_en;
+	int			bimodal_intr_cnt;
+	char			*spdm_mem_base;
+	u16			spdm_max_entries;
+	xge_hal_spdm_entry_t	**spdm_table;
+	spinlock_t		spdm_lock;
+	u32			msi_mask;
+#if defined(XGE_HAL_CONFIG_LRO)
+        xge_hal_lro_desc_t      lro_desc[XGE_HAL_MAX_RING_NUM];
+#endif
+	spinlock_t		xena_post_lock;
+
+	/* bimodal workload stats */
+	int			irq_workload_rxd[XGE_HAL_MAX_RING_NUM];
+	int			irq_workload_rxcnt[XGE_HAL_MAX_RING_NUM];
+	int			irq_workload_rxlen[XGE_HAL_MAX_RING_NUM];
+	int			irq_workload_txd[XGE_HAL_MAX_FIFO_NUM];
+	int			irq_workload_txcnt[XGE_HAL_MAX_FIFO_NUM];
+	int			irq_workload_txlen[XGE_HAL_MAX_FIFO_NUM];
+
+	int			mtu_first_time_set;
+	u64			rxufca_lbolt;
+	u64			rxufca_lbolt_time;
+	u64			rxufca_intr_thres;
+	char*                   dump_buf;
+	xge_hal_pci_mode_e	pci_mode;
+	xge_hal_pci_bus_frequency_e bus_frequency;
+	xge_hal_pci_bus_width_e	bus_width;
+	xge_hal_vpd_data_t      vpd_data;
+	volatile int		in_poll;
+	u64			msix_vector_table[XGE_HAL_MAX_MSIX_MESSAGES_WITH_ADDR];
+} xge_hal_device_t;
+
+
+/* ========================== PRIVATE API ================================= */
+
+void
+__hal_device_event_queued(void *data, int event_type);
+
+xge_hal_status_e
+__hal_device_set_swapper(xge_hal_device_t *hldev);
+
+xge_hal_status_e
+__hal_device_rth_it_configure(xge_hal_device_t *hldev);
+
+xge_hal_status_e
+__hal_device_rth_spdm_configure(xge_hal_device_t *hldev);
+
+xge_hal_status_e
+__hal_verify_pcc_idle(xge_hal_device_t *hldev, u64 adp_status);
+
+xge_hal_status_e
+__hal_device_handle_pic(xge_hal_device_t *hldev, u64 reason);
+
+xge_hal_status_e
+__hal_read_spdm_entry_line(xge_hal_device_t *hldev, u8 spdm_line,
+                        u16 spdm_entry, u64 *spdm_line_val);
+
+void __hal_pio_mem_write32_upper(pci_dev_h pdev, pci_reg_h regh, u32 val,
+			void *addr);
+
+void __hal_pio_mem_write32_lower(pci_dev_h pdev, pci_reg_h regh, u32 val,
+			void *addr);
+void __hal_device_get_vpd_data(xge_hal_device_t *hldev);
+
+xge_hal_status_e
+__hal_device_handle_txpic(xge_hal_device_t *hldev, u64 reason);
+
+xge_hal_status_e
+__hal_device_handle_txdma(xge_hal_device_t *hldev, u64 reason);
+
+xge_hal_status_e
+__hal_device_handle_txmac(xge_hal_device_t *hldev, u64 reason);
+
+xge_hal_status_e
+__hal_device_handle_txxgxs(xge_hal_device_t *hldev, u64 reason);
+
+xge_hal_status_e
+__hal_device_handle_rxpic(xge_hal_device_t *hldev, u64 reason);
+
+xge_hal_status_e
+__hal_device_handle_rxdma(xge_hal_device_t *hldev, u64 reason);
+
+xge_hal_status_e
+__hal_device_handle_rxmac(xge_hal_device_t *hldev, u64 reason);
+
+xge_hal_status_e
+__hal_device_handle_rxxgxs(xge_hal_device_t *hldev, u64 reason);
+
+xge_hal_status_e
+__hal_device_handle_mc(xge_hal_device_t *hldev, u64 reason);
+
+xge_hal_status_e
+__hal_device_register_poll(xge_hal_device_t *hldev, u64 *reg, int op, u64 mask,
+			int max_millis);
+xge_hal_status_e
+__hal_device_rts_mac_configure(xge_hal_device_t *hldev);
+
+xge_hal_status_e
+__hal_device_rts_qos_configure(xge_hal_device_t *hldev);
+
+xge_hal_status_e
+__hal_device_rts_port_configure(xge_hal_device_t *hldev);
+
+xge_hal_status_e
+__hal_device_rti_configure(xge_hal_device_t *hldev, int runtime);
+
+void
+__hal_device_msi_intr_endis(xge_hal_device_t *hldev, int flag);
+
+void
+__hal_device_msix_intr_endis(xge_hal_device_t *hldev,
+			      xge_hal_channel_t *channel, int flag);
+
+/* =========================== PUBLIC API ================================= */
+
+unsigned int
+__hal_fix_time_ival_herc(xge_hal_device_t *hldev,
+			 unsigned int time_ival);
+xge_hal_status_e
+xge_hal_rts_rth_itable_set(xge_hal_device_t *hldev, u8 *itable,
+		u32 itable_size);
+
+void
+xge_hal_rts_rth_set(xge_hal_device_t *hldev, u8 def_q, u64 hash_type,
+		u16 bucket_size);
+
+void
+xge_hal_rts_rth_init(xge_hal_device_t *hldev);
+
+void
+xge_hal_rts_rth_clr(xge_hal_device_t *hldev);
+
+void
+xge_hal_rts_rth_start(xge_hal_device_t *hldev);
+
+void
+xge_hal_rts_rth_stop(xge_hal_device_t *hldev);
+
+void
+xge_hal_device_rts_rth_key_set(xge_hal_device_t *hldev, u8 KeySize, u8 *Key);
+
+xge_hal_status_e
+xge_hal_device_rts_mac_enable(xge_hal_device_h devh, int index, macaddr_t macaddr);
+
+xge_hal_status_e
+xge_hal_device_rts_mac_disable(xge_hal_device_h devh, int index);
+
+int xge_hal_reinitialize_hw(xge_hal_device_t * hldev);
+
+/**
+ * xge_hal_device_rti_reconfigure
+ * @hldev: Hal Device
+ */
+static inline xge_hal_status_e
+xge_hal_device_rti_reconfigure(xge_hal_device_t *hldev)
+{
+	return __hal_device_rti_configure(hldev, 1);
+}
+
+/**
+ * xge_hal_device_rts_port_reconfigure
+ * @hldev: Hal Device
+ */
+static inline xge_hal_status_e
+xge_hal_device_rts_port_reconfigure(xge_hal_device_t *hldev)
+{
+	return __hal_device_rts_port_configure(hldev);
+}
+
+/**
+ * xge_hal_device_is_initialized - Returns 0 if device is not
+ * initialized, non-zero otherwise.
+ * @devh: HAL device handle.
+ *
+ * Returns 0 if device is not initialized, non-zero otherwise.
+ */
+static inline int
+xge_hal_device_is_initialized(xge_hal_device_h devh)
+{
+	return ((xge_hal_device_t*)devh)->is_initialized;
+}
+
+
+/**
+ * xge_hal_device_in_poll - non-zero, if xge_hal_device_poll() is executing.
+ * @devh: HAL device handle.
+ *
+ * Returns non-zero if xge_hal_device_poll() is executing, and 0 - otherwise.
+ */
+static inline int
+xge_hal_device_in_poll(xge_hal_device_h devh)
+{
+	return ((xge_hal_device_t*)devh)->in_poll;
+}
+
+
+/**
+ * xge_hal_device_inject_ecc - Inject ECC error.
+ * @devh: HAL device, pointer to xge_hal_device_t structure.
+ * @err_reg: Contains the error register.
+ *
+ * This function is used to inject ECC error into the driver flow.
+ * This facility can be used to test the driver flow in the
+ * case of ECC error is reported by the firmware.
+ *
+ * Returns: void
+ * See also: xge_hal_device_inject_serr(),
+ * xge_hal_device_inject_bad_tcode()
+ */
+static inline void
+xge_hal_device_inject_ecc(xge_hal_device_h devh, u64 err_reg)
+{
+        ((xge_hal_device_t*)devh)->inject_ecc = err_reg;
+}
+
+
+/**
+ * xge_hal_device_inject_serr - Inject SERR error.
+ * @devh: HAL device, pointer to xge_hal_device_t structure.
+ * @err_reg: Contains the error register.
+ *
+ * This function is used to inject SERR error into the driver flow.
+ * This facility can be used to test the driver flow in the
+ * case of SERR error is reported by firmware.
+ *
+ * Returns: void
+ * See also: xge_hal_device_inject_ecc(),
+ * xge_hal_device_inject_bad_tcode()
+ */
+static inline void
+xge_hal_device_inject_serr(xge_hal_device_h devh, u64 err_reg)
+{
+        ((xge_hal_device_t*)devh)->inject_serr = err_reg;
+}
+
+
+/**
+ * xge_hal_device_inject_bad_tcode - Inject  Bad transfer code.
+ * @devh: HAL device, pointer to xge_hal_device_t structure.
+ * @chan_type: Channel type (fifo/ring).
+ * @t_code: Transfer code.
+ *
+ * This function is used to inject bad (Tx/Rx Data)transfer code
+ * into the driver flow.
+ *
+ * This facility can be used to test the driver flow in the
+ * case of bad transfer code reported by firmware for a Tx/Rx data
+ * transfer.
+ *
+ * Returns: void
+ * See also: xge_hal_device_inject_ecc(), xge_hal_device_inject_serr()
+ */
+static inline void
+xge_hal_device_inject_bad_tcode(xge_hal_device_h devh, int chan_type, u8 t_code)
+{
+        ((xge_hal_device_t*)devh)->inject_bad_tcode_for_chan_type = chan_type;
+        ((xge_hal_device_t*)devh)->inject_bad_tcode = t_code;
+}
+
+void xge_hal_device_msi_enable(xge_hal_device_h	devh);
+
+/*
+ * xge_hal_device_msi_mode - Is MSI enabled?
+ * @devh: HAL device handle.
+ *
+ * Returns 0 if MSI is enabled for the specified device,
+ * non-zero otherwise.
+ */
+static inline int
+xge_hal_device_msi_mode(xge_hal_device_h devh)
+{
+	return ((xge_hal_device_t*)devh)->msi_enabled;
+}
+
+/**
+ * xge_hal_device_queue - Get per-device event queue.
+ * @devh: HAL device handle.
+ *
+ * Returns: event queue associated with the specified HAL device.
+ */
+static inline xge_queue_h
+xge_hal_device_queue (xge_hal_device_h devh)
+{
+	return ((xge_hal_device_t*)devh)->queueh;
+}
+
+/**
+ * xge_hal_device_attr - Get original (user-specified) device
+ * attributes.
+ * @devh: HAL device handle.
+ *
+ * Returns: original (user-specified) device attributes.
+ */
+static inline xge_hal_device_attr_t*
+xge_hal_device_attr(xge_hal_device_h devh)
+{
+	return &((xge_hal_device_t*)devh)->orig_attr;
+}
+
+/**
+ * xge_hal_device_private_set - Set ULD context.
+ * @devh: HAL device handle.
+ * @data: pointer to ULD context
+ *
+ * Use HAL device to set upper-layer driver (ULD) context.
+ *
+ * See also: xge_hal_device_from_private(), xge_hal_device_private()
+ */
+static inline void
+xge_hal_device_private_set(xge_hal_device_h devh, void *data)
+{
+	((xge_hal_device_t*)devh)->upper_layer_info = data;
+}
+
+/**
+ * xge_hal_device_private - Get ULD context.
+ * @devh: HAL device handle.
+ *
+ * Use HAL device to get upper-layer driver (ULD) context.
+ *
+ * Returns:  ULD context.
+ *
+ * See also: xge_hal_device_from_private(), xge_hal_device_private_set()
+ */
+static inline void*
+xge_hal_device_private(xge_hal_device_h devh)
+{
+	return ((xge_hal_device_t*)devh)->upper_layer_info;
+}
+
+/**
+ * xge_hal_device_from_private - Get HAL device object from private.
+ * @info_ptr: ULD context.
+ *
+ * Use ULD context to get HAL device.
+ *
+ * Returns:  Device handle.
+ *
+ * See also: xge_hal_device_private(), xge_hal_device_private_set()
+ */
+static inline xge_hal_device_h
+xge_hal_device_from_private(void *info_ptr)
+{
+	return xge_container_of((void ** ) info_ptr, xge_hal_device_t,
+	upper_layer_info);
+}
+
+/**
+ * xge_hal_device_mtu_check - check MTU value for ranges
+ * @hldev: the device
+ * @new_mtu: new MTU value to check
+ *
+ * Will do sanity check for new MTU value.
+ *
+ * Returns: XGE_HAL_OK - success.
+ * XGE_HAL_ERR_INVALID_MTU_SIZE - MTU is invalid.
+ *
+ * See also: xge_hal_device_mtu_set()
+ */
+static inline xge_hal_status_e
+xge_hal_device_mtu_check(xge_hal_device_t *hldev, int new_mtu)
+{
+	if ((new_mtu < XGE_HAL_MIN_MTU) || (new_mtu > XGE_HAL_MAX_MTU)) {
+		return XGE_HAL_ERR_INVALID_MTU_SIZE;
+	}
+
+	return XGE_HAL_OK;
+}
+
+void xge_hal_device_bcast_enable(xge_hal_device_h devh);
+
+void xge_hal_device_bcast_disable(xge_hal_device_h devh);
+
+void xge_hal_device_terminating(xge_hal_device_h devh);
+
+xge_hal_status_e xge_hal_device_initialize(xge_hal_device_t *hldev,
+		xge_hal_device_attr_t *attr, xge_hal_device_config_t *config);
+
+void xge_hal_device_terminate(xge_hal_device_t *hldev);
+
+xge_hal_status_e xge_hal_device_reset(xge_hal_device_t *hldev);
+
+xge_hal_status_e xge_hal_device_macaddr_get(xge_hal_device_t *hldev,
+		int index,  macaddr_t *macaddr);
+
+xge_hal_status_e xge_hal_device_macaddr_set(xge_hal_device_t *hldev,
+		int index,  macaddr_t macaddr);
+
+xge_hal_status_e xge_hal_device_macaddr_clear(xge_hal_device_t *hldev,
+		int index);
+
+int xge_hal_device_macaddr_find(xge_hal_device_t *hldev, macaddr_t wanted);
+
+xge_hal_status_e xge_hal_device_mtu_set(xge_hal_device_t *hldev, int new_mtu);
+
+xge_hal_status_e xge_hal_device_status(xge_hal_device_t *hldev, u64 *hw_status);
+
+void xge_hal_device_intr_enable(xge_hal_device_t *hldev);
+
+void xge_hal_device_intr_disable(xge_hal_device_t *hldev);
+
+xge_hal_status_e xge_hal_device_mcast_enable(xge_hal_device_t *hldev);
+
+xge_hal_status_e xge_hal_device_mcast_disable(xge_hal_device_t *hldev);
+
+void xge_hal_device_promisc_enable(xge_hal_device_t *hldev);
+
+void xge_hal_device_promisc_disable(xge_hal_device_t *hldev);
+
+xge_hal_status_e xge_hal_device_disable(xge_hal_device_t *hldev);
+
+xge_hal_status_e xge_hal_device_enable(xge_hal_device_t *hldev);
+
+xge_hal_status_e xge_hal_device_handle_tcode(xge_hal_channel_h channelh,
+					     xge_hal_dtr_h dtrh,
+					     u8 t_code);
+
+xge_hal_status_e xge_hal_device_link_state(xge_hal_device_h devh,
+			xge_hal_device_link_state_e *ls);
+
+void xge_hal_device_sched_timer(xge_hal_device_h devh, int interval_us,
+			int one_shot);
+
+void xge_hal_device_poll(xge_hal_device_h devh);
+
+xge_hal_card_e xge_hal_device_check_id(xge_hal_device_h devh);
+
+int xge_hal_device_is_slot_freeze(xge_hal_device_h devh);
+
+xge_hal_status_e
+xge_hal_device_pci_info_get(xge_hal_device_h devh, xge_hal_pci_mode_e *pci_mode,
+			xge_hal_pci_bus_frequency_e *bus_frequency,
+			xge_hal_pci_bus_width_e *bus_width);
+
+xge_hal_status_e
+xge_hal_spdm_entry_add(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip,
+			xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp,
+			u8 is_tcp, u8 is_ipv4, u8 tgt_queue);
+
+xge_hal_status_e
+xge_hal_spdm_entry_remove(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip,
+			xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp,
+			u8 is_tcp, u8 is_ipv4);
+
+xge_hal_status_e
+xge_hal_device_rts_section_enable(xge_hal_device_h devh, int index);
+
+int
+xge_hal_device_is_closed (xge_hal_device_h devh);
+
+/* private functions, don't use them in ULD */
+
+void __hal_serial_mem_write64(xge_hal_device_t *hldev, u64 value, u64 *reg);
+
+u64 __hal_serial_mem_read64(xge_hal_device_t *hldev, u64 *reg);
+
+
+/* Some function protoypes for MSI implementation. */
+xge_hal_status_e
+xge_hal_channel_msi_set (xge_hal_channel_h channelh, int msi,
+			 u32 msg_val);
+void
+xge_hal_mask_msi(xge_hal_device_t *hldev);
+
+void
+xge_hal_unmask_msi(xge_hal_channel_h channelh);
+
+xge_hal_status_e
+xge_hal_channel_msix_set(xge_hal_channel_h channelh, int msix_idx);
+
+xge_hal_status_e
+xge_hal_mask_msix(xge_hal_device_h devh, int msi_id);
+
+xge_hal_status_e
+xge_hal_unmask_msix(xge_hal_device_h devh, int msi_id);
+
+#if defined(XGE_HAL_CONFIG_LRO)
+xge_hal_status_e
+xge_hal_lro_init(u32 lro_scale, xge_hal_device_t *hldev);
+#endif
+
+#if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_DEVICE)
+#define __HAL_STATIC_DEVICE
+#define __HAL_INLINE_DEVICE
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE int
+xge_hal_device_rev(xge_hal_device_t *hldev);
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
+xge_hal_device_begin_irq(xge_hal_device_t *hldev, u64 *reason);
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
+xge_hal_device_clear_rx(xge_hal_device_t *hldev);
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
+xge_hal_device_clear_tx(xge_hal_device_t *hldev);
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
+xge_hal_device_continue_irq(xge_hal_device_t *hldev);
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
+xge_hal_device_handle_irq(xge_hal_device_t *hldev);
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
+xge_hal_device_bar0(xge_hal_device_t *hldev);
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
+xge_hal_device_isrbar0(xge_hal_device_t *hldev);
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
+xge_hal_device_bar1(xge_hal_device_t *hldev);
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
+xge_hal_device_bar0_set(xge_hal_device_t *hldev, char *bar0);
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
+xge_hal_device_isrbar0_set(xge_hal_device_t *hldev, char *isrbar0);
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
+xge_hal_device_bar1_set(xge_hal_device_t *hldev, xge_hal_channel_h channelh,
+		char *bar1);
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
+xge_hal_device_mask_tx(xge_hal_device_t *hldev);
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
+xge_hal_device_mask_rx(xge_hal_device_t *hldev);
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
+xge_hal_device_mask_all(xge_hal_device_t *hldev);
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
+xge_hal_device_unmask_tx(xge_hal_device_t *hldev);
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
+xge_hal_device_unmask_rx(xge_hal_device_t *hldev);
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
+xge_hal_device_unmask_all(xge_hal_device_t *hldev);
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
+xge_hal_device_poll_tx_channels(xge_hal_device_t *hldev, int *got_tx);
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
+xge_hal_device_poll_rx_channels(xge_hal_device_t *hldev, int *got_rx);
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
+xge_hal_device_poll_rx_channel(xge_hal_channel_t *channel, int *got_rx);
+
+__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
+xge_hal_device_poll_tx_channel(xge_hal_channel_t *channel, int *got_tx);
+
+#if defined (XGE_HAL_CONFIG_LRO)
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u8
+__hal_header_parse_token_u8(u8 *string,u16 offset);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16
+__hal_header_parse_token_u16(u8 *string,u16 offset);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u32
+__hal_header_parse_token_u32(u8 *string,u16 offset);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
+__hal_header_update_u8(u8 *string, u16 offset, u8 val);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
+__hal_header_update_u16(u8 *string, u16 offset, u16 val);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
+__hal_header_update_u32(u8 *string, u16 offset, u32 val);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16
+__hal_tcp_seg_len(iplro_t *ip, tcplro_t *tcp);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
+__hal_ip_lro_capable(iplro_t *ip, xge_hal_dtr_info_t *ext_info);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
+__hal_tcp_lro_capable(iplro_t *ip, tcplro_t *tcp, lro_t *lro, int *ts_off);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
+__hal_lro_capable(u8 *buffer, iplro_t **ip, tcplro_t **tcp,
+		xge_hal_dtr_info_t *ext_info);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
+__hal_get_lro_session(u8 *eth_hdr, iplro_t *ip, tcplro_t *tcp, lro_t **lro,
+		xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev,
+		xge_hal_lro_desc_t *ring_lro, lro_t **lro_end3);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
+__hal_lro_under_optimal_thresh(iplro_t *ip, tcplro_t *tcp, lro_t *lro,
+		xge_hal_device_t *hldev);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
+__hal_collapse_ip_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro,
+		xge_hal_device_t *hldev);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
+__hal_collapse_tcp_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro,
+		xge_hal_device_t *hldev);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
+__hal_append_lro(iplro_t *ip, tcplro_t **tcp, u32 *seg_len, lro_t *lro,
+		xge_hal_device_t *hldev);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
+xge_hal_lro_process_rx(int ring, u8 *eth_hdr, u8 *ip_hdr, tcplro_t **tcp, 
+                       u32 *seglen, lro_t **p_lro,
+                       xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev,
+                       lro_t **lro_end3);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
+xge_hal_accumulate_large_rx(u8 *buffer, tcplro_t **tcp, u32 *seglen,
+		lro_t **lro, xge_hal_dtr_info_t *ext_info,
+		xge_hal_device_t *hldev, lro_t **lro_end3);
+
+void
+xge_hal_lro_terminate(u32 lro_scale, xge_hal_device_t *hldev);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t	*
+xge_hal_lro_next_session (xge_hal_device_t *hldev, int ring);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t *
+xge_hal_lro_get_next_session(xge_hal_device_t *hldev);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
+__hal_open_lro_session (u8 *buffer, iplro_t *ip, tcplro_t *tcp, lro_t **lro,
+                        xge_hal_device_t *hldev, xge_hal_lro_desc_t *ring_lro,
+                        int slot, u32 tcp_seg_len, int ts_off);
+
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int
+__hal_lro_get_free_slot (xge_hal_lro_desc_t	*ring_lro);
+#endif
+
+#else /* XGE_FASTPATH_EXTERN */
+#define __HAL_STATIC_DEVICE static
+#define __HAL_INLINE_DEVICE inline
+#include <dev/nxge/xgehal/xgehal-device-fp.c>
+#endif /* XGE_FASTPATH_INLINE */
+
+
+__EXTERN_END_DECLS
+
+#endif /* XGE_HAL_DEVICE_H */
diff --git a/sys/dev/nxge/include/xgehal-driver.h b/sys/dev/nxge/include/xgehal-driver.h
new file mode 100644
index 0000000..e669368
--- /dev/null
+++ b/sys/dev/nxge/include/xgehal-driver.h
@@ -0,0 +1,322 @@
+/*-
+ * Copyright (c) 2002-2007 Neterion, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ *  FileName :    xgehal-driver.h
+ *
+ *  Description:  HAL driver object functionality
+ *
+ *  Created:      14 May 2004
+ */
+
+#ifndef XGE_HAL_DRIVER_H
+#define XGE_HAL_DRIVER_H
+
+#include <dev/nxge/include/xge-os-pal.h>
+#include <dev/nxge/include/xge-list.h>
+#include <dev/nxge/include/xge-queue.h>
+#include <dev/nxge/include/xgehal-types.h>
+#include <dev/nxge/include/xgehal-config.h>
+#include <dev/nxge/include/xgehal-event.h>
+
+__EXTERN_BEGIN_DECLS
+
+/* maximum number of events consumed in a syncle poll() cycle */
+#define XGE_HAL_DRIVER_QUEUE_CONSUME_MAX	5
+
+
+/**
+ * function xge_uld_sched_timer_cb_f - Per-device periodic timer
+ * callback.
+ * @devh: HAL device handle.
+ * @userdata: Per-device user data (a.k.a. context) specified via
+ * xge_hal_device_initialize().
+ *
+ * Periodic or one-shot timer callback. If specified (that is, not NULL)
+ * HAL invokes this callback periodically. The call is performed in the
+ * interrupt context, or more exactly, in the context of HAL's ISR
+ * xge_hal_device_continue_irq().
+ *
+ * See also: xge_hal_device_initialize{}
+ */
+typedef void (*xge_uld_sched_timer_cb_f)(xge_hal_device_h devh, void *userdata);
+
+/**
+ * function xge_uld_link_up_f - Link-Up callback provided by upper-layer
+ * driver.
+ * @userdata: Opaque context set by the ULD via
+ * xge_hal_device_private_set()
+ * (typically - at HAL device iinitialization time).
+ *
+ * Link-up notification callback provided by the ULD.
+ * This is one of the per-driver callbacks, see xge_hal_uld_cbs_t{}.
+ *
+ * See also: xge_hal_uld_cbs_t{}, xge_uld_link_down_f{},
+ * xge_hal_driver_initialize(), xge_hal_device_private_set().
+ */
+typedef void (*xge_uld_link_up_f) (void *userdata);
+
+/**
+ * function xge_uld_link_down_f - Link-Down callback provided by
+ * upper-layer driver.
+ * @userdata: Opaque context set by the ULD via
+ * xge_hal_device_private_set()
+ * (typically - at HAL device iinitialization time).
+ *
+ * Link-Down notification callback provided by the upper-layer driver.
+ * This is one of the per-driver callbacks, see xge_hal_uld_cbs_t{}.
+ *
+ * See also: xge_hal_uld_cbs_t{}, xge_uld_link_up_f{},
+ * xge_hal_driver_initialize(), xge_hal_device_private_set().
+ */
+typedef void (*xge_uld_link_down_f) (void *userdata);
+
+/**
+ * function xge_uld_crit_err_f - Critical Error notification callback.
+ * @userdata: Opaque context set by the ULD via
+ * xge_hal_device_private_set()
+ * (typically - at HAL device iinitialization time).
+ * @type: Enumerated hw error, e.g.: double ECC.
+ * @serr_data: Xframe status.
+ * @ext_data: Extended data. The contents depends on the @type.
+ *
+ * Link-Down notification callback provided by the upper-layer driver.
+ * This is one of the per-driver callbacks, see xge_hal_uld_cbs_t{}.
+ *
+ * See also: xge_hal_uld_cbs_t{}, xge_hal_event_e{},
+ * xge_hal_device_private_set(), xge_hal_driver_initialize().
+ */
+typedef void (*xge_uld_crit_err_f) (void *userdata, xge_hal_event_e type,
+		u64 ext_data);
+
+/**
+ * function xge_uld_event_queued_f - Event-enqueued notification
+ * callback.
+ * @devh: HAL device handle.
+ * @event_type: HAL- or ULD-defined event type. Note that HAL
+ *              events are enumerated by xge_hal_event_e{}.
+ *
+ * "Event-was-enqueued" notification callback provided by the upper-layer
+ * driver. The callback is invoked (if defined, i.e., not NULL in the
+ * xge_hal_uld_cbs_t{} structure) each time immediately after an event
+ * is enqueued.
+ *
+ * See also: xge_hal_uld_cbs_t{}, xge_hal_device_private_set(),
+ * xge_hal_driver_initialize().
+ */
+typedef void (*xge_uld_event_queued_f) (xge_hal_device_h devh, int event_type);
+
+/**
+ * function xge_uld_event_f - ULD event callback.
+ * @item: ULD-defined event, item of the xge_queue_t.
+ *
+ * ULD event callback.
+ * Upper-layer driver can use HAL queue to serialize certain slow-path
+ * events. HAL periodically polls the queue as part of the
+ * xge_hal_device_poll() processing. When/if HAL discovers in the queue
+ * an unkown event type it simply invokes the event callback
+ * (which must be non-NULL and supplied by the ULD in this case).
+ *
+ * See also: xge_hal_uld_cbs_t{}, xge_hal_device_poll(), xge_queue_t{},
+ * xge_hal_driver_initialize(), xge_queue_item_t{}.
+ */
+typedef void (*xge_uld_event_f) (xge_queue_item_t *item);
+
+/**
+ * function xge_uld_before_device_poll_f - ULD "before-poll" callback.
+ * @devh: HAL device handle.
+ *
+ * HAL invokes the callback from inside its xge_hal_device_poll()
+ * implementation %prior to accessing the @devh device. This allows ULD to
+ * perform per-device locking and/or context mapping, if required..
+ * The interface is currently used by AIX driver only.
+ * To avoid using/implementing the callback set the corresponding field
+ * in the xge_hal_uld_cbs_t{} structure to NULL.
+ *
+ * Returns: 0 on success, non-zero on failure.
+ *
+ * See also: xge_hal_driver_initialize(), xge_hal_uld_cbs_t{},
+ * xge_hal_device_poll().
+ */
+typedef int (*xge_uld_before_device_poll_f) (xge_hal_device_h devh);
+
+/**
+ * function xge_uld_after_device_poll_f - ULD "after-poll" callback.
+ * @devh: HAL device handle.
+ *
+ * Unless NULL is specified,
+ * HAL invokes the callback from inside its xge_hal_device_poll()
+ * implementation immediately %after it has completed polling the @devh
+ * device. This allows ULD to undo the affects of
+ * xge_uld_before_device_poll_f{}.
+ * The interface is currently used by AIX driver only.
+ *
+ * See also: xge_hal_driver_initialize(), xge_hal_uld_cbs_t{},
+ * xge_hal_device_poll().
+ */
+typedef void (*xge_uld_after_device_poll_f) (xge_hal_device_h devh);
+
+/**
+ * function xge_uld_xpak_alarm_log_f - ULD "XPAK alarm log" callback.
+ * @devh: HAL device handle.
+ * @type: TODO
+ *
+ * Unless NULL is specified,
+ * HAL invokes the callback from inside __hal_chk_xpak_counter()
+ */
+typedef void (*xge_uld_xpak_alarm_log_f) (xge_hal_device_h devh, xge_hal_xpak_alarm_type_e type);
+
+/**
+ * struct xge_hal_uld_cbs_t - Upper-layer driver "slow-path" callbacks.
+ * @link_up: See xge_uld_link_up_f{}.
+ * @link_down: See xge_uld_link_down_f{}.
+ * @crit_err: See xge_uld_crit_err_f{}.
+ * @event: See xge_uld_event_f{}.
+ * @event_queued: See xge_uld_event_queued_f{}.
+ * @before_device_poll: See xge_uld_before_device_poll_f{}.
+ * @after_device_poll: See xge_uld_after_device_poll_f{}.
+ * @sched_timer: See xge_uld_sched_timer_cb_f{}.
+ * @xpak_alarm_log: TODO
+ *
+ * Upper layer driver slow-path (per-driver) callbacks.
+ * Implemented by ULD and provided to HAL via
+ * xge_hal_driver_initialize().
+ * Note that these callbacks are not mandatory: HAL will not invoke
+ * a callback if NULL is specified.
+ *
+ * Note that in addition to those, there are curently 2 per-channel callbacks
+ * (completion and abort) specified at channel open time
+ * via xge_hal_channel_open().
+ *
+ * See also: xge_hal_driver_initialize().
+ */
+typedef struct xge_hal_uld_cbs_t {
+	xge_uld_link_up_f		link_up;
+	xge_uld_link_down_f		link_down;
+	xge_uld_crit_err_f		crit_err;
+	xge_uld_event_f			event;
+	xge_uld_event_queued_f		event_queued;
+	xge_uld_before_device_poll_f    before_device_poll;
+	xge_uld_after_device_poll_f	after_device_poll;
+	xge_uld_sched_timer_cb_f	sched_timer;
+	xge_uld_xpak_alarm_log_f	xpak_alarm_log;
+} xge_hal_uld_cbs_t;
+
+/**
+ * struct xge_hal_driver_t - Represents HAL object.
+ * @config: HAL configuration.
+ * @devices: List of all PCI-enumerated Xframe devices in the system.
+ * A single xge_hal_driver_t instance contains zero or more
+ * Xframe devices.
+ * @devices_lock: Lock to protect %devices when inserting/removing.
+ * @is_initialized: True if HAL is initialized; false otherwise.
+ * @uld_callbacks: Upper-layer driver callbacks. See xge_hal_uld_cbs_t{}.
+ * @debug_module_mask: 32bit mask that defines which components of the
+ * driver are to be traced. The trace-able components are:
+ *	XGE_COMPONENT_HAL_CONFIG		0x1
+ *	XGE_COMPONENT_HAL_FIFO			0x2
+ *	XGE_COMPONENT_HAL_RING			0x4
+ *	XGE_COMPONENT_HAL_CHANNEL		0x8
+ *	XGE_COMPONENT_HAL_DEVICE		0x10
+ *	XGE_COMPONENT_HAL_MM			0x20
+ *	XGE_COMPONENT_HAL_QUEUE			0x40
+ *	XGE_COMPONENT_HAL_STATS			0x100
+ *	XGE_COMPONENT_OSDEP			0x1000
+ *	XGE_COMPONENT_LL			0x2000
+ *	XGE_COMPONENT_TOE			0x4000
+ *	XGE_COMPONENT_RDMA			0x8000
+ *	XGE_COMPONENT_ALL			0xffffffff
+ * The @debug_module_mask allows to switch off and on tracing at runtime.
+ * In addition, the traces for the same trace-able components can be
+ * compiled out, based on the same mask provided via Makefile.
+ * @debug_level: See xge_debug_level_e{}.
+ *
+ * HAL (driver) object. There is a single instance of this structure per HAL.
+ */
+typedef struct xge_hal_driver_t {
+	xge_hal_driver_config_t		config;
+	int                             is_initialized;
+	xge_hal_uld_cbs_t               uld_callbacks;
+	u32				debug_module_mask;
+	int				debug_level;
+} xge_hal_driver_t;
+
+extern xge_hal_driver_t *g_xge_hal_driver;
+
+static inline int
+xge_hal_driver_is_initialized(void) {
+        return g_xge_hal_driver->is_initialized;
+}
+
+static inline int
+xge_hal_driver_debug_module_mask(void)
+{
+	return g_xge_hal_driver->debug_module_mask;
+}
+
+static inline void
+xge_hal_driver_debug_module_mask_set(u32 new_mask)
+{
+#if (defined(XGE_DEBUG_TRACE_MASK) && XGE_DEBUG_TRACE_MASK > 0) || \
+    (defined(XGE_DEBUG_ERR_MASK) && XGE_DEBUG_ERR_MASK > 0)
+	g_xge_hal_driver->debug_module_mask = new_mask;
+	g_module_mask = (unsigned long *)&g_xge_hal_driver->debug_module_mask;
+#endif
+}
+
+static inline int
+xge_hal_driver_debug_level(void) { return g_xge_hal_driver->debug_level; }
+
+static inline void
+xge_hal_driver_debug_level_set(int new_level)
+{
+#if (defined(XGE_DEBUG_TRACE_MASK) && XGE_DEBUG_TRACE_MASK > 0) || \
+    (defined(XGE_DEBUG_ERR_MASK) && XGE_DEBUG_ERR_MASK > 0)
+	g_xge_hal_driver->debug_level = new_level;
+	g_level = &g_xge_hal_driver->debug_level;
+#endif
+}
+
+xge_hal_status_e xge_hal_driver_initialize(xge_hal_driver_config_t *config,
+		xge_hal_uld_cbs_t *uld_callbacks);
+
+void xge_hal_driver_terminate(void);
+
+#ifdef XGE_TRACE_INTO_CIRCULAR_ARR
+void xge_hal_driver_tracebuf_dump(void);
+
+xge_hal_status_e
+xge_hal_driver_tracebuf_read(int bufsize, char *retbuf, int *retsize);
+#else
+#define xge_hal_driver_tracebuf_dump()
+#define xge_hal_driver_tracebuf_read(a, b, c) (0);
+#endif
+
+__EXTERN_END_DECLS
+
+#endif /* XGE_HAL_DRIVER_H */
diff --git a/sys/dev/nxge/include/xgehal-event.h b/sys/dev/nxge/include/xgehal-event.h
new file mode 100644
index 0000000..7d560d2
--- /dev/null
+++ b/sys/dev/nxge/include/xgehal-event.h
@@ -0,0 +1,85 @@
+/*-
+ * Copyright (c) 2002-2007 Neterion, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ *  FileName :    xgehal-event.h
+ *
+ *  Description:  event types
+ *
+ *  Created:      7 June 2004
+ */
+
+#ifndef XGE_HAL_EVENT_H
+#define XGE_HAL_EVENT_H
+
+#include <dev/nxge/include/xge-os-pal.h>
+
+__EXTERN_BEGIN_DECLS
+
+#define XGE_HAL_EVENT_BASE		0
+#define XGE_LL_EVENT_BASE		100
+
+/**
+ * enum xge_hal_event_e - Enumerates slow-path HAL events.
+ * @XGE_HAL_EVENT_UNKNOWN: Unknown (and invalid) event.
+ * @XGE_HAL_EVENT_SERR: Serious hardware error event.
+ * @XGE_HAL_EVENT_LINK_IS_UP: The link state has changed from 'down' to
+ * 'up'; upper-layer driver (typically, link layer) is
+ * supposed to wake the queue, etc.
+ * @XGE_HAL_EVENT_LINK_IS_DOWN: Link-down event.
+ *                    The link state has changed from 'down' to 'up';
+ *                    upper-layer driver is supposed to stop traffic, etc.
+ * @XGE_HAL_EVENT_ECCERR: ECC error event.
+ * @XGE_HAL_EVENT_PARITYERR: Parity error event.
+ * @XGE_HAL_EVENT_TARGETABORT: Target abort event. Used when device
+ * aborts transmit operation with the corresponding transfer code
+ * (for T_CODE enum see xgehal-fifo.h and xgehal-ring.h)
+ * @XGE_HAL_EVENT_SLOT_FREEZE: Slot-freeze event. Driver tries to distinguish
+ * slot-freeze from the rest critical events (e.g. ECC) when it is
+ * impossible to PIO read "through" the bus, i.e. when getting all-foxes.
+ *
+ * xge_hal_event_e enumerates slow-path HAL eventis.
+ *
+ * See also: xge_hal_uld_cbs_t{}, xge_uld_link_up_f{},
+ * xge_uld_link_down_f{}.
+ */
+typedef enum xge_hal_event_e {
+	XGE_HAL_EVENT_UNKNOWN		= 0,
+	/* HAL events */
+	XGE_HAL_EVENT_SERR		= XGE_HAL_EVENT_BASE + 1,
+	XGE_HAL_EVENT_LINK_IS_UP	= XGE_HAL_EVENT_BASE + 2,
+	XGE_HAL_EVENT_LINK_IS_DOWN	= XGE_HAL_EVENT_BASE + 3,
+	XGE_HAL_EVENT_ECCERR		= XGE_HAL_EVENT_BASE + 4,
+	XGE_HAL_EVENT_PARITYERR		= XGE_HAL_EVENT_BASE + 5,
+	XGE_HAL_EVENT_TARGETABORT       = XGE_HAL_EVENT_BASE + 6,
+	XGE_HAL_EVENT_SLOT_FREEZE       = XGE_HAL_EVENT_BASE + 7,
+} xge_hal_event_e;
+
+__EXTERN_END_DECLS
+
+#endif /* XGE_HAL_EVENT_H */
diff --git a/sys/dev/nxge/include/xgehal-fifo.h b/sys/dev/nxge/include/xgehal-fifo.h
new file mode 100644
index 0000000..6de6048
--- /dev/null
+++ b/sys/dev/nxge/include/xgehal-fifo.h
@@ -0,0 +1,363 @@
+/*-
+ * Copyright (c) 2002-2007 Neterion, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ *  FileName :    xgehal-fifo.h
+ *
+ *  Description:  Tx fifo object functionality
+ *
+ *  Created:      19 May 2004
+ */
+
+#ifndef XGE_HAL_FIFO_H
+#define XGE_HAL_FIFO_H
+
+#include <dev/nxge/include/xgehal-channel.h>
+#include <dev/nxge/include/xgehal-config.h>
+#include <dev/nxge/include/xgehal-mm.h>
+
+__EXTERN_BEGIN_DECLS
+
+/* HW fifo configuration */
+#define	XGE_HAL_FIFO_INT_PER_LIST_THRESHOLD	65
+#define XGE_HAL_FIFO_MAX_WRR			5
+#define XGE_HAL_FIFO_MAX_PARTITION		4
+#define XGE_HAL_FIFO_MAX_WRR_STATE		36
+#define XGE_HAL_FIFO_HW_PAIR_OFFSET		0x20000
+
+/* HW FIFO Weight Calender */
+#define XGE_HAL_FIFO_WRR_0      0x0706050407030602ULL
+#define XGE_HAL_FIFO_WRR_1      0x0507040601070503ULL
+#define XGE_HAL_FIFO_WRR_2      0x0604070205060700ULL
+#define XGE_HAL_FIFO_WRR_3      0x0403060705010207ULL
+#define XGE_HAL_FIFO_WRR_4      0x0604050300000000ULL
+/*
+ * xge_hal_fifo_hw_pair_t
+ *
+ * Represent a single fifo in the BAR1 memory space.
+ */
+typedef struct {
+	u64 txdl_pointer; /* offset 0x0 */
+
+	u64 reserved[2];
+
+	u64 list_control; /* offset 0x18 */
+#define XGE_HAL_TX_FIFO_LAST_TXD_NUM( val)     vBIT(val,0,8)
+#define XGE_HAL_TX_FIFO_FIRST_LIST             BIT(14)
+#define XGE_HAL_TX_FIFO_LAST_LIST              BIT(15)
+#define XGE_HAL_TX_FIFO_FIRSTNLAST_LIST        vBIT(3,14,2)
+#define XGE_HAL_TX_FIFO_SPECIAL_FUNC           BIT(23)
+#define XGE_HAL_TX_FIFO_NO_SNOOP(n)            vBIT(n,30,2)
+} xge_hal_fifo_hw_pair_t;
+
+
+/* Bad TxDL transfer codes */
+#define XGE_HAL_TXD_T_CODE_OK		        0x0
+#define XGE_HAL_TXD_T_CODE_UNUSED_1		0x1
+#define XGE_HAL_TXD_T_CODE_ABORT_BUFFER		0x2
+#define XGE_HAL_TXD_T_CODE_ABORT_DTOR		0x3
+#define XGE_HAL_TXD_T_CODE_UNUSED_5		0x5
+#define XGE_HAL_TXD_T_CODE_PARITY		0x7
+#define XGE_HAL_TXD_T_CODE_LOSS_OF_LINK		0xA
+#define XGE_HAL_TXD_T_CODE_GENERAL_ERR		0xF
+
+
+/**
+ * struct xge_hal_fifo_txd_t - TxD.
+ * @control_1: Control_1.
+ * @control_2: Control_2.
+ * @buffer_pointer: Buffer_Address.
+ * @host_control: Host_Control.Opaque 64bit data stored by ULD inside the Xframe
+ *            descriptor prior to posting the latter on the channel
+ *            via xge_hal_fifo_dtr_post() or xge_hal_ring_dtr_post().
+ *            The %host_control is returned as is to the ULD with each
+ *            completed descriptor.
+ *
+ * Transmit descriptor (TxD).Fifo descriptor contains configured number
+ * (list) of TxDs. * For more details please refer to Xframe User Guide,
+ * Section 5.4.2 "Transmit Descriptor (TxD) Format".
+ */
+typedef struct xge_hal_fifo_txd_t {
+	u64 control_1;
+#define XGE_HAL_TXD_LIST_OWN_XENA       BIT(7)
+#define XGE_HAL_TXD_T_CODE		(BIT(12)|BIT(13)|BIT(14)|BIT(15))
+#define XGE_HAL_GET_TXD_T_CODE(val)     ((val & XGE_HAL_TXD_T_CODE)>>48)
+#define XGE_HAL_SET_TXD_T_CODE(x, val)  (x |= (((u64)val & 0xF) << 48))
+#define XGE_HAL_TXD_GATHER_CODE         (BIT(22) | BIT(23))
+#define XGE_HAL_TXD_GATHER_CODE_FIRST   BIT(22)
+#define XGE_HAL_TXD_GATHER_CODE_LAST    BIT(23)
+#define XGE_HAL_TXD_NO_LSO				0
+#define XGE_HAL_TXD_UDF_COF				1
+#define XGE_HAL_TXD_TCP_LSO				2
+#define XGE_HAL_TXD_UDP_LSO				3
+#define XGE_HAL_TXD_LSO_COF_CTRL(val)   vBIT(val,30,2)
+#define XGE_HAL_TXD_TCP_LSO_MSS(val)    vBIT(val,34,14)
+#define XGE_HAL_TXD_BUFFER0_SIZE(val)   vBIT(val,48,16)
+#define XGE_HAL_TXD_GET_LSO_BYTES_SENT(val) ((val & vBIT(0xFFFF,16,16))>>32)
+	u64 control_2;
+#define XGE_HAL_TXD_TX_CKO_CONTROL      (BIT(5)|BIT(6)|BIT(7))
+#define XGE_HAL_TXD_TX_CKO_IPV4_EN      BIT(5)
+#define XGE_HAL_TXD_TX_CKO_TCP_EN       BIT(6)
+#define XGE_HAL_TXD_TX_CKO_UDP_EN       BIT(7)
+#define XGE_HAL_TXD_VLAN_ENABLE         BIT(15)
+#define XGE_HAL_TXD_VLAN_TAG(val)       vBIT(val,16,16)
+#define XGE_HAL_TXD_INT_NUMBER(val)     vBIT(val,34,6)
+#define XGE_HAL_TXD_INT_TYPE_PER_LIST   BIT(47)
+#define XGE_HAL_TXD_INT_TYPE_UTILZ      BIT(46)
+#define XGE_HAL_TXD_SET_MARKER          vBIT(0x6,0,4)
+
+	u64 buffer_pointer;
+
+	u64 host_control;
+
+} xge_hal_fifo_txd_t;
+
+typedef xge_hal_fifo_txd_t* xge_hal_fifo_txdl_t;
+
+/**
+ * struct xge_hal_fifo_t - Fifo channel.
+ * @channel: Channel "base" of this fifo, the common part of all HAL
+ *           channels.
+ * @post_lock_ptr: Points to a lock that serializes (pointer, control) PIOs.
+ *           Note that for Xena the serialization is done across all device
+ *           fifos.
+ * @hw_pair: Per-fifo (Pointer, Control) pair used to send descriptors to the
+ *           Xframe hardware (for details see Xframe user guide).
+ * @config: Fifo configuration, part of device configuration
+ *          (see xge_hal_device_config_t{}).
+ * @no_snoop_bits: See xge_hal_fifo_config_t{}.
+ * @txdl_per_memblock: Number of TxDLs (TxD lists) per memblock.
+ * on TxDL please refer to Xframe UG.
+ * @interrupt_type: FIXME: to-be-defined.
+ * @txdl_size: Configured TxDL size (i.e., number of TxDs in a list), plus
+ *             per-TxDL HAL private space (xge_hal_fifo_txdl_priv_t).
+ * @priv_size: Per-Tx descriptor space reserved for upper-layer driver
+ *             usage.
+ * @mempool: Memory pool, from which descriptors get allocated.
+ * @align_size: TBD
+ *
+ * Fifo channel.
+ * Note: The structure is cache line aligned.
+ */
+typedef struct xge_hal_fifo_t {
+	xge_hal_channel_t	channel;
+	spinlock_t		*post_lock_ptr;
+	xge_hal_fifo_hw_pair_t	*hw_pair;
+	xge_hal_fifo_config_t	*config;
+	int			no_snoop_bits;
+	int			txdl_per_memblock;
+	u64			interrupt_type;
+	int			txdl_size;
+	int			priv_size;
+	xge_hal_mempool_t	*mempool;
+	int			align_size;
+} __xge_os_attr_cacheline_aligned xge_hal_fifo_t;
+
+/**
+ * struct xge_hal_fifo_txdl_priv_t - Transmit descriptor HAL-private
+ * data.
+ * @dma_addr: DMA (mapped) address of _this_ descriptor.
+ * @dma_handle: DMA handle used to map the descriptor onto device.
+ * @dma_offset: Descriptor's offset in the memory block. HAL allocates
+ * descriptors in memory blocks (see
+ * xge_hal_fifo_config_t{})
+ * Each memblock is a contiguous block of DMA-able memory.
+ * @frags: Total number of fragments (that is, contiguous data buffers)
+ * carried by this TxDL.
+ * @align_vaddr_start: (TODO).
+ * @align_vaddr: Virtual address of the per-TxDL area in memory used for
+ * alignement. Used to place one or more mis-aligned fragments
+ * (the maximum defined by configration variable
+ * @max_aligned_frags).
+ * @align_dma_addr: DMA address translated from the @align_vaddr.
+ * @align_dma_handle: DMA handle that corresponds to @align_dma_addr.
+ * @align_dma_acch: DMA access handle corresponds to @align_dma_addr.
+ * @align_dma_offset: The current offset into the @align_vaddr area.
+ * Grows while filling the descriptor, gets reset.
+ * @align_used_frags: (TODO).
+ * @alloc_frags: Total number of fragments allocated.
+ * @dang_frags: Number of fragments kept from release until this TxDL is freed.
+ * @bytes_sent: TODO
+ * @unused: TODO
+ * @dang_txdl: (TODO).
+ * @next_txdl_priv: (TODO).
+ * @first_txdp: (TODO).
+ * @dang_dtrh: Pointer to TxDL (list) kept from release until this TxDL
+ * is freed.
+ * @linked_txdl_priv: Pointer to any linked TxDL for creating contiguous
+ * TxDL list.
+ * @dtrh: Corresponding dtrh to this TxDL.
+ * @memblock: Pointer to the TxDL memory block or memory page.
+ * on the next send operation.
+ * @dma_object: DMA address and handle of the memory block that contains
+ * the descriptor. This member is used only in the "checked"
+ * version of the HAL (to enforce certain assertions);
+ * otherwise it gets compiled out.
+ * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage.
+ *
+ * Per-transmit decsriptor HAL-private data. HAL uses the space to keep DMA
+ * information associated with the descriptor. Note that ULD can ask HAL
+ * to allocate additional per-descriptor space for its own (ULD-specific)
+ * purposes.
+ *
+ * See also: xge_hal_ring_rxd_priv_t{}.
+ */
+typedef struct xge_hal_fifo_txdl_priv_t {
+	dma_addr_t				dma_addr;
+	pci_dma_h				dma_handle;
+	ptrdiff_t				dma_offset;
+	int					frags;
+	char					*align_vaddr_start;
+	char					*align_vaddr;
+	dma_addr_t				align_dma_addr;
+	pci_dma_h				align_dma_handle;
+	pci_dma_acc_h				align_dma_acch;
+	ptrdiff_t				align_dma_offset;
+	int					align_used_frags;
+	int					alloc_frags;
+	int					dang_frags;
+	unsigned int				bytes_sent;
+	int					unused;
+	xge_hal_fifo_txd_t			*dang_txdl;
+	struct xge_hal_fifo_txdl_priv_t		*next_txdl_priv;
+	xge_hal_fifo_txd_t			*first_txdp;
+	void					*memblock;
+#ifdef XGE_DEBUG_ASSERT
+	xge_hal_mempool_dma_t			*dma_object;
+#endif
+#ifdef XGE_OS_MEMORY_CHECK
+	int					allocated;
+#endif
+} xge_hal_fifo_txdl_priv_t;
+
+/**
+ * xge_hal_fifo_get_max_frags_cnt - Return the max fragments allocated
+ * for the fifo.
+ * @channelh: Channel handle.
+ */
+static inline int
+xge_hal_fifo_get_max_frags_cnt(xge_hal_channel_h channelh)
+{
+	return ((xge_hal_fifo_t *)channelh)->config->max_frags;
+}
+/* ========================= FIFO PRIVATE API ============================= */
+
+xge_hal_status_e __hal_fifo_open(xge_hal_channel_h channelh,
+			xge_hal_channel_attr_t *attr);
+
+void __hal_fifo_close(xge_hal_channel_h channelh);
+
+void __hal_fifo_hw_initialize(xge_hal_device_h hldev);
+
+xge_hal_status_e
+__hal_fifo_dtr_align_alloc_map(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
+
+void
+__hal_fifo_dtr_align_free_unmap(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
+
+#if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_FIFO)
+#define __HAL_STATIC_FIFO
+#define __HAL_INLINE_FIFO
+
+__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_fifo_txdl_priv_t*
+__hal_fifo_txdl_priv(xge_hal_dtr_h dtrh);
+
+__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
+__hal_fifo_dtr_post_single(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
+			u64 ctrl_1);
+__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
+__hal_fifo_txdl_restore_many(xge_hal_channel_h channelh,
+			  xge_hal_fifo_txd_t *txdp, int txdl_count);
+
+/* ========================= FIFO PUBLIC API ============================== */
+
+__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
+xge_hal_fifo_dtr_reserve(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh);
+
+__HAL_STATIC_FIFO __HAL_INLINE_FIFO void*
+xge_hal_fifo_dtr_private(xge_hal_dtr_h dtrh);
+
+__HAL_STATIC_FIFO __HAL_INLINE_FIFO int
+xge_hal_fifo_dtr_buffer_cnt(xge_hal_dtr_h dtrh);
+
+__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
+xge_hal_fifo_dtr_reserve_sp(xge_hal_channel_h channel, int dtr_sp_size,
+			xge_hal_dtr_h dtr_sp);
+
+__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
+xge_hal_fifo_dtr_post(xge_hal_channel_h	channelh, xge_hal_dtr_h dtrh);
+
+__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
+xge_hal_fifo_dtr_post_many(xge_hal_channel_h channelh, int num,
+			xge_hal_dtr_h dtrs[]);
+
+__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
+xge_hal_fifo_dtr_next_completed(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh,
+			u8 *t_code);
+
+__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
+xge_hal_fifo_dtr_free(xge_hal_channel_h	channelh, xge_hal_dtr_h dtr);
+
+__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
+xge_hal_fifo_dtr_buffer_set(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
+			int frag_idx, dma_addr_t dma_pointer, int size);
+
+__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
+xge_hal_fifo_dtr_buffer_set_aligned(xge_hal_channel_h channelh,
+			xge_hal_dtr_h dtrh, int frag_idx, void *vaddr,
+			dma_addr_t dma_pointer, int size, int misaligned_size);
+
+__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
+xge_hal_fifo_dtr_buffer_append(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
+		void *vaddr, int size);
+
+__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
+xge_hal_fifo_dtr_buffer_finalize(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
+		int frag_idx);
+
+__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
+xge_hal_fifo_dtr_mss_set(xge_hal_dtr_h dtrh, int mss);
+
+__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
+xge_hal_fifo_dtr_cksum_set_bits(xge_hal_dtr_h dtrh, u64 cksum_bits);
+
+__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
+xge_hal_fifo_dtr_vlan_set(xge_hal_dtr_h	dtrh, u16 vlan_tag);
+
+__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
+xge_hal_fifo_is_next_dtr_completed(xge_hal_channel_h channelh);
+
+#else /* XGE_FASTPATH_EXTERN */
+#define __HAL_STATIC_FIFO static
+#define __HAL_INLINE_FIFO inline
+#include <dev/nxge/xgehal/xgehal-fifo-fp.c>
+#endif /* XGE_FASTPATH_INLINE */
+
+__EXTERN_END_DECLS
+
+#endif /* XGE_HAL_FIFO_H */
diff --git a/sys/dev/nxge/include/xgehal-mgmt.h b/sys/dev/nxge/include/xgehal-mgmt.h
new file mode 100644
index 0000000..061320e
--- /dev/null
+++ b/sys/dev/nxge/include/xgehal-mgmt.h
@@ -0,0 +1,228 @@
+/*-
+ * Copyright (c) 2002-2007 Neterion, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ *  FileName :    xgehal-mgmt.h
+ *
+ *  Description:  management API
+ *
+ *  Created:      1 September 2004
+ */
+
+#ifndef XGE_HAL_MGMT_H
+#define XGE_HAL_MGMT_H
+
+#include <dev/nxge/include/xge-os-pal.h>
+#include <dev/nxge/include/xge-debug.h>
+#include <dev/nxge/include/xgehal-types.h>
+#include <dev/nxge/include/xgehal-config.h>
+#include <dev/nxge/include/xgehal-stats.h>
+#include <dev/nxge/include/xgehal-regs.h>
+#include <dev/nxge/include/xgehal-device.h>
+
+__EXTERN_BEGIN_DECLS
+
+/**
+ * struct xge_hal_mgmt_about_info_t - About info.
+ * @vendor: PCI Vendor ID.
+ * @device: PCI Device ID.
+ * @subsys_vendor: PCI Subsystem Vendor ID.
+ * @subsys_device: PCI Subsystem Device ID.
+ * @board_rev: PCI Board revision, e.g. 3 - for Xena 3.
+ * @vendor_name: Neterion, Inc.
+ * @chip_name: Xframe.
+ * @media: Fiber, copper.
+ * @hal_major: HAL major version number.
+ * @hal_minor: HAL minor version number.
+ * @hal_fix: HAL fix number.
+ * @hal_build: HAL build number.
+ * @ll_major: Link-layer ULD major version number.
+ * @ll_minor: Link-layer ULD minor version number.
+ * @ll_fix: Link-layer ULD fix version number.
+ * @ll_build: Link-layer ULD build number.
+ * @transponder_temperature: TODO
+ */
+typedef struct xge_hal_mgmt_about_info_t {
+	u16		vendor;
+	u16		device;
+	u16		subsys_vendor;
+	u16		subsys_device;
+	u8		board_rev;
+	char		vendor_name[16];
+	char		chip_name[16];
+	char		media[16];
+	char		hal_major[4];
+	char		hal_minor[4];
+	char		hal_fix[4];
+	char		hal_build[16];
+	char		ll_major[4];
+	char		ll_minor[4];
+	char		ll_fix[4];
+	char		ll_build[16];
+	u32		transponder_temperature;
+} xge_hal_mgmt_about_info_t;
+
+typedef xge_hal_stats_hw_info_t		xge_hal_mgmt_hw_stats_t;
+typedef xge_hal_stats_pcim_info_t	xge_hal_mgmt_pcim_stats_t;
+typedef xge_hal_stats_sw_err_t		xge_hal_mgmt_sw_stats_t;
+typedef xge_hal_stats_device_info_t	xge_hal_mgmt_device_stats_t;
+typedef xge_hal_stats_channel_info_t	xge_hal_mgmt_channel_stats_t;
+typedef xge_hal_device_config_t		xge_hal_mgmt_device_config_t;
+typedef xge_hal_driver_config_t		xge_hal_mgmt_driver_config_t;
+typedef xge_hal_pci_config_t		xge_hal_mgmt_pci_config_t;
+
+xge_hal_status_e
+xge_hal_mgmt_about(xge_hal_device_h devh, xge_hal_mgmt_about_info_t *about_info,
+		int size);
+
+xge_hal_status_e
+xge_hal_mgmt_hw_stats(xge_hal_device_h devh, xge_hal_mgmt_hw_stats_t *hw_stats,
+		int size);
+
+xge_hal_status_e
+xge_hal_mgmt_hw_stats_off(xge_hal_device_h devh, int off, int size, char *out);
+
+xge_hal_status_e
+xge_hal_mgmt_pcim_stats(xge_hal_device_h devh,
+		xge_hal_mgmt_pcim_stats_t *pcim_stats, int size);
+
+xge_hal_status_e
+xge_hal_mgmt_pcim_stats_off(xge_hal_device_h devh, int off, int size,
+		char *out);
+
+xge_hal_status_e
+xge_hal_mgmt_sw_stats(xge_hal_device_h devh, xge_hal_mgmt_sw_stats_t *hw_stats,
+		int size);
+
+xge_hal_status_e
+xge_hal_mgmt_device_stats(xge_hal_device_h devh,
+		xge_hal_mgmt_device_stats_t *device_stats, int size);
+
+xge_hal_status_e
+xge_hal_mgmt_channel_stats(xge_hal_channel_h channelh,
+		xge_hal_mgmt_channel_stats_t *channel_stats, int size);
+
+xge_hal_status_e
+xge_hal_mgmt_reg_read(xge_hal_device_h devh, int bar_id, unsigned int offset,
+		u64 *value);
+
+xge_hal_status_e
+xge_hal_mgmt_reg_write(xge_hal_device_h	devh, int bar_id, unsigned int offset,
+		u64 value);
+
+xge_hal_status_e
+xge_hal_mgmt_pcireg_read(xge_hal_device_h devh, unsigned int offset,
+		int bits, u32 *value);
+
+xge_hal_status_e
+xge_hal_mgmt_device_config(xge_hal_device_h devh,
+		xge_hal_mgmt_device_config_t *dev_config, int size);
+
+xge_hal_status_e
+xge_hal_mgmt_driver_config(xge_hal_mgmt_driver_config_t *drv_config,
+		int size);
+
+xge_hal_status_e
+xge_hal_mgmt_pci_config(xge_hal_device_h devh,
+		xge_hal_mgmt_pci_config_t *pci_config, int size);
+
+xge_hal_status_e
+xge_hal_pma_loopback( xge_hal_device_h devh, int enable );
+
+xge_hal_status_e
+xge_hal_rldram_test(xge_hal_device_h devh, u64 * data);
+
+u16
+xge_hal_mdio_read( xge_hal_device_h devh, u32 mmd_type, u64 addr );
+
+xge_hal_status_e
+xge_hal_mdio_write( xge_hal_device_h devh, u32 mmd_type, u64 addr, u32 value );
+
+u32
+xge_hal_read_xfp_current_temp(xge_hal_device_h devh);
+
+xge_hal_status_e
+xge_hal_read_eeprom(xge_hal_device_h devh, int off, u32* data);
+
+xge_hal_status_e
+xge_hal_write_eeprom(xge_hal_device_h devh, int off, u32 data, int cnt);
+
+xge_hal_status_e
+xge_hal_register_test(xge_hal_device_h devh, u64 *data);
+
+xge_hal_status_e
+xge_hal_eeprom_test(xge_hal_device_h devh, u64 *data);
+
+xge_hal_status_e
+xge_hal_bist_test(xge_hal_device_h devh, u64 *data);
+
+xge_hal_status_e
+xge_hal_link_test(xge_hal_device_h devh, u64 *data);
+
+int
+xge_hal_setpause_data(xge_hal_device_h devh, int tx, int rx);
+
+void
+xge_hal_getpause_data(xge_hal_device_h devh, int *tx, int *rx);
+
+void
+__hal_updt_stats_xpak(xge_hal_device_t *hldev);
+
+void
+__hal_chk_xpak_counter(xge_hal_device_t *hldev, int type, u32 value);
+
+#ifdef XGE_TRACE_INTO_CIRCULAR_ARR
+xge_hal_status_e
+xge_hal_mgmt_trace_read(char *buffer, unsigned buf_size, unsigned *offset,
+		unsigned *read_length);
+#endif
+
+void
+xge_hal_restore_link_led(xge_hal_device_h devh);
+
+
+void
+xge_hal_flick_link_led(xge_hal_device_h devh);
+
+/*
+ * Some set of Xena3 Cards were known to have some link LED
+ * Problems. This macro identifies if the card is among them
+ * given its Sub system ID.
+ */
+#define CARDS_WITH_FAULTY_LINK_INDICATORS(subid) \
+		((((subid >= 0x600B) && (subid <= 0x600D)) || \
+		 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0)
+#define CHECKBIT(value, nbit) (value & (1 << nbit))
+
+#ifdef XGE_HAL_USE_MGMT_AUX
+#include <dev/nxge/include/xgehal-mgmtaux.h>
+#endif
+
+__EXTERN_END_DECLS
+
+#endif /* XGE_HAL_MGMT_H */
diff --git a/sys/dev/nxge/include/xgehal-mgmtaux.h b/sys/dev/nxge/include/xgehal-mgmtaux.h
new file mode 100644
index 0000000..6d4922e
--- /dev/null
+++ b/sys/dev/nxge/include/xgehal-mgmtaux.h
@@ -0,0 +1,95 @@
+/*-
+ * Copyright (c) 2002-2007 Neterion, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ *  FileName :    xgehal-mgmtaux.h
+ *
+ *  Description:  management auxiliary API
+ *
+ *  Created:      1 September 2004
+ */
+
+#ifndef XGE_HAL_MGMTAUX_H
+#define XGE_HAL_MGMTAUX_H
+
+#include <dev/nxge/include/xgehal-mgmt.h>
+
+__EXTERN_BEGIN_DECLS
+
+#define XGE_HAL_AUX_SEPA		' '
+
+xge_hal_status_e xge_hal_aux_about_read(xge_hal_device_h devh, int bufsize,
+			char *retbuf, int *retsize);
+
+xge_hal_status_e xge_hal_aux_stats_tmac_read(xge_hal_device_h devh, int	bufsize,
+			char *retbuf, int *retsize);
+
+xge_hal_status_e xge_hal_aux_stats_rmac_read(xge_hal_device_h devh, int	bufsize,
+			char *retbuf, int *retsize);
+
+xge_hal_status_e xge_hal_aux_stats_sw_dev_read(xge_hal_device_h devh,
+			int bufsize, char *retbuf, int *retsize);
+
+xge_hal_status_e xge_hal_aux_stats_pci_read(xge_hal_device_h devh, int bufsize,
+			char *retbuf, int *retsize);
+
+xge_hal_status_e xge_hal_aux_stats_hal_read(xge_hal_device_h devh, int bufsize,
+			char *retbuf, int *retsize);
+
+xge_hal_status_e xge_hal_aux_bar0_read(xge_hal_device_h	devh,
+			unsigned int offset, int bufsize, char *retbuf,
+			int *retsize);
+
+xge_hal_status_e xge_hal_aux_bar0_write(xge_hal_device_h devh,
+			unsigned int offset, u64 value);
+
+xge_hal_status_e xge_hal_aux_bar1_read(xge_hal_device_h devh,
+			unsigned int offset, int bufsize, char *retbuf,
+			int *retsize);
+
+xge_hal_status_e xge_hal_aux_pci_config_read(xge_hal_device_h devh, int	bufsize,
+			char *retbuf, int *retsize);
+
+xge_hal_status_e xge_hal_aux_stats_herc_enchanced(xge_hal_device_h devh,
+			int bufsize, char *retbuf, int *retsize);
+
+xge_hal_status_e xge_hal_aux_channel_read(xge_hal_device_h devh, int bufsize,
+			char *retbuf, int *retsize);
+
+xge_hal_status_e xge_hal_aux_device_dump(xge_hal_device_h devh);
+
+
+xge_hal_status_e xge_hal_aux_driver_config_read(int bufsize, char *retbuf,
+			int *retsize);
+
+xge_hal_status_e xge_hal_aux_device_config_read(xge_hal_device_h devh,
+			int bufsize, char *retbuf, int *retsize);
+
+__EXTERN_END_DECLS
+
+#endif /* XGE_HAL_MGMTAUX_H */
diff --git a/sys/dev/nxge/include/xgehal-mm.h b/sys/dev/nxge/include/xgehal-mm.h
new file mode 100644
index 0000000..5a8f836
--- /dev/null
+++ b/sys/dev/nxge/include/xgehal-mm.h
@@ -0,0 +1,174 @@
+/*-
+ * Copyright (c) 2002-2007 Neterion, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ *  FileName :    xgehal-mm.h
+ *
+ *  Description:  memory pool object
+ *
+ *  Created:      28 May 2004
+ */
+
+#ifndef XGE_HAL_MM_H
+#define XGE_HAL_MM_H
+
+#include <dev/nxge/include/xge-os-pal.h>
+#include <dev/nxge/include/xge-debug.h>
+#include <dev/nxge/include/xgehal-types.h>
+#include <dev/nxge/include/xgehal-driver.h>
+
+__EXTERN_BEGIN_DECLS
+
+typedef void* xge_hal_mempool_h;
+
+/*
+ * struct xge_hal_mempool_dma_t - Represents DMA objects passed to the
+ caller.
+ */
+typedef struct xge_hal_mempool_dma_t {
+	dma_addr_t			addr;
+	pci_dma_h			handle;
+	pci_dma_acc_h			acc_handle;
+} xge_hal_mempool_dma_t;
+
+/*
+ * xge_hal_mempool_item_f  - Mempool item alloc/free callback
+ * @mempoolh: Memory pool handle.
+ * @item: Item that gets allocated or freed.
+ * @index: Item's index in the memory pool.
+ * @is_last: True, if this item is the last one in the pool; false - otherwise.
+ * userdat: Per-pool user context.
+ *
+ * Memory pool allocation/deallocation callback.
+ */
+typedef xge_hal_status_e (*xge_hal_mempool_item_f) (xge_hal_mempool_h mempoolh,
+				void *memblock, int memblock_index,
+				xge_hal_mempool_dma_t *dma_object, void	*item,
+				int index, int is_last, void *userdata);
+
+/*
+ * struct xge_hal_mempool_t - Memory pool.
+ */
+typedef struct xge_hal_mempool_t {
+	xge_hal_mempool_item_f		item_func_alloc;
+	xge_hal_mempool_item_f		item_func_free;
+	void				*userdata;
+	void				**memblocks_arr;
+	void				**memblocks_priv_arr;
+	xge_hal_mempool_dma_t		*memblocks_dma_arr;
+	pci_dev_h			pdev;
+	int				memblock_size;
+	int				memblocks_max;
+	int				memblocks_allocated;
+	int				item_size;
+	int				items_max;
+	int				items_initial;
+	int				items_current;
+	int				items_per_memblock;
+	void				**items_arr;
+	void				**shadow_items_arr;
+	int				items_priv_size;
+} xge_hal_mempool_t;
+
+/*
+ * __hal_mempool_item - Returns pointer to the item in the mempool
+ * items array.
+ */
+static inline void*
+__hal_mempool_item(xge_hal_mempool_t *mempool, int index)
+{
+	return mempool->items_arr[index];
+}
+
+/*
+ * __hal_mempool_item_priv - will return pointer on per item private space
+ */
+static inline void*
+__hal_mempool_item_priv(xge_hal_mempool_t *mempool, int memblock_idx,
+			void *item, int *memblock_item_idx)
+{
+	ptrdiff_t offset;
+	void *memblock = mempool->memblocks_arr[memblock_idx];
+
+	xge_assert(memblock);
+
+	offset = (int)((char * )item - (char *)memblock);
+	xge_assert(offset >= 0 && offset < mempool->memblock_size);
+
+	(*memblock_item_idx) = (int) offset / mempool->item_size;
+	xge_assert((*memblock_item_idx) < mempool->items_per_memblock);
+
+	return (char*)mempool->memblocks_priv_arr[memblock_idx] +
+			    (*memblock_item_idx) * mempool->items_priv_size;
+}
+
+/*
+ * __hal_mempool_items_arr - will return pointer to the items array in the
+ *  mempool.
+ */
+static inline void*
+__hal_mempool_items_arr(xge_hal_mempool_t *mempool)
+{
+	return mempool->items_arr;
+}
+
+/*
+ * __hal_mempool_memblock - will return pointer to the memblock in the
+ *  mempool memblocks array.
+ */
+static inline void*
+__hal_mempool_memblock(xge_hal_mempool_t *mempool, int memblock_idx)
+{
+	xge_assert(mempool->memblocks_arr[memblock_idx]);
+	return mempool->memblocks_arr[memblock_idx];
+}
+
+/*
+ * __hal_mempool_memblock_dma - will return pointer to the dma block
+ *  corresponds to the memblock(identified by memblock_idx) in the mempool.
+ */
+static inline xge_hal_mempool_dma_t*
+__hal_mempool_memblock_dma(xge_hal_mempool_t *mempool, int memblock_idx)
+{
+	return mempool->memblocks_dma_arr + memblock_idx;
+}
+
+xge_hal_status_e __hal_mempool_grow(xge_hal_mempool_t *mempool,
+			int num_allocate, int *num_allocated);
+
+xge_hal_mempool_t* __hal_mempool_create(pci_dev_h pdev, int memblock_size,
+			int item_size, int private_size, int items_initial,
+			int items_max, xge_hal_mempool_item_f item_func_alloc,
+			xge_hal_mempool_item_f item_func_free, void *userdata);
+
+void __hal_mempool_destroy(xge_hal_mempool_t *mempool);
+
+
+__EXTERN_END_DECLS
+
+#endif /* XGE_HAL_MM_H */
diff --git a/sys/dev/nxge/include/xgehal-regs.h b/sys/dev/nxge/include/xgehal-regs.h
new file mode 100644
index 0000000..89a2c4a
--- /dev/null
+++ b/sys/dev/nxge/include/xgehal-regs.h
@@ -0,0 +1,1377 @@
+/*-
+ * Copyright (c) 2002-2007 Neterion, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ *  FileName :    xgehal-regs.h
+ *
+ *  Description:  Xframe mem-mapped register space
+ *
+ *  Created:      14 May 2004
+ */
+
+#ifndef XGE_HAL_REGS_H
+#define XGE_HAL_REGS_H
+
+typedef struct {
+
+/* General Control-Status Registers */
+	u64 general_int_status;
+#define XGE_HAL_GEN_INTR_TXPIC             BIT(0)
+#define XGE_HAL_GEN_INTR_TXDMA             BIT(1)
+#define XGE_HAL_GEN_INTR_TXMAC             BIT(2)
+#define XGE_HAL_GEN_INTR_TXXGXS            BIT(3)
+#define XGE_HAL_GEN_INTR_TXTRAFFIC         BIT(8)
+#define XGE_HAL_GEN_INTR_RXPIC             BIT(32)
+#define XGE_HAL_GEN_INTR_RXDMA             BIT(33)
+#define XGE_HAL_GEN_INTR_RXMAC             BIT(34)
+#define XGE_HAL_GEN_INTR_MC                BIT(35)
+#define XGE_HAL_GEN_INTR_RXXGXS            BIT(36)
+#define XGE_HAL_GEN_INTR_RXTRAFFIC         BIT(40)
+#define XGE_HAL_GEN_ERROR_INTR             (XGE_HAL_GEN_INTR_TXPIC  | \
+					 XGE_HAL_GEN_INTR_RXPIC  | \
+					 XGE_HAL_GEN_INTR_TXDMA  | \
+					 XGE_HAL_GEN_INTR_RXDMA  | \
+					 XGE_HAL_GEN_INTR_TXMAC  | \
+					 XGE_HAL_GEN_INTR_RXMAC  | \
+					 XGE_HAL_GEN_INTR_TXXGXS | \
+					 XGE_HAL_GEN_INTR_RXXGXS | \
+					 XGE_HAL_GEN_INTR_MC)
+
+	u64 general_int_mask;
+
+	u8 unused0[0x100 - 0x10];
+
+	u64 sw_reset;
+
+/* XGXS must be removed from reset only once. */
+#define XGE_HAL_SW_RESET_XENA              vBIT(0xA5,0,8)
+#define XGE_HAL_SW_RESET_FLASH             vBIT(0xA5,8,8)
+#define XGE_HAL_SW_RESET_EOI               vBIT(0xA5,16,8)
+#define XGE_HAL_SW_RESET_XGXS              vBIT(0xA5,24,8)
+#define XGE_HAL_SW_RESET_ALL               (XGE_HAL_SW_RESET_XENA  | \
+					    XGE_HAL_SW_RESET_FLASH | \
+					    XGE_HAL_SW_RESET_EOI | \
+					    XGE_HAL_SW_RESET_XGXS)
+
+/* The SW_RESET register must read this value after a successful reset. */
+#if defined(XGE_OS_HOST_BIG_ENDIAN) && !defined(XGE_OS_PIO_LITTLE_ENDIAN)
+#define XGE_HAL_SW_RESET_RAW_VAL_XENA			0xA500000000ULL
+#define XGE_HAL_SW_RESET_RAW_VAL_HERC			0xA5A500000000ULL
+#else
+#define XGE_HAL_SW_RESET_RAW_VAL_XENA			0xA5000000ULL
+#define XGE_HAL_SW_RESET_RAW_VAL_HERC			0xA5A50000ULL
+#endif
+
+
+	u64 adapter_status;
+#define XGE_HAL_ADAPTER_STATUS_TDMA_READY          BIT(0)
+#define XGE_HAL_ADAPTER_STATUS_RDMA_READY          BIT(1)
+#define XGE_HAL_ADAPTER_STATUS_PFC_READY           BIT(2)
+#define XGE_HAL_ADAPTER_STATUS_TMAC_BUF_EMPTY      BIT(3)
+#define XGE_HAL_ADAPTER_STATUS_PIC_QUIESCENT       BIT(5)
+#define XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT   BIT(6)
+#define XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT    BIT(7)
+#define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_IDLE       vBIT(0xFF,8,8)
+#define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_4_IDLE     vBIT(0x0F,8,8)
+#define XGE_HAL_ADAPTER_PCC_ENABLE_FOUR            vBIT(0x0F,0,8)
+
+#define XGE_HAL_ADAPTER_STATUS_RC_PRC_QUIESCENT    vBIT(0xFF,16,8)
+#define XGE_HAL_ADAPTER_STATUS_MC_DRAM_READY       BIT(24)
+#define XGE_HAL_ADAPTER_STATUS_MC_QUEUES_READY     BIT(25)
+#define XGE_HAL_ADAPTER_STATUS_M_PLL_LOCK          BIT(30)
+#define XGE_HAL_ADAPTER_STATUS_P_PLL_LOCK          BIT(31)
+
+	u64 adapter_control;
+#define XGE_HAL_ADAPTER_CNTL_EN                    BIT(7)
+#define XGE_HAL_ADAPTER_EOI_TX_ON                  BIT(15)
+#define XGE_HAL_ADAPTER_LED_ON                     BIT(23)
+#define XGE_HAL_ADAPTER_UDPI(val)                  vBIT(val,36,4)
+#define XGE_HAL_ADAPTER_WAIT_INT                   BIT(48)
+#define XGE_HAL_ADAPTER_ECC_EN                     BIT(55)
+
+	u64 serr_source;
+#define XGE_HAL_SERR_SOURCE_PIC	                BIT(0)
+#define XGE_HAL_SERR_SOURCE_TXDMA               BIT(1)
+#define XGE_HAL_SERR_SOURCE_RXDMA               BIT(2)
+#define XGE_HAL_SERR_SOURCE_MAC			BIT(3)
+#define XGE_HAL_SERR_SOURCE_MC			BIT(4)
+#define XGE_HAL_SERR_SOURCE_XGXS			 BIT(5)
+#define XGE_HAL_SERR_SOURCE_ANY		(XGE_HAL_SERR_SOURCE_PIC   | \
+					 XGE_HAL_SERR_SOURCE_TXDMA | \
+					 XGE_HAL_SERR_SOURCE_RXDMA | \
+					 XGE_HAL_SERR_SOURCE_MAC   | \
+					 XGE_HAL_SERR_SOURCE_MC    | \
+					 XGE_HAL_SERR_SOURCE_XGXS)
+
+	u64	pci_info;
+#define XGE_HAL_PCI_INFO			vBIT(0xF,0,4)
+#define XGE_HAL_PCI_32_BIT			BIT(8)
+
+	u8 unused0_1[0x160 - 0x128];
+ 
+	u64 ric_status;
+
+	u8  unused0_2[0x558 - 0x168];
+
+	u64 mbist_status;
+
+	u8  unused0_3[0x800 - 0x560];
+
+/* PCI-X Controller registers */
+	u64 pic_int_status;
+	u64 pic_int_mask;
+#define XGE_HAL_PIC_INT_TX                     BIT(0)
+#define XGE_HAL_PIC_INT_FLSH                   BIT(1)
+#define XGE_HAL_PIC_INT_MDIO                   BIT(2)
+#define XGE_HAL_PIC_INT_IIC                    BIT(3)
+#define XGE_HAL_PIC_INT_MISC                   BIT(4)
+#define XGE_HAL_PIC_INT_RX                     BIT(32)
+
+	u64 txpic_int_reg;
+#define XGE_HAL_TXPIC_INT_SCHED_INTR            BIT(42)
+	u64 txpic_int_mask;
+#define XGE_HAL_PCIX_INT_REG_ECC_SG_ERR                BIT(0)
+#define XGE_HAL_PCIX_INT_REG_ECC_DB_ERR                BIT(1)
+#define XGE_HAL_PCIX_INT_REG_FLASHR_R_FSM_ERR          BIT(8)
+#define XGE_HAL_PCIX_INT_REG_FLASHR_W_FSM_ERR          BIT(9)
+#define XGE_HAL_PCIX_INT_REG_INI_TX_FSM_SERR           BIT(10)
+#define XGE_HAL_PCIX_INT_REG_INI_TXO_FSM_ERR           BIT(11)
+#define XGE_HAL_PCIX_INT_REG_TRT_FSM_SERR              BIT(13)
+#define XGE_HAL_PCIX_INT_REG_SRT_FSM_SERR              BIT(14)
+#define XGE_HAL_PCIX_INT_REG_PIFR_FSM_SERR             BIT(15)
+#define XGE_HAL_PCIX_INT_REG_WRC_TX_SEND_FSM_SERR      BIT(21)
+#define XGE_HAL_PCIX_INT_REG_RRC_TX_REQ_FSM_SERR       BIT(23)
+#define XGE_HAL_PCIX_INT_REG_INI_RX_FSM_SERR           BIT(48)
+#define XGE_HAL_PCIX_INT_REG_RA_RX_FSM_SERR            BIT(50)
+/*
+#define XGE_HAL_PCIX_INT_REG_WRC_RX_SEND_FSM_SERR      BIT(52)
+#define XGE_HAL_PCIX_INT_REG_RRC_RX_REQ_FSM_SERR       BIT(54)
+#define XGE_HAL_PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR     BIT(58)
+*/
+	u64 txpic_alarms;
+	u64 rxpic_int_reg;
+#define XGE_HAL_RX_PIC_INT_REG_SPDM_READY               BIT(0)
+#define XGE_HAL_RX_PIC_INT_REG_SPDM_OVERWRITE_ERR       BIT(44)
+#define XGE_HAL_RX_PIC_INT_REG_SPDM_PERR                BIT(55)
+	u64 rxpic_int_mask;
+	u64 rxpic_alarms;
+
+	u64 flsh_int_reg;
+	u64 flsh_int_mask;
+#define XGE_HAL_PIC_FLSH_INT_REG_CYCLE_FSM_ERR          BIT(63)
+#define XGE_HAL_PIC_FLSH_INT_REG_ERR                    BIT(62)
+	u64 flash_alarms;
+
+	u64 mdio_int_reg;
+	u64 mdio_int_mask;
+#define XGE_HAL_MDIO_INT_REG_MDIO_BUS_ERR              BIT(0)
+#define XGE_HAL_MDIO_INT_REG_DTX_BUS_ERR               BIT(8)
+#define XGE_HAL_MDIO_INT_REG_LASI                      BIT(39)
+	u64 mdio_alarms;
+
+	u64 iic_int_reg;
+	u64 iic_int_mask;
+#define XGE_HAL_IIC_INT_REG_BUS_FSM_ERR                BIT(4)
+#define XGE_HAL_IIC_INT_REG_BIT_FSM_ERR                BIT(5)
+#define XGE_HAL_IIC_INT_REG_CYCLE_FSM_ERR              BIT(6)
+#define XGE_HAL_IIC_INT_REG_REQ_FSM_ERR                BIT(7)
+#define XGE_HAL_IIC_INT_REG_ACK_ERR                    BIT(8)
+	u64 iic_alarms;
+
+	u64 msi_pending_reg;
+
+	u64 misc_int_reg;
+#define XGE_HAL_MISC_INT_REG_DP_ERR_INT			BIT(0)
+#define XGE_HAL_MISC_INT_REG_LINK_DOWN_INT		BIT(1)
+#define XGE_HAL_MISC_INT_REG_LINK_UP_INT		BIT(2)
+	u64 misc_int_mask;
+	u64 misc_alarms;
+
+	u64 msi_triggered_reg;
+
+	u64 xfp_gpio_int_reg;
+	u64 xfp_gpio_int_mask;
+	u64 xfp_alarms;
+
+	u8  unused5[0x8E0 - 0x8C8];
+
+	u64 tx_traffic_int;
+#define XGE_HAL_TX_TRAFFIC_INT_n(n)                     BIT(n)
+	u64 tx_traffic_mask;
+
+	u64 rx_traffic_int;
+#define XGE_HAL_RX_TRAFFIC_INT_n(n)                     BIT(n)
+	u64 rx_traffic_mask;
+
+/* PIC Control registers */
+	u64 pic_control;
+#define XGE_HAL_PIC_CNTL_RX_ALARM_MAP_1                BIT(0)
+#define XGE_HAL_PIC_CNTL_ONE_SHOT_TINT                 BIT(1)
+#define XGE_HAL_PIC_CNTL_SHARED_SPLITS(n)              vBIT(n,11,4)
+
+	u64 swapper_ctrl;
+#define XGE_HAL_SWAPPER_CTRL_PIF_R_FE                  BIT(0)
+#define XGE_HAL_SWAPPER_CTRL_PIF_R_SE                  BIT(1)
+#define XGE_HAL_SWAPPER_CTRL_PIF_W_FE                  BIT(8)
+#define XGE_HAL_SWAPPER_CTRL_PIF_W_SE                  BIT(9)
+#define XGE_HAL_SWAPPER_CTRL_RTH_FE                    BIT(10)
+#define XGE_HAL_SWAPPER_CTRL_RTH_SE                    BIT(11)
+#define XGE_HAL_SWAPPER_CTRL_TXP_FE                    BIT(16)
+#define XGE_HAL_SWAPPER_CTRL_TXP_SE                    BIT(17)
+#define XGE_HAL_SWAPPER_CTRL_TXD_R_FE                  BIT(18)
+#define XGE_HAL_SWAPPER_CTRL_TXD_R_SE                  BIT(19)
+#define XGE_HAL_SWAPPER_CTRL_TXD_W_FE                  BIT(20)
+#define XGE_HAL_SWAPPER_CTRL_TXD_W_SE                  BIT(21)
+#define XGE_HAL_SWAPPER_CTRL_TXF_R_FE                  BIT(22)
+#define XGE_HAL_SWAPPER_CTRL_TXF_R_SE                  BIT(23)
+#define XGE_HAL_SWAPPER_CTRL_RXD_R_FE                  BIT(32)
+#define XGE_HAL_SWAPPER_CTRL_RXD_R_SE                  BIT(33)
+#define XGE_HAL_SWAPPER_CTRL_RXD_W_FE                  BIT(34)
+#define XGE_HAL_SWAPPER_CTRL_RXD_W_SE                  BIT(35)
+#define XGE_HAL_SWAPPER_CTRL_RXF_W_FE                  BIT(36)
+#define XGE_HAL_SWAPPER_CTRL_RXF_W_SE                  BIT(37)
+#define XGE_HAL_SWAPPER_CTRL_XMSI_FE                   BIT(40)
+#define XGE_HAL_SWAPPER_CTRL_XMSI_SE                   BIT(41)
+#define XGE_HAL_SWAPPER_CTRL_STATS_FE                  BIT(48)
+#define XGE_HAL_SWAPPER_CTRL_STATS_SE                  BIT(49)
+
+	u64 pif_rd_swapper_fb;
+#define XGE_HAL_IF_RD_SWAPPER_FB   0x0123456789ABCDEFULL
+
+	u64 scheduled_int_ctrl;
+#define XGE_HAL_SCHED_INT_CTRL_TIMER_EN                BIT(0)
+#define XGE_HAL_SCHED_INT_CTRL_ONE_SHOT                BIT(1)
+#define XGE_HAL_SCHED_INT_CTRL_INT2MSI(val)	     vBIT(val,10,6)
+#define XGE_HAL_SCHED_INT_PERIOD(val)		     vBIT(val,32,32)
+#define XGE_HAL_SCHED_INT_PERIOD_MASK		     0xFFFFFFFF00000000ULL
+
+
+	u64 txreqtimeout;
+#define XGE_HAL_TXREQTO_VAL(val)		vBIT(val,0,32)
+#define XGE_HAL_TXREQTO_EN			BIT(63)
+
+	u64 statsreqtimeout;
+#define XGE_HAL_STATREQTO_VAL(n)                  TBD
+#define XGE_HAL_STATREQTO_EN                      BIT(63)
+
+	u64 read_retry_delay;
+	u64 read_retry_acceleration;
+	u64 write_retry_delay;
+	u64 write_retry_acceleration;
+
+	u64 xmsi_control;
+#define XGE_HAL_XMSI_EN				BIT(0)
+#define XGE_HAL_XMSI_DIS_TINT_SERR		BIT(1)
+#define XGE_HAL_XMSI_BYTE_COUNT(val)		vBIT(val,13,3)
+
+	u64 xmsi_access;
+#define XGE_HAL_XMSI_WR_RDN			BIT(7)
+#define XGE_HAL_XMSI_STROBE			BIT(15)
+#define XGE_HAL_XMSI_NO(val)			vBIT(val,26,6)
+
+	u64 xmsi_address;
+	u64 xmsi_data;
+
+	u64 rx_mat;
+#define XGE_HAL_SET_RX_MAT(ring, msi)	vBIT(msi, (8 * ring), 8)
+
+	u8 unused6[0x8];
+
+	u64 tx_mat[8];
+#define XGE_HAL_SET_TX_MAT(fifo, msi)	vBIT(msi, (8 * fifo), 8)
+
+	u64 xmsi_mask_reg;
+
+	/* Automated statistics collection */
+	u64 stat_byte_cnt;
+	u64 stat_cfg;
+#define XGE_HAL_STAT_CFG_STAT_EN           BIT(0)
+#define XGE_HAL_STAT_CFG_ONE_SHOT_EN       BIT(1)
+#define XGE_HAL_STAT_CFG_STAT_NS_EN        BIT(8)
+#define XGE_HAL_STAT_CFG_STAT_RO           BIT(9)
+#define XGE_HAL_XENA_PER_SEC	           0x208d5
+#define XGE_HAL_SET_UPDT_PERIOD(n)	   vBIT(n,32,32)
+
+	u64 stat_addr;
+
+	/* General Configuration */
+	u64 mdio_control;
+#define XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(n)	vBIT(n,0,16)
+#define XGE_HAL_MDIO_CONTROL_MMD_DEV_ADDR(n)	vBIT(n,19,5)
+#define XGE_HAL_MDIO_CONTROL_MMD_PRT_ADDR(n)	vBIT(n,27,5)
+#define XGE_HAL_MDIO_CONTROL_MMD_DATA(n)	vBIT(n,32,16)
+#define XGE_HAL_MDIO_CONTROL_MMD_CTRL(n)	vBIT(n,56,4)
+#define XGE_HAL_MDIO_CONTROL_MMD_OP(n)		vBIT(n,60,2)
+#define XGE_HAL_MDIO_CONTROL_MMD_DATA_GET(n)	((n>>16)&0xFFFF)
+#define XGE_HAL_MDIO_MMD_PMA_DEV_ADDR		0x01
+#define XGE_HAL_MDIO_DOM_REG_ADDR		0xA100
+#define XGE_HAL_MDIO_ALARM_FLAGS_ADDR		0xA070
+#define XGE_HAL_MDIO_WARN_FLAGS_ADDR		0xA074
+#define XGE_HAL_MDIO_CTRL_START			0xE
+#define XGE_HAL_MDIO_OP_ADDRESS			0x0
+#define XGE_HAL_MDIO_OP_WRITE			0x1
+#define XGE_HAL_MDIO_OP_READ			0x3
+#define XGE_HAL_MDIO_OP_READ_POST_INCREMENT	0x2
+#define XGE_HAL_MDIO_ALARM_TEMPHIGH		0x0080
+#define XGE_HAL_MDIO_ALARM_TEMPLOW		0x0040
+#define XGE_HAL_MDIO_ALARM_BIASHIGH		0x0008
+#define XGE_HAL_MDIO_ALARM_BIASLOW		0x0004
+#define XGE_HAL_MDIO_ALARM_POUTPUTHIGH		0x0002
+#define XGE_HAL_MDIO_ALARM_POUTPUTLOW		0x0001
+#define XGE_HAL_MDIO_WARN_TEMPHIGH		0x0080
+#define XGE_HAL_MDIO_WARN_TEMPLOW		0x0040
+#define XGE_HAL_MDIO_WARN_BIASHIGH		0x0008
+#define XGE_HAL_MDIO_WARN_BIASLOW		0x0004
+#define XGE_HAL_MDIO_WARN_POUTPUTHIGH		0x0002
+#define XGE_HAL_MDIO_WARN_POUTPUTLOW		0x0001
+
+	u64 dtx_control;
+
+	u64 i2c_control;
+#define XGE_HAL_I2C_CONTROL_DEV_ID(id)		vBIT(id,1,3)
+#define XGE_HAL_I2C_CONTROL_ADDR(addr)		vBIT(addr,5,11)
+#define XGE_HAL_I2C_CONTROL_BYTE_CNT(cnt)	vBIT(cnt,22,2)
+#define XGE_HAL_I2C_CONTROL_READ		BIT(24)
+#define XGE_HAL_I2C_CONTROL_NACK		BIT(25)
+#define XGE_HAL_I2C_CONTROL_CNTL_START		vBIT(0xE,28,4)
+#define XGE_HAL_I2C_CONTROL_CNTL_END(val)	(val & vBIT(0x1,28,4))
+#define XGE_HAL_I2C_CONTROL_GET_DATA(val)	(u32)(val & 0xFFFFFFFF)
+#define XGE_HAL_I2C_CONTROL_SET_DATA(val)	vBIT(val,32,32)
+
+	u64 beacon_control;
+	u64 misc_control;
+#define XGE_HAL_MISC_CONTROL_LINK_STABILITY_PERIOD(val)	vBIT(val,29,3)
+#define XGE_HAL_MISC_CONTROL_EXT_REQ_EN     BIT(1)
+#define XGE_HAL_MISC_CONTROL_LINK_FAULT		BIT(0)
+
+	u64 xfb_control;
+	u64 gpio_control;
+#define XGE_HAL_GPIO_CTRL_GPIO_0           	BIT(8)
+
+	u64 txfifo_dw_mask;
+	u64 split_table_line_no;
+	u64 sc_timeout;
+	u64 pic_control_2;
+#define XGE_HAL_TXD_WRITE_BC(n)                 vBIT(n, 13, 3)
+	u64 ini_dperr_ctrl;
+	u64 wreq_split_mask;
+	u64 qw_per_rxd;
+	u8  unused7[0x300 - 0x250];
+
+	u64 pic_status;
+	u64 txp_status;
+	u64 txp_err_context;
+	u64 spdm_bir_offset;
+#define XGE_HAL_SPDM_PCI_BAR_NUM(spdm_bir_offset)	\
+				(u8)(spdm_bir_offset >> 61)
+#define XGE_HAL_SPDM_PCI_BAR_OFFSET(spdm_bir_offset) \
+				(u32)((spdm_bir_offset >> 32) & 0x1FFFFFFF)
+	u64 spdm_overwrite;
+#define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_ENTRY(spdm_overwrite)  \
+				(u8)((spdm_overwrite >> 48) & 0xff)
+#define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_DW(spdm_overwrite)  \
+				(u8)((spdm_overwrite >> 40) & 0x3)
+#define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_LINE(spdm_overwrite)  \
+				(u8)((spdm_overwrite >> 32) & 0x7)
+	u64 cfg_addr_on_dperr;
+	u64 pif_addr_on_dperr;
+	u64 tags_in_use;
+	u64 rd_req_types;
+	u64 split_table_line;
+	u64 unxp_split_add_ph;
+	u64 unexp_split_attr_ph;
+	u64 split_message;
+	u64 spdm_structure;
+#define XGE_HAL_SPDM_MAX_ENTRIES(spdm_structure)  (u16)(spdm_structure >> 48)
+#define XGE_HAL_SPDM_INT_QW_PER_ENTRY(spdm_structure)  \
+				(u8)((spdm_structure >> 40) & 0xff)
+#define XGE_HAL_SPDM_PCI_QW_PER_ENTRY(spdm_structure)  \
+				(u8)((spdm_structure >> 32) & 0xff)
+
+	u64 txdw_ptr_cnt_0;
+	u64 txdw_ptr_cnt_1;
+	u64 txdw_ptr_cnt_2;
+	u64 txdw_ptr_cnt_3;
+	u64 txdw_ptr_cnt_4;
+	u64 txdw_ptr_cnt_5;
+	u64 txdw_ptr_cnt_6;
+	u64 txdw_ptr_cnt_7;
+	u64 rxdw_cnt_ring_0;
+	u64 rxdw_cnt_ring_1;
+	u64 rxdw_cnt_ring_2;
+	u64 rxdw_cnt_ring_3;
+	u64 rxdw_cnt_ring_4;
+	u64 rxdw_cnt_ring_5;
+	u64 rxdw_cnt_ring_6;
+	u64 rxdw_cnt_ring_7;
+
+	u8  unused8[0x410];
+
+/* TxDMA registers */
+	u64 txdma_int_status;
+	u64 txdma_int_mask;
+#define XGE_HAL_TXDMA_PFC_INT			BIT(0)
+#define XGE_HAL_TXDMA_TDA_INT			BIT(1)
+#define XGE_HAL_TXDMA_PCC_INT			BIT(2)
+#define XGE_HAL_TXDMA_TTI_INT			BIT(3)
+#define XGE_HAL_TXDMA_LSO_INT			BIT(4)
+#define XGE_HAL_TXDMA_TPA_INT			BIT(5)
+#define XGE_HAL_TXDMA_SM_INT			BIT(6)
+	u64 pfc_err_reg;
+#define XGE_HAL_PFC_ECC_SG_ERR			BIT(7)
+#define XGE_HAL_PFC_ECC_DB_ERR			BIT(15)
+#define XGE_HAL_PFC_SM_ERR_ALARM		BIT(23)
+#define XGE_HAL_PFC_MISC_0_ERR			BIT(31)
+#define XGE_HAL_PFC_MISC_1_ERR			BIT(32)
+#define XGE_HAL_PFC_PCIX_ERR			BIT(39)
+	u64 pfc_err_mask;
+	u64 pfc_err_alarm;
+
+	u64 tda_err_reg;
+#define XGE_HAL_TDA_Fn_ECC_SG_ERR		vBIT(0xff,0,8)
+#define XGE_HAL_TDA_Fn_ECC_DB_ERR		vBIT(0xff,8,8)
+#define XGE_HAL_TDA_SM0_ERR_ALARM		BIT(22)
+#define XGE_HAL_TDA_SM1_ERR_ALARM		BIT(23)
+#define XGE_HAL_TDA_PCIX_ERR			BIT(39)
+	u64 tda_err_mask;
+	u64 tda_err_alarm;
+
+	u64 pcc_err_reg;
+#define XGE_HAL_PCC_FB_ECC_SG_ERR		vBIT(0xFF,0,8)
+#define XGE_HAL_PCC_TXB_ECC_SG_ERR		vBIT(0xFF,8,8)
+#define XGE_HAL_PCC_FB_ECC_DB_ERR		vBIT(0xFF,16, 8)
+#define XGE_HAL_PCC_TXB_ECC_DB_ERR		vBIT(0xff,24,8)
+#define XGE_HAL_PCC_SM_ERR_ALARM		vBIT(0xff,32,8)
+#define XGE_HAL_PCC_WR_ERR_ALARM		vBIT(0xff,40,8)
+#define XGE_HAL_PCC_N_SERR			vBIT(0xff,48,8)
+#define XGE_HAL_PCC_ENABLE_FOUR			vBIT(0x0F,0,8)
+#define XGE_HAL_PCC_6_COF_OV_ERR		BIT(56)
+#define XGE_HAL_PCC_7_COF_OV_ERR		BIT(57)
+#define XGE_HAL_PCC_6_LSO_OV_ERR		BIT(58)
+#define XGE_HAL_PCC_7_LSO_OV_ERR		BIT(59)
+	u64 pcc_err_mask;
+	u64 pcc_err_alarm;
+
+	u64 tti_err_reg;
+#define XGE_HAL_TTI_ECC_SG_ERR			BIT(7)
+#define XGE_HAL_TTI_ECC_DB_ERR			BIT(15)
+#define XGE_HAL_TTI_SM_ERR_ALARM		BIT(23)
+	u64 tti_err_mask;
+	u64 tti_err_alarm;
+
+	u64 lso_err_reg;
+#define XGE_HAL_LSO6_SEND_OFLOW			BIT(12)
+#define XGE_HAL_LSO7_SEND_OFLOW			BIT(13)
+#define XGE_HAL_LSO6_ABORT			BIT(14)
+#define XGE_HAL_LSO7_ABORT			BIT(15)
+#define XGE_HAL_LSO6_SM_ERR_ALARM		BIT(22)
+#define XGE_HAL_LSO7_SM_ERR_ALARM		BIT(23)
+	u64 lso_err_mask;
+	u64 lso_err_alarm;
+
+	u64 tpa_err_reg;
+#define XGE_HAL_TPA_TX_FRM_DROP			BIT(7)
+#define XGE_HAL_TPA_SM_ERR_ALARM		BIT(23)
+	u64 tpa_err_mask;
+	u64 tpa_err_alarm;
+
+	u64 sm_err_reg;
+#define XGE_HAL_SM_SM_ERR_ALARM			BIT(15)
+	u64 sm_err_mask;
+	u64 sm_err_alarm;
+
+	u8 unused9[0x100 - 0xB8];
+
+/* TxDMA arbiter */
+	u64 tx_dma_wrap_stat;
+
+/* Tx FIFO controller */
+#define XGE_HAL_X_MAX_FIFOS                        8
+#define XGE_HAL_X_FIFO_MAX_LEN                     0x1FFF	/*8191 */
+	u64 tx_fifo_partition_0;
+#define XGE_HAL_TX_FIFO_PARTITION_EN               BIT(0)
+#define XGE_HAL_TX_FIFO_PARTITION_0_PRI(val)       vBIT(val,5,3)
+#define XGE_HAL_TX_FIFO_PARTITION_0_LEN(val)       vBIT(val,19,13)
+#define XGE_HAL_TX_FIFO_PARTITION_1_PRI(val)       vBIT(val,37,3)
+#define XGE_HAL_TX_FIFO_PARTITION_1_LEN(val)       vBIT(val,51,13  )
+
+	u64 tx_fifo_partition_1;
+#define XGE_HAL_TX_FIFO_PARTITION_2_PRI(val)       vBIT(val,5,3)
+#define XGE_HAL_TX_FIFO_PARTITION_2_LEN(val)       vBIT(val,19,13)
+#define XGE_HAL_TX_FIFO_PARTITION_3_PRI(val)       vBIT(val,37,3)
+#define XGE_HAL_TX_FIFO_PARTITION_3_LEN(val)       vBIT(val,51,13)
+
+	u64 tx_fifo_partition_2;
+#define XGE_HAL_TX_FIFO_PARTITION_4_PRI(val)       vBIT(val,5,3)
+#define XGE_HAL_TX_FIFO_PARTITION_4_LEN(val)       vBIT(val,19,13)
+#define XGE_HAL_TX_FIFO_PARTITION_5_PRI(val)       vBIT(val,37,3)
+#define XGE_HAL_TX_FIFO_PARTITION_5_LEN(val)       vBIT(val,51,13)
+
+	u64 tx_fifo_partition_3;
+#define XGE_HAL_TX_FIFO_PARTITION_6_PRI(val)       vBIT(val,5,3)
+#define XGE_HAL_TX_FIFO_PARTITION_6_LEN(val)       vBIT(val,19,13)
+#define XGE_HAL_TX_FIFO_PARTITION_7_PRI(val)       vBIT(val,37,3)
+#define XGE_HAL_TX_FIFO_PARTITION_7_LEN(val)       vBIT(val,51,13)
+
+#define XGE_HAL_TX_FIFO_PARTITION_PRI_0            0	/* highest */
+#define XGE_HAL_TX_FIFO_PARTITION_PRI_1            1
+#define XGE_HAL_TX_FIFO_PARTITION_PRI_2            2
+#define XGE_HAL_TX_FIFO_PARTITION_PRI_3            3
+#define XGE_HAL_TX_FIFO_PARTITION_PRI_4            4
+#define XGE_HAL_TX_FIFO_PARTITION_PRI_5            5
+#define XGE_HAL_TX_FIFO_PARTITION_PRI_6            6
+#define XGE_HAL_TX_FIFO_PARTITION_PRI_7            7	/* lowest */
+
+	u64 tx_w_round_robin_0;
+	u64 tx_w_round_robin_1;
+	u64 tx_w_round_robin_2;
+	u64 tx_w_round_robin_3;
+	u64 tx_w_round_robin_4;
+
+	u64 tti_command_mem;
+#define XGE_HAL_TTI_CMD_MEM_WE                     BIT(7)
+#define XGE_HAL_TTI_CMD_MEM_STROBE_NEW_CMD         BIT(15)
+#define XGE_HAL_TTI_CMD_MEM_STROBE_BEING_EXECUTED  BIT(15)
+#define XGE_HAL_TTI_CMD_MEM_OFFSET(n)              vBIT(n,26,6)
+
+	u64 tti_data1_mem;
+#define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_VAL(n)      vBIT(n,6,26)
+#define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_CI(n)    vBIT(n,38,2)
+#define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_EN       BIT(38)
+#define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_CI_EN       BIT(39)
+#define XGE_HAL_TTI_DATA1_MEM_TX_URNG_A(n)         vBIT(n,41,7)
+#define XGE_HAL_TTI_DATA1_MEM_TX_URNG_B(n)         vBIT(n,49,7)
+#define XGE_HAL_TTI_DATA1_MEM_TX_URNG_C(n)         vBIT(n,57,7)
+
+	u64 tti_data2_mem;
+#define XGE_HAL_TTI_DATA2_MEM_TX_UFC_A(n)          vBIT(n,0,16)
+#define XGE_HAL_TTI_DATA2_MEM_TX_UFC_B(n)          vBIT(n,16,16)
+#define XGE_HAL_TTI_DATA2_MEM_TX_UFC_C(n)          vBIT(n,32,16)
+#define XGE_HAL_TTI_DATA2_MEM_TX_UFC_D(n)          vBIT(n,48,16)
+
+/* Tx Protocol assist */
+	u64 tx_pa_cfg;
+#define XGE_HAL_TX_PA_CFG_IGNORE_FRM_ERR           BIT(1)
+#define XGE_HAL_TX_PA_CFG_IGNORE_SNAP_OUI          BIT(2)
+#define XGE_HAL_TX_PA_CFG_IGNORE_LLC_CTRL          BIT(3)
+#define XGE_HAL_TX_PA_CFG_IGNORE_L2_ERR		 BIT(6)
+
+/* Recent add, used only debug purposes. */
+	u64 pcc_enable;
+	
+	u64 pfc_monitor_0;
+	u64 pfc_monitor_1;
+	u64 pfc_monitor_2;
+	u64 pfc_monitor_3;
+	u64 txd_ownership_ctrl;
+	u64 pfc_read_cntrl;
+	u64 pfc_read_data;
+	
+	u8  unused10[0x1700 - 0x11B0];
+	
+	u64 txdma_debug_ctrl;
+
+	u8 unused11[0x1800 - 0x1708];
+
+/* RxDMA Registers */
+	u64 rxdma_int_status;
+#define XGE_HAL_RXDMA_RC_INT                   BIT(0)
+#define XGE_HAL_RXDMA_RPA_INT                  BIT(1)
+#define XGE_HAL_RXDMA_RDA_INT                  BIT(2)
+#define XGE_HAL_RXDMA_RTI_INT                  BIT(3)
+
+	u64 rxdma_int_mask;
+#define XGE_HAL_RXDMA_INT_RC_INT_M             BIT(0)
+#define XGE_HAL_RXDMA_INT_RPA_INT_M            BIT(1)
+#define XGE_HAL_RXDMA_INT_RDA_INT_M            BIT(2)
+#define XGE_HAL_RXDMA_INT_RTI_INT_M            BIT(3)
+
+	u64 rda_err_reg;
+#define XGE_HAL_RDA_RXDn_ECC_SG_ERR		vBIT(0xFF,0,8)
+#define XGE_HAL_RDA_RXDn_ECC_DB_ERR		vBIT(0xFF,8,8)
+#define XGE_HAL_RDA_FRM_ECC_SG_ERR		BIT(23)
+#define XGE_HAL_RDA_FRM_ECC_DB_N_AERR		BIT(31)
+#define XGE_HAL_RDA_SM1_ERR_ALARM		BIT(38)
+#define XGE_HAL_RDA_SM0_ERR_ALARM		BIT(39)
+#define XGE_HAL_RDA_MISC_ERR			BIT(47)
+#define XGE_HAL_RDA_PCIX_ERR			BIT(55)
+#define XGE_HAL_RDA_RXD_ECC_DB_SERR		BIT(63)
+	u64 rda_err_mask;
+	u64 rda_err_alarm;
+
+	u64 rc_err_reg;
+#define XGE_HAL_RC_PRCn_ECC_SG_ERR		vBIT(0xFF,0,8)
+#define XGE_HAL_RC_PRCn_ECC_DB_ERR		vBIT(0xFF,8,8)
+#define XGE_HAL_RC_FTC_ECC_SG_ERR		BIT(23)
+#define XGE_HAL_RC_FTC_ECC_DB_ERR		BIT(31)
+#define XGE_HAL_RC_PRCn_SM_ERR_ALARM		vBIT(0xFF,32,8)
+#define XGE_HAL_RC_FTC_SM_ERR_ALARM		BIT(47)
+#define XGE_HAL_RC_RDA_FAIL_WR_Rn		vBIT(0xFF,48,8)
+	u64 rc_err_mask;
+	u64 rc_err_alarm;
+
+	u64 prc_pcix_err_reg;
+#define XGE_HAL_PRC_PCI_AB_RD_Rn		vBIT(0xFF,0,8)
+#define XGE_HAL_PRC_PCI_DP_RD_Rn		vBIT(0xFF,8,8)
+#define XGE_HAL_PRC_PCI_AB_WR_Rn		vBIT(0xFF,16,8)
+#define XGE_HAL_PRC_PCI_DP_WR_Rn		vBIT(0xFF,24,8)
+#define XGE_HAL_PRC_PCI_AB_F_WR_Rn		vBIT(0xFF,32,8)
+#define XGE_HAL_PRC_PCI_DP_F_WR_Rn		vBIT(0xFF,40,8)
+	u64 prc_pcix_err_mask;
+	u64 prc_pcix_err_alarm;
+
+	u64 rpa_err_reg;
+#define XGE_HAL_RPA_ECC_SG_ERR			BIT(7)
+#define XGE_HAL_RPA_ECC_DB_ERR			BIT(15)
+#define XGE_HAL_RPA_FLUSH_REQUEST		BIT(22)
+#define XGE_HAL_RPA_SM_ERR_ALARM		BIT(23)
+#define XGE_HAL_RPA_CREDIT_ERR			BIT(31)
+	u64 rpa_err_mask;
+	u64 rpa_err_alarm;
+
+	u64 rti_err_reg;
+#define XGE_HAL_RTI_ECC_SG_ERR			BIT(7)
+#define XGE_HAL_RTI_ECC_DB_ERR			BIT(15)
+#define XGE_HAL_RTI_SM_ERR_ALARM		BIT(23)
+	u64 rti_err_mask;
+	u64 rti_err_alarm;
+
+	u8 unused12[0x100 - 0x88];
+
+/* DMA arbiter */
+	u64 rx_queue_priority;
+#define XGE_HAL_RX_QUEUE_0_PRIORITY(val)       vBIT(val,5,3)
+#define XGE_HAL_RX_QUEUE_1_PRIORITY(val)       vBIT(val,13,3)
+#define XGE_HAL_RX_QUEUE_2_PRIORITY(val)       vBIT(val,21,3)
+#define XGE_HAL_RX_QUEUE_3_PRIORITY(val)       vBIT(val,29,3)
+#define XGE_HAL_RX_QUEUE_4_PRIORITY(val)       vBIT(val,37,3)
+#define XGE_HAL_RX_QUEUE_5_PRIORITY(val)       vBIT(val,45,3)
+#define XGE_HAL_RX_QUEUE_6_PRIORITY(val)       vBIT(val,53,3)
+#define XGE_HAL_RX_QUEUE_7_PRIORITY(val)       vBIT(val,61,3)
+
+#define XGE_HAL_RX_QUEUE_PRI_0                 0	/* highest */
+#define XGE_HAL_RX_QUEUE_PRI_1                 1
+#define XGE_HAL_RX_QUEUE_PRI_2                 2
+#define XGE_HAL_RX_QUEUE_PRI_3                 3
+#define XGE_HAL_RX_QUEUE_PRI_4                 4
+#define XGE_HAL_RX_QUEUE_PRI_5                 5
+#define XGE_HAL_RX_QUEUE_PRI_6                 6
+#define XGE_HAL_RX_QUEUE_PRI_7                 7	/* lowest */
+
+	u64 rx_w_round_robin_0;
+	u64 rx_w_round_robin_1;
+	u64 rx_w_round_robin_2;
+	u64 rx_w_round_robin_3;
+	u64 rx_w_round_robin_4;
+
+	/* Per-ring controller regs */
+#define XGE_HAL_RX_MAX_RINGS                8
+	u64 prc_rxd0_n[XGE_HAL_RX_MAX_RINGS];
+	u64 prc_ctrl_n[XGE_HAL_RX_MAX_RINGS];
+#define XGE_HAL_PRC_CTRL_RC_ENABLED                    BIT(7)
+#define XGE_HAL_PRC_CTRL_RING_MODE                     (BIT(14)|BIT(15))
+#define XGE_HAL_PRC_CTRL_RING_MODE_1                   vBIT(0,14,2)
+#define XGE_HAL_PRC_CTRL_RING_MODE_3                   vBIT(1,14,2)
+#define XGE_HAL_PRC_CTRL_RING_MODE_5                   vBIT(2,14,2)
+#define XGE_HAL_PRC_CTRL_RING_MODE_x                   vBIT(3,14,2)
+#define XGE_HAL_PRC_CTRL_NO_SNOOP(n)                   vBIT(n,22,2)
+#define XGE_HAL_PRC_CTRL_RTH_DISABLE                   BIT(31)
+#define XGE_HAL_PRC_CTRL_BIMODAL_INTERRUPT             BIT(37)
+#define XGE_HAL_PRC_CTRL_GROUP_READS                   BIT(38)
+#define XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(val)     vBIT(val,40,24)
+
+	u64 prc_alarm_action;
+#define XGE_HAL_PRC_ALARM_ACTION_RR_R0_STOP            BIT(3)
+#define XGE_HAL_PRC_ALARM_ACTION_RW_R0_STOP            BIT(7)
+#define XGE_HAL_PRC_ALARM_ACTION_RR_R1_STOP            BIT(11)
+#define XGE_HAL_PRC_ALARM_ACTION_RW_R1_STOP            BIT(15)
+#define XGE_HAL_PRC_ALARM_ACTION_RR_R2_STOP            BIT(19)
+#define XGE_HAL_PRC_ALARM_ACTION_RW_R2_STOP            BIT(23)
+#define XGE_HAL_PRC_ALARM_ACTION_RR_R3_STOP            BIT(27)
+#define XGE_HAL_PRC_ALARM_ACTION_RW_R3_STOP            BIT(31)
+#define XGE_HAL_PRC_ALARM_ACTION_RR_R4_STOP            BIT(35)
+#define XGE_HAL_PRC_ALARM_ACTION_RW_R4_STOP            BIT(39)
+#define XGE_HAL_PRC_ALARM_ACTION_RR_R5_STOP            BIT(43)
+#define XGE_HAL_PRC_ALARM_ACTION_RW_R5_STOP            BIT(47)
+#define XGE_HAL_PRC_ALARM_ACTION_RR_R6_STOP            BIT(51)
+#define XGE_HAL_PRC_ALARM_ACTION_RW_R6_STOP            BIT(55)
+#define XGE_HAL_PRC_ALARM_ACTION_RR_R7_STOP            BIT(59)
+#define XGE_HAL_PRC_ALARM_ACTION_RW_R7_STOP            BIT(63)
+
+/* Receive traffic interrupts */
+	u64 rti_command_mem;
+#define XGE_HAL_RTI_CMD_MEM_WE                          BIT(7)
+#define XGE_HAL_RTI_CMD_MEM_STROBE                      BIT(15)
+#define XGE_HAL_RTI_CMD_MEM_STROBE_NEW_CMD              BIT(15)
+#define XGE_HAL_RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED   BIT(15)
+#define XGE_HAL_RTI_CMD_MEM_OFFSET(n)                   vBIT(n,29,3)
+
+	u64 rti_data1_mem;
+#define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_VAL(n)      vBIT(n,3,29)
+#define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_AC_EN       BIT(38)
+#define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_CI_EN       BIT(39)
+#define XGE_HAL_RTI_DATA1_MEM_RX_URNG_A(n)         vBIT(n,41,7)
+#define XGE_HAL_RTI_DATA1_MEM_RX_URNG_B(n)         vBIT(n,49,7)
+#define XGE_HAL_RTI_DATA1_MEM_RX_URNG_C(n)         vBIT(n,57,7)
+
+	u64 rti_data2_mem;
+#define XGE_HAL_RTI_DATA2_MEM_RX_UFC_A(n)          vBIT(n,0,16)
+#define XGE_HAL_RTI_DATA2_MEM_RX_UFC_B(n)          vBIT(n,16,16)
+#define XGE_HAL_RTI_DATA2_MEM_RX_UFC_C(n)          vBIT(n,32,16)
+#define XGE_HAL_RTI_DATA2_MEM_RX_UFC_D(n)          vBIT(n,48,16)
+
+	u64 rx_pa_cfg;
+#define XGE_HAL_RX_PA_CFG_IGNORE_FRM_ERR           BIT(1)
+#define XGE_HAL_RX_PA_CFG_IGNORE_SNAP_OUI          BIT(2)
+#define XGE_HAL_RX_PA_CFG_IGNORE_LLC_CTRL          BIT(3)
+#define XGE_HAL_RX_PA_CFG_SCATTER_MODE(n)          vBIT(n,6,1)
+#define XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(n)   vBIT(n,15,1)
+
+	u8 unused13_0[0x8];
+
+	u64 ring_bump_counter1;
+	u64 ring_bump_counter2;
+#define XGE_HAL_RING_BUMP_CNT(i, val) (u16)(val >> (48 - (16 * (i % 4))))
+
+	u8 unused13[0x700 - 0x1f0];
+
+	u64 rxdma_debug_ctrl;
+
+	u8 unused14[0x2000 - 0x1f08];
+
+/* Media Access Controller Register */
+	u64 mac_int_status;
+	u64 mac_int_mask;
+#define XGE_HAL_MAC_INT_STATUS_TMAC_INT            BIT(0)
+#define XGE_HAL_MAC_INT_STATUS_RMAC_INT            BIT(1)
+
+	u64 mac_tmac_err_reg;
+#define XGE_HAL_TMAC_ECC_DB_ERR			BIT(15) 
+#define XGE_HAL_TMAC_TX_BUF_OVRN		BIT(23)
+#define XGE_HAL_TMAC_TX_CRI_ERR		   	BIT(31)
+#define XGE_HAL_TMAC_TX_SM_ERR			BIT(39)
+	u64 mac_tmac_err_mask;
+	u64 mac_tmac_err_alarm;
+
+	u64 mac_rmac_err_reg;
+#define XGE_HAL_RMAC_RX_BUFF_OVRN		BIT(0)
+#define XGE_HAL_RMAC_RTH_SPDM_ECC_SG_ERR	BIT(0)
+#define XGE_HAL_RMAC_RTS_ECC_DB_ERR		BIT(0)
+#define XGE_HAL_RMAC_ECC_DB_ERR			BIT(0)
+#define XGE_HAL_RMAC_RTH_SPDM_ECC_DB_ERR	BIT(0)
+#define XGE_HAL_RMAC_LINK_STATE_CHANGE_INT	BIT(0)
+#define XGE_HAL_RMAC_RX_SM_ERR			BIT(39)
+	u64 mac_rmac_err_mask;
+	u64 mac_rmac_err_alarm;
+
+	u8 unused15[0x100 - 0x40];
+
+	u64 mac_cfg;
+#define XGE_HAL_MAC_CFG_TMAC_ENABLE             BIT(0)
+#define XGE_HAL_MAC_CFG_RMAC_ENABLE             BIT(1)
+#define XGE_HAL_MAC_CFG_LAN_NOT_WAN             BIT(2)
+#define XGE_HAL_MAC_CFG_TMAC_LOOPBACK           BIT(3)
+#define XGE_HAL_MAC_CFG_TMAC_APPEND_PAD         BIT(4)
+#define XGE_HAL_MAC_CFG_RMAC_STRIP_FCS          BIT(5)
+#define XGE_HAL_MAC_CFG_RMAC_STRIP_PAD          BIT(6)
+#define XGE_HAL_MAC_CFG_RMAC_PROM_ENABLE        BIT(7)
+#define XGE_HAL_MAC_RMAC_DISCARD_PFRM           BIT(8)
+#define XGE_HAL_MAC_RMAC_BCAST_ENABLE           BIT(9)
+#define XGE_HAL_MAC_RMAC_ALL_ADDR_ENABLE        BIT(10)
+#define XGE_HAL_MAC_RMAC_INVLD_IPG_THR(val)     vBIT(val,16,8)
+
+	u64 tmac_avg_ipg;
+#define XGE_HAL_TMAC_AVG_IPG(val)           vBIT(val,0,8)
+
+	u64 rmac_max_pyld_len;
+#define XGE_HAL_RMAC_MAX_PYLD_LEN(val)      vBIT(val,2,14)
+
+	u64 rmac_err_cfg;
+#define XGE_HAL_RMAC_ERR_FCS                    BIT(0)
+#define XGE_HAL_RMAC_ERR_FCS_ACCEPT             BIT(1)
+#define XGE_HAL_RMAC_ERR_TOO_LONG               BIT(1)
+#define XGE_HAL_RMAC_ERR_TOO_LONG_ACCEPT        BIT(1)
+#define XGE_HAL_RMAC_ERR_RUNT                   BIT(2)
+#define XGE_HAL_RMAC_ERR_RUNT_ACCEPT            BIT(2)
+#define XGE_HAL_RMAC_ERR_LEN_MISMATCH           BIT(3)
+#define XGE_HAL_RMAC_ERR_LEN_MISMATCH_ACCEPT    BIT(3)
+
+	u64 rmac_cfg_key;
+#define XGE_HAL_RMAC_CFG_KEY(val)               vBIT(val,0,16)
+
+#define XGE_HAL_MAX_MAC_ADDRESSES               64
+#define XGE_HAL_MAC_MC_ALL_MC_ADDR_OFFSET       63
+#define XGE_HAL_MAX_MAC_ADDRESSES_HERC          256
+#define XGE_HAL_MAC_MC_ALL_MC_ADDR_OFFSET_HERC  255
+
+	u64 rmac_addr_cmd_mem;
+#define XGE_HAL_RMAC_ADDR_CMD_MEM_WE                    BIT(7)
+#define XGE_HAL_RMAC_ADDR_CMD_MEM_RD                    0
+#define XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD        BIT(15)
+#define XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING  BIT(15)
+#define XGE_HAL_RMAC_ADDR_CMD_MEM_OFFSET(n)             vBIT(n,26,6)
+
+	u64 rmac_addr_data0_mem;
+#define XGE_HAL_RMAC_ADDR_DATA0_MEM_ADDR(n)    vBIT(n,0,48)
+#define XGE_HAL_RMAC_ADDR_DATA0_MEM_USER       BIT(48)
+
+	u64 rmac_addr_data1_mem;
+#define XGE_HAL_RMAC_ADDR_DATA1_MEM_MASK(n)    vBIT(n,0,48)
+
+	u8 unused16[0x8];
+
+/*
+        u64 rmac_addr_cfg;
+#define XGE_HAL_RMAC_ADDR_UCASTn_EN(n)     mBIT(0)_n(n)
+#define XGE_HAL_RMAC_ADDR_MCASTn_EN(n)     mBIT(0)_n(n)
+#define XGE_HAL_RMAC_ADDR_BCAST_EN         vBIT(0)_48
+#define XGE_HAL_RMAC_ADDR_ALL_ADDR_EN      vBIT(0)_49
+*/
+	u64 tmac_ipg_cfg;
+
+	u64 rmac_pause_cfg;
+#define XGE_HAL_RMAC_PAUSE_GEN_EN          BIT(0)
+#define XGE_HAL_RMAC_PAUSE_RCV_EN          BIT(1)
+#define XGE_HAL_RMAC_PAUSE_HG_PTIME_DEF    vBIT(0xFFFF,16,16)
+#define XGE_HAL_RMAC_PAUSE_HG_PTIME(val)    vBIT(val,16,16)
+
+	u64 rmac_red_cfg;
+
+	u64 rmac_red_rate_q0q3;
+	u64 rmac_red_rate_q4q7;
+
+	u64 mac_link_util;
+#define XGE_HAL_MAC_TX_LINK_UTIL           vBIT(0xFE,1,7)
+#define XGE_HAL_MAC_TX_LINK_UTIL_DISABLE   vBIT(0xF, 8,4)
+#define XGE_HAL_MAC_TX_LINK_UTIL_VAL( n )  vBIT(n,8,4)
+#define XGE_HAL_MAC_RX_LINK_UTIL           vBIT(0xFE,33,7)
+#define XGE_HAL_MAC_RX_LINK_UTIL_DISABLE   vBIT(0xF,40,4)
+#define XGE_HAL_MAC_RX_LINK_UTIL_VAL( n )  vBIT(n,40,4)
+
+#define XGE_HAL_MAC_LINK_UTIL_DISABLE (XGE_HAL_MAC_TX_LINK_UTIL_DISABLE | \
+				       XGE_HAL_MAC_RX_LINK_UTIL_DISABLE)
+
+	u64 rmac_invalid_ipg;
+
+/* rx traffic steering */
+#define XGE_HAL_MAC_RTS_FRM_LEN_SET(len)	vBIT(len,2,14)
+	u64 rts_frm_len_n[8];
+
+	u64 rts_qos_steering;
+
+#define XGE_HAL_MAX_DIX_MAP                         4
+	u64 rts_dix_map_n[XGE_HAL_MAX_DIX_MAP];
+#define XGE_HAL_RTS_DIX_MAP_ETYPE(val)             vBIT(val,0,16)
+#define XGE_HAL_RTS_DIX_MAP_SCW(val)               BIT(val,21)
+
+	u64 rts_q_alternates;
+	u64 rts_default_q;
+#define XGE_HAL_RTS_DEFAULT_Q(n)		   vBIT(n,5,3)
+
+	u64 rts_ctrl;
+#define XGE_HAL_RTS_CTRL_IGNORE_SNAP_OUI           BIT(2)
+#define XGE_HAL_RTS_CTRL_IGNORE_LLC_CTRL           BIT(3)
+#define XGE_HAL_RTS_CTRL_ENHANCED_MODE		   BIT(7)
+
+	u64 rts_pn_cam_ctrl;
+#define XGE_HAL_RTS_PN_CAM_CTRL_WE                 BIT(7)
+#define XGE_HAL_RTS_PN_CAM_CTRL_STROBE_NEW_CMD     BIT(15)
+#define XGE_HAL_RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED   BIT(15)
+#define XGE_HAL_RTS_PN_CAM_CTRL_OFFSET(n)          vBIT(n,24,8)
+	u64 rts_pn_cam_data;
+#define XGE_HAL_RTS_PN_CAM_DATA_TCP_SELECT         BIT(7)
+#define XGE_HAL_RTS_PN_CAM_DATA_PORT(val)          vBIT(val,8,16)
+#define XGE_HAL_RTS_PN_CAM_DATA_SCW(val)           vBIT(val,24,8)
+
+	u64 rts_ds_mem_ctrl;
+#define XGE_HAL_RTS_DS_MEM_CTRL_WE                 BIT(7)
+#define XGE_HAL_RTS_DS_MEM_CTRL_STROBE_NEW_CMD     BIT(15)
+#define XGE_HAL_RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED   BIT(15)
+#define XGE_HAL_RTS_DS_MEM_CTRL_OFFSET(n)          vBIT(n,26,6)
+	u64 rts_ds_mem_data;
+#define XGE_HAL_RTS_DS_MEM_DATA(n)                 vBIT(n,0,8)
+
+	u8  unused16_1[0x308 - 0x220];
+	
+	u64 rts_vid_mem_ctrl;
+	u64 rts_vid_mem_data;
+	u64 rts_p0_p3_map;
+	u64 rts_p4_p7_map;
+	u64 rts_p8_p11_map;
+	u64 rts_p12_p15_map;
+
+	u64 rts_mac_cfg;
+#define XGE_HAL_RTS_MAC_SECT0_EN                    BIT(0)
+#define XGE_HAL_RTS_MAC_SECT1_EN                    BIT(1)
+#define XGE_HAL_RTS_MAC_SECT2_EN                    BIT(2)
+#define XGE_HAL_RTS_MAC_SECT3_EN                    BIT(3)
+#define XGE_HAL_RTS_MAC_SECT4_EN                    BIT(4)
+#define XGE_HAL_RTS_MAC_SECT5_EN                    BIT(5)
+#define XGE_HAL_RTS_MAC_SECT6_EN                    BIT(6)
+#define XGE_HAL_RTS_MAC_SECT7_EN                    BIT(7)
+
+	u8 unused16_2[0x380 - 0x340];
+
+	u64 rts_rth_cfg;
+#define XGE_HAL_RTS_RTH_EN                         BIT(3)
+#define XGE_HAL_RTS_RTH_BUCKET_SIZE(n)             vBIT(n,4,4)
+#define XGE_HAL_RTS_RTH_ALG_SEL_MS                 BIT(11)
+#define XGE_HAL_RTS_RTH_TCP_IPV4_EN                BIT(15)
+#define XGE_HAL_RTS_RTH_UDP_IPV4_EN                BIT(19)
+#define XGE_HAL_RTS_RTH_IPV4_EN                    BIT(23)
+#define XGE_HAL_RTS_RTH_TCP_IPV6_EN                BIT(27)
+#define XGE_HAL_RTS_RTH_UDP_IPV6_EN                BIT(31)
+#define XGE_HAL_RTS_RTH_IPV6_EN                    BIT(35)
+#define XGE_HAL_RTS_RTH_TCP_IPV6_EX_EN             BIT(39)
+#define XGE_HAL_RTS_RTH_UDP_IPV6_EX_EN             BIT(43)
+#define XGE_HAL_RTS_RTH_IPV6_EX_EN                 BIT(47)
+
+	u64 rts_rth_map_mem_ctrl;
+#define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_WE            BIT(7)
+#define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_STROBE        BIT(15)
+#define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_OFFSET(n)     vBIT(n,24,8)
+
+	u64 rts_rth_map_mem_data;
+#define XGE_HAL_RTS_RTH_MAP_MEM_DATA_ENTRY_EN      BIT(3)
+#define XGE_HAL_RTS_RTH_MAP_MEM_DATA(n)            vBIT(n,5,3)
+
+	u64 rts_rth_spdm_mem_ctrl;
+#define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_STROBE       BIT(15)
+#define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_LINE_SEL(n)  vBIT(n,21,3)
+#define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_OFFSET(n)    vBIT(n,24,8)
+
+	u64 rts_rth_spdm_mem_data;
+
+	u64 rts_rth_jhash_cfg;
+#define XGE_HAL_RTS_RTH_JHASH_GOLDEN(n)            vBIT(n,0,32)
+#define XGE_HAL_RTS_RTH_JHASH_INIT_VAL(n)          vBIT(n,32,32)
+
+	u64 rts_rth_hash_mask[5]; /* rth mask's 0...4 */
+	u64 rts_rth_hash_mask_5;
+#define XGE_HAL_RTH_HASH_MASK_5(n)                 vBIT(n,0,32)
+
+	u64 rts_rth_status;
+#define XGE_HAL_RTH_STATUS_SPDM_USE_L4             BIT(3)
+
+	u8  unused17[0x400 - 0x3E8];
+	
+	u64 rmac_red_fine_q0q3;
+	u64 rmac_red_fine_q4q7;    
+	u64 rmac_pthresh_cross;
+	u64 rmac_rthresh_cross;
+	u64 rmac_pnum_range[32];
+
+	u64 rmac_mp_crc_0;
+	u64 rmac_mp_mask_a_0;
+	u64 rmac_mp_mask_b_0;
+	
+	u64 rmac_mp_crc_1;
+	u64 rmac_mp_mask_a_1;
+	u64 rmac_mp_mask_b_1;
+	
+	u64 rmac_mp_crc_2;
+	u64 rmac_mp_mask_a_2;
+	u64 rmac_mp_mask_b_2;
+	
+	u64 rmac_mp_crc_3;
+	u64 rmac_mp_mask_a_3;
+	u64 rmac_mp_mask_b_3;
+	
+	u64 rmac_mp_crc_4;
+	u64 rmac_mp_mask_a_4;
+	u64 rmac_mp_mask_b_4;
+	
+	u64 rmac_mp_crc_5;
+	u64 rmac_mp_mask_a_5;
+	u64 rmac_mp_mask_b_5;
+	
+	u64 rmac_mp_crc_6;
+	u64 rmac_mp_mask_a_6;
+	u64 rmac_mp_mask_b_6;
+
+	u64 rmac_mp_crc_7;
+	u64 rmac_mp_mask_a_7;
+	u64 rmac_mp_mask_b_7;
+
+	u64 mac_ctrl;
+	u64 activity_control;
+	
+	u8  unused17_2[0x700 - 0x5F0];
+
+	u64 mac_debug_ctrl;
+#define XGE_HAL_MAC_DBG_ACTIVITY_VALUE		   0x411040400000000ULL
+
+	u8 unused18[0x2800 - 0x2708];
+
+/* memory controller registers */
+	u64 mc_int_status;
+#define XGE_HAL_MC_INT_STATUS_MC_INT               BIT(0)
+	u64 mc_int_mask;
+#define XGE_HAL_MC_INT_MASK_MC_INT                 BIT(0)
+
+	u64 mc_err_reg;
+#define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_L        BIT(2) /* non-Xena */
+#define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_U        BIT(3) /* non-Xena */
+#define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_L        BIT(4) /* non-Xena */
+#define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_U        BIT(5) /* non-Xena */
+#define XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_L        BIT(6)
+#define XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_U        BIT(7)
+#define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_L        BIT(10) /* non-Xena */
+#define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_U        BIT(11) /* non-Xena */
+#define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_L        BIT(12) /* non-Xena */
+#define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_U        BIT(13) /* non-Xena */
+#define XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_L        BIT(14)
+#define XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_U        BIT(15)
+#define XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_0       BIT(17)
+#define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_0       BIT(18) /* Xena: reset */
+#define XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_1       BIT(19)
+#define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_1       BIT(20) /* Xena: reset */
+#define XGE_HAL_MC_ERR_REG_MIRI_CRI_ERR_0          BIT(22)
+#define XGE_HAL_MC_ERR_REG_MIRI_CRI_ERR_1          BIT(23)
+#define XGE_HAL_MC_ERR_REG_SM_ERR                  BIT(31)
+#define XGE_HAL_MC_ERR_REG_PL_LOCK_N               BIT(39)
+
+	u64 mc_err_mask;
+	u64 mc_err_alarm;
+
+	u8 unused19[0x100 - 0x28];
+
+/* MC configuration */
+	u64 rx_queue_cfg;
+#define XGE_HAL_RX_QUEUE_CFG_Q0_SZ(n)              vBIT(n,0,8)
+#define XGE_HAL_RX_QUEUE_CFG_Q1_SZ(n)              vBIT(n,8,8)
+#define XGE_HAL_RX_QUEUE_CFG_Q2_SZ(n)              vBIT(n,16,8)
+#define XGE_HAL_RX_QUEUE_CFG_Q3_SZ(n)              vBIT(n,24,8)
+#define XGE_HAL_RX_QUEUE_CFG_Q4_SZ(n)              vBIT(n,32,8)
+#define XGE_HAL_RX_QUEUE_CFG_Q5_SZ(n)              vBIT(n,40,8)
+#define XGE_HAL_RX_QUEUE_CFG_Q6_SZ(n)              vBIT(n,48,8)
+#define XGE_HAL_RX_QUEUE_CFG_Q7_SZ(n)              vBIT(n,56,8)
+
+	u64 mc_rldram_mrs;
+#define XGE_HAL_MC_RLDRAM_QUEUE_SIZE_ENABLE	BIT(39)
+#define XGE_HAL_MC_RLDRAM_MRS_ENABLE		BIT(47)
+
+	u64 mc_rldram_interleave;
+
+	u64 mc_pause_thresh_q0q3;
+	u64 mc_pause_thresh_q4q7;
+
+	u64 mc_red_thresh_q[8];
+
+	u8 unused20[0x200 - 0x168];
+	u64 mc_rldram_ref_per;
+	u8 unused21[0x220 - 0x208];
+	u64 mc_rldram_test_ctrl;
+#define XGE_HAL_MC_RLDRAM_TEST_MODE		BIT(47)
+#define XGE_HAL_MC_RLDRAM_TEST_WRITE		BIT(7)
+#define XGE_HAL_MC_RLDRAM_TEST_GO		BIT(15)
+#define XGE_HAL_MC_RLDRAM_TEST_DONE		BIT(23)
+#define XGE_HAL_MC_RLDRAM_TEST_PASS		BIT(31)
+
+	u8 unused22[0x240 - 0x228];
+	u64 mc_rldram_test_add;
+	u8 unused23[0x260 - 0x248];
+	u64 mc_rldram_test_d0;
+	u8 unused24[0x280 - 0x268];
+	u64 mc_rldram_test_d1;
+	u8 unused25[0x300 - 0x288];
+	u64 mc_rldram_test_d2;
+	u8  unused26_1[0x2C00 - 0x2B08];
+	u64 mc_rldram_test_read_d0;
+	u8  unused26_2[0x20 - 0x8];
+	u64 mc_rldram_test_read_d1;
+	u8  unused26_3[0x40 - 0x28];
+	u64 mc_rldram_test_read_d2;
+	u8  unused26_4[0x60 - 0x48];
+	u64 mc_rldram_test_add_bkg;
+	u8  unused26_5[0x80 - 0x68];
+	u64 mc_rldram_test_d0_bkg;
+	u8  unused26_6[0xD00 - 0xC88];    
+	u64 mc_rldram_test_d1_bkg;
+	u8  unused26_7[0x20 - 0x8];
+	u64 mc_rldram_test_d2_bkg;
+	u8  unused26_8[0x40 - 0x28];
+	u64 mc_rldram_test_read_d0_bkg;
+	u8  unused26_9[0x60 - 0x48];
+	u64 mc_rldram_test_read_d1_bkg;
+	u8  unused26_10[0x80 - 0x68];
+	u64 mc_rldram_test_read_d2_bkg;
+	u8  unused26_11[0xE00 - 0xD88];
+	u64 mc_rldram_generation;
+	u8  unused26_12[0x20 - 0x8];
+	u64 mc_driver;
+	u8  unused26_13[0x40 - 0x28];
+	u64 mc_rldram_ref_per_herc;
+#define XGE_HAL_MC_RLDRAM_SET_REF_PERIOD(n)   vBIT(n, 0, 16)
+	u8 unused26_14[0x660 - 0x648];
+	u64 mc_rldram_mrs_herc;
+#define XGE_HAL_MC_RLDRAM_MRS(n)              vBIT(n, 14, 17)
+	u8 unused26_15[0x700 - 0x668];
+	u64 mc_debug_ctrl;
+
+	u8 unused27[0x3000 - 0x2f08];
+
+/* XGXG */
+	/* XGXS control registers */
+
+	u64 xgxs_int_status;
+#define XGE_HAL_XGXS_INT_STATUS_TXGXS              BIT(0)
+#define XGE_HAL_XGXS_INT_STATUS_RXGXS              BIT(1)
+	u64 xgxs_int_mask;
+#define XGE_HAL_XGXS_INT_MASK_TXGXS                BIT(0)
+#define XGE_HAL_XGXS_INT_MASK_RXGXS                BIT(1)
+
+	u64 xgxs_txgxs_err_reg;
+#define XGE_HAL_TXGXS_ECC_SG_ERR			BIT(7)
+#define XGE_HAL_TXGXS_ECC_DB_ERR			BIT(15)
+#define XGE_HAL_TXGXS_ESTORE_UFLOW			BIT(31)
+#define XGE_HAL_TXGXS_TX_SM_ERR				BIT(39)
+	u64 xgxs_txgxs_err_mask;
+	u64 xgxs_txgxs_err_alarm;
+
+	u64 xgxs_rxgxs_err_reg;
+#define XGE_HAL_RXGXS_ESTORE_OFLOW			BIT(7)
+#define XGE_HAL_RXGXS_RX_SM_ERR				BIT(39)
+	u64 xgxs_rxgxs_err_mask;
+	u64 xgxs_rxgxs_err_alarm;
+
+	u64 spi_err_reg;
+	u64 spi_err_mask;
+	u64 spi_err_alarm;
+
+	u8 unused28[0x100 - 0x58];
+
+	u64 xgxs_cfg;
+	u64 xgxs_status;
+
+	u64 xgxs_cfg_key;
+	u64 xgxs_efifo_cfg; /* CHANGED */
+	u64 rxgxs_ber_0;    /* CHANGED */
+	u64 rxgxs_ber_1;    /* CHANGED */
+	
+	u64 spi_control;
+	u64 spi_data;
+	u64 spi_write_protect;
+	
+	u8  unused29[0x80 - 0x48];
+	
+	u64 xgxs_cfg_1;
+} xge_hal_pci_bar0_t;
+
+/* Using this strcture to calculate offsets */
+typedef struct xge_hal_pci_config_le_t {
+    u16     vendor_id;              // 0x00
+    u16     device_id;              // 0x02
+
+    u16     command;                // 0x04
+    u16     status;                 // 0x06
+
+    u8      revision;               // 0x08
+    u8      pciClass[3];            // 0x09
+
+    u8      cache_line_size;        // 0x0c
+    u8      latency_timer;          // 0x0d
+    u8      header_type;            // 0x0e
+    u8      bist;                   // 0x0f
+
+    u32     base_addr0_lo;          // 0x10
+    u32     base_addr0_hi;          // 0x14
+
+    u32     base_addr1_lo;          // 0x18
+    u32     base_addr1_hi;          // 0x1C
+
+    u32     not_Implemented1;       // 0x20
+    u32     not_Implemented2;       // 0x24
+
+    u32     cardbus_cis_pointer;    // 0x28
+
+    u16     subsystem_vendor_id;    // 0x2c
+    u16     subsystem_id;           // 0x2e
+
+    u32     rom_base;               // 0x30
+    u8      capabilities_pointer;   // 0x34
+    u8      rsvd_35[3];             // 0x35
+    u32     rsvd_38;                // 0x38
+
+    u8      interrupt_line;         // 0x3c
+    u8      interrupt_pin;          // 0x3d
+    u8      min_grant;              // 0x3e
+    u8      max_latency;            // 0x3f
+
+    u8      msi_cap_id;             // 0x40
+    u8      msi_next_ptr;           // 0x41
+    u16     msi_control;            // 0x42
+    u32     msi_lower_address;      // 0x44
+    u32     msi_higher_address;     // 0x48
+    u16     msi_data;               // 0x4c
+    u16     msi_unused;             // 0x4e
+
+    u8      vpd_cap_id;             // 0x50
+    u8      vpd_next_cap;           // 0x51
+    u16     vpd_addr;               // 0x52
+    u32     vpd_data;               // 0x54
+
+    u8      rsvd_b0[8];             // 0x58
+
+    u8      pcix_cap;               // 0x60
+    u8      pcix_next_cap;          // 0x61
+    u16     pcix_command;           // 0x62
+
+    u32     pcix_status;            // 0x64
+
+    u8      rsvd_b1[XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE-0x68];
+} xge_hal_pci_config_le_t;              // 0x100
+
+typedef struct xge_hal_pci_config_t {
+#ifdef XGE_OS_HOST_BIG_ENDIAN
+    u16     device_id;              // 0x02
+    u16     vendor_id;              // 0x00
+
+    u16     status;                 // 0x06
+    u16     command;                // 0x04
+
+    u8      pciClass[3];            // 0x09
+    u8      revision;               // 0x08
+
+    u8      bist;                   // 0x0f
+    u8      header_type;            // 0x0e
+    u8      latency_timer;          // 0x0d
+    u8      cache_line_size;        // 0x0c
+
+    u32     base_addr0_lo;           // 0x10
+    u32     base_addr0_hi;           // 0x14
+
+    u32     base_addr1_lo;          // 0x18
+    u32     base_addr1_hi;          // 0x1C
+
+    u32     not_Implemented1;       // 0x20
+    u32     not_Implemented2;       // 0x24
+
+    u32     cardbus_cis_pointer;    // 0x28
+
+    u16     subsystem_id;           // 0x2e
+    u16     subsystem_vendor_id;    // 0x2c
+
+    u32     rom_base;               // 0x30
+    u8      rsvd_35[3];             // 0x35
+    u8      capabilities_pointer;   // 0x34
+    u32     rsvd_38;                // 0x38
+
+    u8      max_latency;            // 0x3f
+    u8      min_grant;              // 0x3e
+    u8      interrupt_pin;          // 0x3d
+    u8      interrupt_line;         // 0x3c
+
+    u16     msi_control;            // 0x42
+    u8      msi_next_ptr;           // 0x41
+    u8      msi_cap_id;             // 0x40
+    u32     msi_lower_address;      // 0x44
+    u32     msi_higher_address;     // 0x48
+    u16     msi_unused;             // 0x4e
+    u16     msi_data;               // 0x4c
+
+    u16     vpd_addr;               // 0x52
+    u8      vpd_next_cap;           // 0x51
+    u8      vpd_cap_id;             // 0x50
+    u32     vpd_data;               // 0x54
+
+    u8      rsvd_b0[8];             // 0x58
+
+    u16     pcix_command;           // 0x62
+    u8      pcix_next_cap;          // 0x61
+    u8      pcix_cap;               // 0x60
+
+    u32     pcix_status;            // 0x64
+#else
+    u16     vendor_id;              // 0x00
+    u16     device_id;              // 0x02
+
+    u16     command;                // 0x04
+    u16     status;                 // 0x06
+
+    u8      revision;               // 0x08
+    u8      pciClass[3];            // 0x09
+
+    u8      cache_line_size;        // 0x0c
+    u8      latency_timer;          // 0x0d
+    u8      header_type;            // 0x0e
+    u8      bist;                   // 0x0f
+
+    u32     base_addr0_lo;          // 0x10
+    u32     base_addr0_hi;          // 0x14
+
+    u32     base_addr1_lo;          // 0x18
+    u32     base_addr1_hi;          // 0x1C
+
+    u32     not_Implemented1;       // 0x20
+    u32     not_Implemented2;       // 0x24
+
+    u32     cardbus_cis_pointer;    // 0x28
+
+    u16     subsystem_vendor_id;    // 0x2c
+    u16     subsystem_id;           // 0x2e
+
+    u32     rom_base;               // 0x30
+    u8      capabilities_pointer;   // 0x34
+    u8      rsvd_35[3];             // 0x35
+    u32     rsvd_38;                // 0x38
+
+    u8      interrupt_line;         // 0x3c
+    u8      interrupt_pin;          // 0x3d
+    u8      min_grant;              // 0x3e
+    u8      max_latency;            // 0x3f
+
+    u8      msi_cap_id;             // 0x40
+    u8      msi_next_ptr;           // 0x41
+    u16     msi_control;            // 0x42
+    u32     msi_lower_address;      // 0x44
+    u32     msi_higher_address;     // 0x48
+    u16     msi_data;               // 0x4c
+    u16     msi_unused;             // 0x4e
+
+    u8      vpd_cap_id;             // 0x50
+    u8      vpd_next_cap;           // 0x51
+    u16     vpd_addr;               // 0x52
+    u32     vpd_data;               // 0x54
+
+    u8      rsvd_b0[8];             // 0x58
+
+    u8      pcix_cap;               // 0x60
+    u8      pcix_next_cap;          // 0x61
+    u16     pcix_command;           // 0x62
+
+    u32     pcix_status;            // 0x64
+
+#endif
+    u8      rsvd_b1[XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE-0x68];
+} xge_hal_pci_config_t;               // 0x100
+
+#define XGE_HAL_REG_SPACE	sizeof(xge_hal_pci_bar0_t)
+#define XGE_HAL_EEPROM_SIZE	(0x01 << 11)
+
+#endif /* XGE_HAL_REGS_H */
diff --git a/sys/dev/nxge/include/xgehal-ring.h b/sys/dev/nxge/include/xgehal-ring.h
new file mode 100644
index 0000000..c3efdf0
--- /dev/null
+++ b/sys/dev/nxge/include/xgehal-ring.h
@@ -0,0 +1,473 @@
+/*-
+ * Copyright (c) 2002-2007 Neterion, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ *  FileName :    xgehal-ring.h
+ *
+ *  Description:  HAL Rx ring object functionality
+ *
+ *  Created:      19 May 2004
+ */
+
+#ifndef XGE_HAL_RING_H
+#define XGE_HAL_RING_H
+
+#include <dev/nxge/include/xgehal-channel.h>
+#include <dev/nxge/include/xgehal-config.h>
+#include <dev/nxge/include/xgehal-mm.h>
+
+__EXTERN_BEGIN_DECLS
+
+/* HW ring configuration */
+#define XGE_HAL_RING_RXDBLOCK_SIZE	0x1000
+
+#define XGE_HAL_RXD_T_CODE_OK		0x0
+#define XGE_HAL_RXD_T_CODE_PARITY	0x1
+#define XGE_HAL_RXD_T_CODE_ABORT	0x2
+#define XGE_HAL_RXD_T_CODE_PARITY_ABORT	0x3
+#define XGE_HAL_RXD_T_CODE_RDA_FAILURE	0x4
+#define XGE_HAL_RXD_T_CODE_UNKNOWN_PROTO 0x5
+#define XGE_HAL_RXD_T_CODE_BAD_FCS	0x6
+#define XGE_HAL_RXD_T_CODE_BUFF_SIZE	0x7
+#define XGE_HAL_RXD_T_CODE_BAD_ECC	0x8
+#define XGE_HAL_RXD_T_CODE_UNUSED_C	0xC
+#define XGE_HAL_RXD_T_CODE_UNKNOWN	0xF
+
+#define XGE_HAL_RING_USE_MTU		-1
+
+/* control_1 and control_2 formatting - same for all buffer modes */
+#define XGE_HAL_RXD_GET_L3_CKSUM(control_1) ((u16)(control_1>>16) & 0xFFFF)
+#define XGE_HAL_RXD_GET_L4_CKSUM(control_1) ((u16)(control_1 & 0xFFFF))
+
+#define XGE_HAL_RXD_MASK_VLAN_TAG		vBIT(0xFFFF,48,16)
+#define XGE_HAL_RXD_SET_VLAN_TAG(control_2, val) control_2 |= (u16)val
+#define XGE_HAL_RXD_GET_VLAN_TAG(control_2)	((u16)(control_2 & 0xFFFF))
+
+#define XGE_HAL_RXD_POSTED_4_XFRAME		BIT(7)  /* control_1 */
+#define XGE_HAL_RXD_NOT_COMPLETED               BIT(0)  /* control_2 */
+#define XGE_HAL_RXD_T_CODE		(BIT(12)|BIT(13)|BIT(14)|BIT(15))
+#define XGE_HAL_RXD_GET_T_CODE(control_1)	\
+				((control_1 & XGE_HAL_RXD_T_CODE)>>48)
+#define XGE_HAL_RXD_SET_T_CODE(control_1, val) \
+				(control_1 |= (((u64)val & 0xF) << 48))
+
+#define XGE_HAL_RXD_MASK_FRAME_TYPE		vBIT(0x3,25,2)
+#define XGE_HAL_RXD_MASK_FRAME_PROTO		vBIT(0xFFFF,24,8)
+#define XGE_HAL_RXD_GET_FRAME_TYPE(control_1)	\
+		(u8)(0x3 & ((control_1 & XGE_HAL_RXD_MASK_FRAME_TYPE) >> 37))
+#define XGE_HAL_RXD_GET_FRAME_PROTO(control_1)	\
+			(u8)((control_1 & XGE_HAL_RXD_MASK_FRAME_PROTO) >> 32)
+#define XGE_HAL_RXD_FRAME_PROTO_VLAN_TAGGED	BIT(24)
+#define XGE_HAL_RXD_FRAME_PROTO_IPV4		BIT(27)
+#define XGE_HAL_RXD_FRAME_PROTO_IPV6		BIT(28)
+#define XGE_HAL_RXD_FRAME_PROTO_IP_FRAGMENTED	BIT(29)
+#define XGE_HAL_RXD_FRAME_PROTO_TCP		BIT(30)
+#define XGE_HAL_RXD_FRAME_PROTO_UDP		BIT(31)
+#define XGE_HAL_RXD_FRAME_TCP_OR_UDP (XGE_HAL_RXD_FRAME_PROTO_TCP | \
+				XGE_HAL_RXD_FRAME_PROTO_UDP)
+
+/**
+ * enum xge_hal_frame_type_e - Ethernet frame format.
+ * @XGE_HAL_FRAME_TYPE_DIX: DIX (Ethernet II) format.
+ * @XGE_HAL_FRAME_TYPE_LLC: LLC format.
+ * @XGE_HAL_FRAME_TYPE_SNAP: SNAP format.
+ * @XGE_HAL_FRAME_TYPE_IPX: IPX format.
+ *
+ * Ethernet frame format.
+ */
+typedef enum xge_hal_frame_type_e {
+	XGE_HAL_FRAME_TYPE_DIX			= 0x0,
+	XGE_HAL_FRAME_TYPE_LLC			= 0x1,
+	XGE_HAL_FRAME_TYPE_SNAP			= 0x2,
+	XGE_HAL_FRAME_TYPE_IPX			= 0x3,
+} xge_hal_frame_type_e;
+
+/**
+ * enum xge_hal_frame_proto_e - Higher-layer ethernet protocols.
+ * @XGE_HAL_FRAME_PROTO_VLAN_TAGGED: VLAN.
+ * @XGE_HAL_FRAME_PROTO_IPV4: IPv4.
+ * @XGE_HAL_FRAME_PROTO_IPV6: IPv6.
+ * @XGE_HAL_FRAME_PROTO_IP_FRAGMENTED: IP fragmented.
+ * @XGE_HAL_FRAME_PROTO_TCP: TCP.
+ * @XGE_HAL_FRAME_PROTO_UDP: UDP.
+ * @XGE_HAL_FRAME_PROTO_TCP_OR_UDP: TCP or UDP.
+ *
+ * Higher layer ethernet protocols and options.
+ */
+typedef enum xge_hal_frame_proto_e {
+	XGE_HAL_FRAME_PROTO_VLAN_TAGGED		= 0x80,
+	XGE_HAL_FRAME_PROTO_IPV4		= 0x10,
+	XGE_HAL_FRAME_PROTO_IPV6		= 0x08,
+	XGE_HAL_FRAME_PROTO_IP_FRAGMENTED	= 0x04,
+	XGE_HAL_FRAME_PROTO_TCP			= 0x02,
+	XGE_HAL_FRAME_PROTO_UDP			= 0x01,
+	XGE_HAL_FRAME_PROTO_TCP_OR_UDP		= (XGE_HAL_FRAME_PROTO_TCP | \
+						   XGE_HAL_FRAME_PROTO_UDP)
+} xge_hal_frame_proto_e;
+
+/*
+ * xge_hal_ring_rxd_1_t
+ */
+typedef struct {
+	u64 host_control;
+	u64 control_1;
+	u64 control_2;
+#define XGE_HAL_RXD_1_MASK_BUFFER0_SIZE		vBIT(0xFFFF,0,16)
+#define XGE_HAL_RXD_1_SET_BUFFER0_SIZE(val)	vBIT(val,0,16)
+#define XGE_HAL_RXD_1_GET_BUFFER0_SIZE(Control_2) \
+			(int)((Control_2 & vBIT(0xFFFF,0,16))>>48)
+#define XGE_HAL_RXD_1_GET_RTH_VALUE(Control_2) \
+			(u32)((Control_2 & vBIT(0xFFFFFFFF,16,32))>>16)
+	u64 buffer0_ptr;
+} xge_hal_ring_rxd_1_t;
+
+/*
+ * xge_hal_ring_rxd_3_t
+ */
+typedef struct {
+	u64 host_control;
+	u64 control_1;
+
+	u64 control_2;
+#define XGE_HAL_RXD_3_MASK_BUFFER0_SIZE		vBIT(0xFF,8,8)
+#define XGE_HAL_RXD_3_SET_BUFFER0_SIZE(val)	vBIT(val,8,8)
+#define XGE_HAL_RXD_3_MASK_BUFFER1_SIZE		vBIT(0xFFFF,16,16)
+#define XGE_HAL_RXD_3_SET_BUFFER1_SIZE(val)	vBIT(val,16,16)
+#define XGE_HAL_RXD_3_MASK_BUFFER2_SIZE		vBIT(0xFFFF,32,16)
+#define XGE_HAL_RXD_3_SET_BUFFER2_SIZE(val)	vBIT(val,32,16)
+
+
+#define XGE_HAL_RXD_3_GET_BUFFER0_SIZE(Control_2) \
+				(int)((Control_2 & vBIT(0xFF,8,8))>>48)
+#define XGE_HAL_RXD_3_GET_BUFFER1_SIZE(Control_2) \
+				(int)((Control_2 & vBIT(0xFFFF,16,16))>>32)
+#define XGE_HAL_RXD_3_GET_BUFFER2_SIZE(Control_2) \
+				(int)((Control_2 & vBIT(0xFFFF,32,16))>>16)
+
+	u64 buffer0_ptr;
+	u64 buffer1_ptr;
+	u64 buffer2_ptr;
+} xge_hal_ring_rxd_3_t;
+
+/*
+ * xge_hal_ring_rxd_5_t
+ */
+typedef struct {
+#ifdef XGE_OS_HOST_BIG_ENDIAN
+	u32 host_control;
+	u32 control_3;
+#else
+	u32 control_3;
+	u32 host_control;
+#endif
+
+
+#define XGE_HAL_RXD_5_MASK_BUFFER3_SIZE		vBIT(0xFFFF,32,16)
+#define XGE_HAL_RXD_5_SET_BUFFER3_SIZE(val)	vBIT(val,32,16)
+#define XGE_HAL_RXD_5_MASK_BUFFER4_SIZE		vBIT(0xFFFF,48,16)
+#define XGE_HAL_RXD_5_SET_BUFFER4_SIZE(val)	vBIT(val,48,16)
+
+#define XGE_HAL_RXD_5_GET_BUFFER3_SIZE(Control_3) \
+				(int)((Control_3 & vBIT(0xFFFF,32,16))>>16)
+#define XGE_HAL_RXD_5_GET_BUFFER4_SIZE(Control_3) \
+				(int)((Control_3 & vBIT(0xFFFF,48,16)))
+
+	u64 control_1;
+	u64 control_2;
+
+#define XGE_HAL_RXD_5_MASK_BUFFER0_SIZE		vBIT(0xFFFF,0,16)
+#define XGE_HAL_RXD_5_SET_BUFFER0_SIZE(val)	vBIT(val,0,16)
+#define XGE_HAL_RXD_5_MASK_BUFFER1_SIZE		vBIT(0xFFFF,16,16)
+#define XGE_HAL_RXD_5_SET_BUFFER1_SIZE(val)	vBIT(val,16,16)
+#define XGE_HAL_RXD_5_MASK_BUFFER2_SIZE		vBIT(0xFFFF,32,16)
+#define XGE_HAL_RXD_5_SET_BUFFER2_SIZE(val)	vBIT(val,32,16)
+
+
+#define XGE_HAL_RXD_5_GET_BUFFER0_SIZE(Control_2) \
+			(int)((Control_2 & vBIT(0xFFFF,0,16))>>48)
+#define XGE_HAL_RXD_5_GET_BUFFER1_SIZE(Control_2) \
+			(int)((Control_2 & vBIT(0xFFFF,16,16))>>32)
+#define XGE_HAL_RXD_5_GET_BUFFER2_SIZE(Control_2) \
+			(int)((Control_2 & vBIT(0xFFFF,32,16))>>16)
+	u64 buffer0_ptr;
+	u64 buffer1_ptr;
+	u64 buffer2_ptr;
+	u64 buffer3_ptr;
+	u64 buffer4_ptr;
+} xge_hal_ring_rxd_5_t;
+
+#define XGE_HAL_RXD_GET_RTH_SPDM_HIT(Control_1) \
+		(u8)((Control_1 & BIT(18))>>45)
+#define XGE_HAL_RXD_GET_RTH_IT_HIT(Control_1) \
+		(u8)((Control_1 & BIT(19))>>44)
+#define XGE_HAL_RXD_GET_RTH_HASH_TYPE(Control_1) \
+		(u8)((Control_1 & vBIT(0xF,20,4))>>40)
+
+#define XGE_HAL_RXD_HASH_TYPE_NONE				0x0
+#define XGE_HAL_RXD_HASH_TYPE_TCP_IPV4			0x1
+#define XGE_HAL_RXD_HASH_TYPE_UDP_IPV4			0x2
+#define XGE_HAL_RXD_HASH_TYPE_IPV4				0x3
+#define XGE_HAL_RXD_HASH_TYPE_TCP_IPV6			0x4
+#define XGE_HAL_RXD_HASH_TYPE_UDP_IPV6			0x5
+#define XGE_HAL_RXD_HASH_TYPE_IPV6				0x6
+#define XGE_HAL_RXD_HASH_TYPE_TCP_IPV6_EX		0x7
+#define XGE_HAL_RXD_HASH_TYPE_UDP_IPV6_EX		0x8
+#define XGE_HAL_RXD_HASH_TYPE_IPV6_EX			0x9
+
+typedef u8 xge_hal_ring_block_t[XGE_HAL_RING_RXDBLOCK_SIZE];
+
+#define XGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET	0xFF8
+#define XGE_HAL_RING_MEMBLOCK_IDX_OFFSET	0xFF0
+
+#define XGE_HAL_RING_RXD_SIZEOF(n) \
+	(n==1 ? sizeof(xge_hal_ring_rxd_1_t) : \
+		(n==3 ? sizeof(xge_hal_ring_rxd_3_t) : \
+			sizeof(xge_hal_ring_rxd_5_t)))
+
+#define XGE_HAL_RING_RXDS_PER_BLOCK(n) \
+	(n==1 ? 127 : (n==3 ? 85 : 63))
+
+/**
+ * struct xge_hal_ring_rxd_priv_t - Receive descriptor HAL-private data.
+ * @dma_addr: DMA (mapped) address of _this_ descriptor.
+ * @dma_handle: DMA handle used to map the descriptor onto device.
+ * @dma_offset: Descriptor's offset in the memory block. HAL allocates
+ *              descriptors in memory blocks of
+ *              %XGE_HAL_RING_RXDBLOCK_SIZE
+ *              bytes. Each memblock is contiguous DMA-able memory. Each
+ *              memblock contains 1 or more 4KB RxD blocks visible to the
+ *              Xframe hardware.
+ * @dma_object: DMA address and handle of the memory block that contains
+ *              the descriptor. This member is used only in the "checked"
+ *              version of the HAL (to enforce certain assertions);
+ *              otherwise it gets compiled out.
+ * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage.
+ *
+ * Per-receive decsriptor HAL-private data. HAL uses the space to keep DMA
+ * information associated with the descriptor. Note that ULD can ask HAL
+ * to allocate additional per-descriptor space for its own (ULD-specific)
+ * purposes.
+ */
+typedef struct xge_hal_ring_rxd_priv_t {
+	dma_addr_t		dma_addr;
+	pci_dma_h		dma_handle;
+	ptrdiff_t		dma_offset;
+#ifdef XGE_DEBUG_ASSERT
+	xge_hal_mempool_dma_t	*dma_object;
+#endif
+#ifdef XGE_OS_MEMORY_CHECK
+	int			allocated;
+#endif
+} xge_hal_ring_rxd_priv_t;
+
+/**
+ * struct xge_hal_ring_t - Ring channel.
+ * @channel: Channel "base" of this ring, the common part of all HAL
+ *           channels.
+ * @buffer_mode: 1, 3, or 5. The value specifies a receive buffer mode,
+ *          as per Xframe User Guide.
+ * @indicate_max_pkts: Maximum number of packets processed within a single
+ *          interrupt. Can be used to limit the time spent inside hw
+ *          interrupt.
+ * @config: Ring configuration, part of device configuration
+ *          (see xge_hal_device_config_t{}).
+ * @rxd_size: RxD sizes for 1-, 3- or 5- buffer modes. As per Xframe spec,
+ *            1-buffer mode descriptor is 32 byte long, etc.
+ * @rxd_priv_size: Per RxD size reserved (by HAL) for ULD to keep per-descriptor
+ *                 data (e.g., DMA handle for Solaris)
+ * @rxds_per_block: Number of descriptors per hardware-defined RxD
+ *                  block. Depends on the (1-,3-,5-) buffer mode.
+ * @mempool: Memory pool, the pool from which descriptors get allocated.
+ *           (See xge_hal_mm.h).
+ * @rxdblock_priv_size: Reserved at the end of each RxD block. HAL internal
+ *                      usage. Not to confuse with @rxd_priv_size.
+ * @reserved_rxds_arr: Array of RxD pointers. At any point in time each
+ *                     entry in this array is available for allocation
+ *                     (via xge_hal_ring_dtr_reserve()) and posting.
+ * @cmpl_cnt: Completion counter. Is reset to zero upon entering the ISR.
+ *            Used in conjunction with @indicate_max_pkts. 
+ * Ring channel.
+ *
+ * Note: The structure is cache line aligned to better utilize
+ *       CPU cache performance.
+ */
+typedef struct xge_hal_ring_t {
+	xge_hal_channel_t		channel;
+	int				buffer_mode;
+	int				indicate_max_pkts;
+	xge_hal_ring_config_t		*config;
+	int				rxd_size;
+	int				rxd_priv_size;
+	int				rxds_per_block;
+	xge_hal_mempool_t		*mempool;
+	int				rxdblock_priv_size;
+	void				**reserved_rxds_arr;
+	int				cmpl_cnt;
+} __xge_os_attr_cacheline_aligned xge_hal_ring_t;
+
+/**
+ * struct xge_hal_dtr_info_t - Extended information associated with a
+ * completed ring descriptor.
+ * @l3_cksum: Result of IP checksum check (by Xframe hardware).
+ *            This field containing XGE_HAL_L3_CKSUM_OK would mean that
+ *            the checksum is correct, otherwise - the datagram is
+ *            corrupted.
+ * @l4_cksum: Result of TCP/UDP checksum check (by Xframe hardware).
+ *            This field containing XGE_HAL_L4_CKSUM_OK would mean that
+ *            the checksum is correct. Otherwise - the packet is
+ *            corrupted.
+ * @frame: See xge_hal_frame_type_e{}.
+ * @proto:    Reporting bits for various higher-layer protocols, including (but
+ *	      note restricted to) TCP and UDP. See xge_hal_frame_proto_e{}.
+ * @vlan:     VLAN tag extracted from the received frame.
+ * @rth_value: Receive Traffic Hashing(RTH) hash value. Produced by Xframe II
+ *             hardware if RTH is enabled.
+ * @rth_it_hit: Set, If RTH hash value calculated by the Xframe II hardware
+ *             has a matching entry in the Indirection table.
+ * @rth_spdm_hit: Set, If RTH hash value calculated by the Xframe II hardware
+ *             has a matching entry in the Socket Pair Direct Match table.
+ * @rth_hash_type: RTH hash code of the function used to calculate the hash.
+ * @reserved_pad: Unused byte.
+ */
+typedef struct xge_hal_dtr_info_t {
+	int	l3_cksum;
+	int	l4_cksum;
+	int	frame; /* zero or more of xge_hal_frame_type_e flags */
+	int	proto; /* zero or more of xge_hal_frame_proto_e flags */
+	int	vlan;
+	u32	rth_value;
+	u8	rth_it_hit;
+	u8	rth_spdm_hit;
+	u8	rth_hash_type;
+	u8	reserved_pad;
+} xge_hal_dtr_info_t;
+
+/* ========================== RING PRIVATE API ============================ */
+
+xge_hal_status_e __hal_ring_open(xge_hal_channel_h channelh,
+			xge_hal_channel_attr_t	*attr);
+
+void __hal_ring_close(xge_hal_channel_h channelh);
+
+void __hal_ring_hw_initialize(xge_hal_device_h devh);
+
+void __hal_ring_mtu_set(xge_hal_device_h devh, int new_mtu);
+
+void __hal_ring_prc_enable(xge_hal_channel_h channelh);
+
+void __hal_ring_prc_disable(xge_hal_channel_h channelh);
+
+xge_hal_status_e __hal_ring_initial_replenish(xge_hal_channel_t *channel,
+					      xge_hal_channel_reopen_e reopen);
+
+#if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_RING)
+#define __HAL_STATIC_RING
+#define __HAL_INLINE_RING
+
+__HAL_STATIC_RING __HAL_INLINE_RING int
+__hal_ring_block_memblock_idx(xge_hal_ring_block_t *block);
+
+__HAL_STATIC_RING __HAL_INLINE_RING void
+__hal_ring_block_memblock_idx_set(xge_hal_ring_block_t*block, int memblock_idx);
+
+__HAL_STATIC_RING __HAL_INLINE_RING dma_addr_t
+__hal_ring_block_next_pointer(xge_hal_ring_block_t *block);
+
+__HAL_STATIC_RING __HAL_INLINE_RING void
+__hal_ring_block_next_pointer_set(xge_hal_ring_block_t*block,
+			dma_addr_t dma_next);
+
+__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_ring_rxd_priv_t*
+__hal_ring_rxd_priv(xge_hal_ring_t *ring, xge_hal_dtr_h dtrh);
+
+/* =========================== RING PUBLIC API ============================ */
+
+__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e
+xge_hal_ring_dtr_reserve(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh);
+
+__HAL_STATIC_RING __HAL_INLINE_RING void*
+xge_hal_ring_dtr_private(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
+
+__HAL_STATIC_RING __HAL_INLINE_RING void
+xge_hal_ring_dtr_1b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointer, int	size);
+
+__HAL_STATIC_RING __HAL_INLINE_RING void
+xge_hal_ring_dtr_info_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
+			xge_hal_dtr_info_t *ext_info);
+
+__HAL_STATIC_RING __HAL_INLINE_RING void
+xge_hal_ring_dtr_1b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
+			dma_addr_t *dma_pointer, int *pkt_length);
+
+__HAL_STATIC_RING __HAL_INLINE_RING void
+xge_hal_ring_dtr_3b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[],
+			int sizes[]);
+
+__HAL_STATIC_RING __HAL_INLINE_RING void
+xge_hal_ring_dtr_3b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
+			dma_addr_t dma_pointers[], int sizes[]);
+
+__HAL_STATIC_RING __HAL_INLINE_RING void
+xge_hal_ring_dtr_5b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[],
+			int sizes[]);
+
+__HAL_STATIC_RING __HAL_INLINE_RING void
+xge_hal_ring_dtr_5b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
+			dma_addr_t dma_pointer[], int sizes[]);
+
+__HAL_STATIC_RING __HAL_INLINE_RING void
+xge_hal_ring_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
+
+__HAL_STATIC_RING __HAL_INLINE_RING void
+xge_hal_ring_dtr_pre_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
+
+__HAL_STATIC_RING __HAL_INLINE_RING void
+xge_hal_ring_dtr_post_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
+
+__HAL_STATIC_RING __HAL_INLINE_RING void
+xge_hal_ring_dtr_post_post_wmb(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
+
+__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e
+xge_hal_ring_dtr_next_completed(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh,
+			u8 *t_code);
+
+__HAL_STATIC_RING __HAL_INLINE_RING void
+xge_hal_ring_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
+
+__HAL_STATIC_RING __HAL_INLINE_RING	xge_hal_status_e
+xge_hal_ring_is_next_dtr_completed(xge_hal_channel_h channelh);
+
+#else /* XGE_FASTPATH_EXTERN */
+#define __HAL_STATIC_RING static
+#define __HAL_INLINE_RING inline
+#include <dev/nxge/xgehal/xgehal-ring-fp.c>
+#endif /* XGE_FASTPATH_INLINE */
+
+__EXTERN_END_DECLS
+
+#endif /* XGE_HAL_RING_H */
diff --git a/sys/dev/nxge/include/xgehal-stats.h b/sys/dev/nxge/include/xgehal-stats.h
new file mode 100644
index 0000000..ffe0e6e
--- /dev/null
+++ b/sys/dev/nxge/include/xgehal-stats.h
@@ -0,0 +1,1601 @@
+/*-
+ * Copyright (c) 2002-2007 Neterion, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+	xge_hal_fifo_t            *fifo    = (xge_hal_fifo_t *)channelh;
+ *  FileName :    xgehal-stats.h
+ *
+ *  Description:  HW statistics object
+ *
+ *  Created:      2 June 2004
+ */
+
+#ifndef XGE_HAL_STATS_H
+#define XGE_HAL_STATS_H
+
+#include <dev/nxge/include/xge-os-pal.h>
+#include <dev/nxge/include/xge-debug.h>
+#include <dev/nxge/include/xgehal-types.h>
+#include <dev/nxge/include/xgehal-config.h>
+
+__EXTERN_BEGIN_DECLS
+
+/**
+ * struct xge_hal_stats_hw_info_t - Xframe hardware statistics.
+ * Transmit MAC Statistics:
+ *
+ * @tmac_frms: Count of successfully transmitted MAC
+ * frames Note that this statistic may be inaccurate. The correct statistic may
+ * be derived by calcualating (tmac_ttl_octets - tmac_ttl_less_fb_octets) / 8
+ *
+ * @tmac_data_octets: Count of data and padding octets of successfully
+ * transmitted frames.
+ *
+ * @tmac_drop_frms: Count of frames that could not be sent for no other reason
+ * than internal MAC processing. Increments once whenever the
+ * transmit buffer is flushed (due to an ECC error on a memory descriptor).
+ *
+ * @tmac_mcst_frms: Count of successfully transmitted frames to a multicast
+ * address. Does not include frames sent to the broadcast address.
+ *
+ * @tmac_bcst_frms: Count of successfully transmitted frames to the broadcast
+ * address.
+ *
+ * @tmac_pause_ctrl_frms: Count of MAC PAUSE control frames that are
+ * transmitted. Since, the only control frames supported by this device
+ * are PAUSE frames, this register is a count of all transmitted MAC control
+ * frames.
+ *
+ * @tmac_ttl_octets: Count of total octets of transmitted frames, including
+ * framing characters.
+ *
+ * @tmac_ucst_frms: Count of transmitted frames containing a unicast address.
+ * @tmac_nucst_frms: Count of transmitted frames containing a non-unicast
+ * (broadcast, multicast) address.
+ *
+ * @tmac_any_err_frms: Count of transmitted frames containing any error that
+ * prevents them from being passed to the network. Increments if there is an ECC
+ * while reading the frame out of the transmit buffer.
+ *
+ * @tmac_ttl_less_fb_octets: Count of total octets of transmitted
+ * frames, not including framing characters (i.e. less framing bits)
+ *
+ * @tmac_vld_ip_octets: Count of total octets of transmitted IP datagrams that
+ * were passed to the network. Frames that are padded by the host have
+ * their padding counted as part of the IP datagram.
+ *
+ * @tmac_vld_ip: Count of transmitted IP datagrams that were passed to the
+ * network.
+ *
+ * @tmac_drop_ip: Count of transmitted IP datagrams that could not be passed to
+ * the network. Increments because of 1) an internal processing error (such as
+ * an uncorrectable ECC error); 2) a frame parsing error during IP checksum
+ * calculation.
+ *
+ * @tmac_icmp: Count of transmitted ICMP messages. Includes messages not sent
+ * due to problems within ICMP.
+ *
+ * @tmac_rst_tcp: Count of transmitted TCP segments containing the RST flag.
+ *
+ * @tmac_tcp: Count of transmitted TCP segments. Note that Xena has
+ * no knowledge of retransmission.
+ *
+ * @tmac_udp: Count of transmitted UDP datagrams.
+ * @reserved_0: Reserved.
+ *
+ * Receive MAC Statistics:
+ * @rmac_vld_frms: Count of successfully received MAC frames. Does not include
+ * frames received with frame-too-long, FCS, or length errors.
+ *
+ * @rmac_data_octets: Count of data and padding octets of successfully received
+ * frames. Does not include frames received with frame-too-long, FCS, or length
+ * errors.
+ *
+ * @rmac_fcs_err_frms: Count of received MAC frames that do not pass FCS. Does
+ * not include frames received with frame-too-long or frame-too-short error.
+ *
+ * @rmac_drop_frms: Count of received frames that could not be passed to the
+ * host because of 1) Random Early Discard (RED); 2) Frame steering algorithm
+ * found no available queue; 3) Receive ingress buffer overflow.
+ *
+ * @rmac_vld_mcst_frms: Count of successfully received MAC frames containing a
+ * multicast address. Does not include frames received with frame-too-long, FCS,
+ * or length errors.
+ *
+ * @rmac_vld_bcst_frms: Count of successfully received MAC frames containing a
+ * broadcast address. Does not include frames received with frame-too-long, FCS,
+ * or length errors.
+ *
+ * @rmac_in_rng_len_err_frms: Count of received frames with a length/type field
+ * value between 46 (42 for VLANtagged frames) and 1500 (also 1500 for
+ * VLAN-tagged frames), inclusive, that does not match the number of data octets
+ * (including pad) received. Also contains a count of received frames with a
+ * length/type field less than 46 (42 for VLAN-tagged frames) and the number of
+ * data octets (including pad) received is greater than 46 (42 for VLAN-tagged
+ * frames).
+ *
+ * @rmac_out_rng_len_err_frms: Count of received frames with length/type field
+ * between 1501 and 1535 decimal, inclusive.
+ *
+ * @rmac_long_frms: Count of received frames that are longer than
+ * rmac_max_pyld_len + 18 bytes (+22 bytes if VLAN-tagged).
+ *
+ * @rmac_pause_ctrl_frms: Count of received MAC PAUSE control frames.
+ *
+ * @rmac_unsup_ctrl_frms: Count of received MAC control frames
+ * that do not contain the PAUSE opcode. The sum of MAC_PAUSE_CTRL_FRMS and this
+ * register is a count of all received MAC control frames.
+ *
+ * @rmac_ttl_octets: Count of total octets of received frames, including framing
+ * characters.
+ *
+ * @rmac_accepted_ucst_frms: Count of successfully received frames
+ * containing a unicast address. Only includes frames that are passed to the
+ * system.
+ *
+ * @rmac_accepted_nucst_frms: Count of successfully received frames
+ * containing a non-unicast (broadcast or multicast) address. Only includes
+ * frames that are passed to the system. Could include, for instance,
+ * non-unicast frames that contain FCS errors if the MAC_ERROR_CFG register is
+ * set to pass FCSerrored frames to the host.
+ *
+ * @rmac_discarded_frms: Count of received frames containing any error that
+ * prevents them from being passed to the system. Includes, for example,
+ * received pause frames that are discarded by the MAC and frames discarded
+ * because of their destination address.
+ *
+ * @rmac_drop_events: Because the RMAC drops one frame at a time, this stat
+ * matches rmac_drop_frms.
+ *
+ * @reserved_1: Reserved.
+ * @rmac_ttl_less_fb_octets: Count of total octets of received frames,
+ * not including framing characters (i.e. less framing bits).
+ *
+ * @rmac_ttl_frms: Count of all received MAC frames, including frames received
+ * with frame-too-long, FCS, or length errors.
+ *
+ * @reserved_2: Reserved.
+ * @reserved_3: Reserved.
+ * @rmac_usized_frms: Count of received frames of length (including FCS, but not
+ * framing bits) less than 64 octets, that are otherwise well-formed.
+ *
+ * @rmac_osized_frms: Count of received frames of length (including FCS, but not
+ * framing bits) more than 1518 octets, that are otherwise well-formed.
+ *
+ * @rmac_frag_frms: Count of received frames of length (including FCS, but not
+ * framing bits) less than 64 octets that had bad FCS. In other words, counts
+ * fragments (i.e. runts).
+ *
+ * @rmac_jabber_frms: Count of received frames of length (including FCS, but not
+ * framing bits) more than MTU octets that had bad FCS. In other words, counts
+ * jabbers.
+ *
+ * @reserved_4: Reserved.
+ * @rmac_ttl_64_frms: Count of all received MAC frames with length (including
+ * FCS, but not framing bits) of exactly 64 octets. Includes frames received
+ * with frame-too-long, FCS, or length errors.
+ *
+ * @rmac_ttl_65_127_frms: Count of all received MAC frames with length
+ * (including FCS, but not framing bits) of between 65 and 127 octets
+ * inclusive. Includes frames received with frame-too-long, FCS, or length
+ * errors.
+ * @reserved_5: Reserved.
+ * @rmac_ttl_128_255_frms: Count of all received MAC frames with length
+ * (including FCS, but not framing bits) of between 128 and 255 octets
+ * inclusive. Includes frames received with frame-too-long, FCS, or length
+ * errors.
+ *
+ * @rmac_ttl_256_511_frms: Count of all received MAC frames with length
+ * (including FCS, but not framing bits) of between 256 and 511 octets
+ * inclusive. Includes frames received with frame-too-long, FCS, or length
+ * errors.
+ *
+ * @reserved_6: Reserved.
+ * @rmac_ttl_512_1023_frms: Count of all received MAC frames with length
+ * (including FCS, but not framing bits) of between 512 and 1023 octets
+ * inclusive. Includes frames received with frame-too-long, FCS, or length
+ * errors.
+ *
+ * @rmac_ttl_1024_1518_frms: Count of all received MAC frames with length
+ * (including FCS, but not framing bits) of between 1024 and 1518 octets
+ * inclusive. Includes frames received with frame-too-long, FCS, or length
+ * errors.
+ * @reserved_7: Reserved.
+ * @rmac_ip: Count of received IP datagrams. Includes errored IP datagrams.
+ *
+ * @rmac_ip_octets: Count of number of octets in received IP datagrams. Includes
+ * errored IP datagrams.
+ *
+ * @rmac_hdr_err_ip: Count of received IP datagrams that are discarded due to IP
+ * header errors.
+ *
+ * @rmac_drop_ip: Count of received IP datagrams that could not be passed to the
+ * host because of 1) Random Early Discard (RED); 2) Frame steering algorithm
+ * found no available queue; 3) Receive ingress buffer overflow.
+ * @rmac_icmp: Count of received ICMP messages. Includes errored ICMP messages
+ * (due to ICMP checksum fail).
+ *
+ * @reserved_8: Reserved.
+ * @rmac_tcp: Count of received TCP segments. Since Xena is unaware of
+ * connection context, counts all received TCP segments, regardless of whether
+ * or not they pertain to an established connection.
+ *
+ * @rmac_udp: Count of received UDP datagrams.
+ * @rmac_err_drp_udp: Count of received UDP datagrams that were not delivered to
+ * the system because of 1) Random Early Discard (RED); 2) Frame steering
+ * algorithm found no available queue; 3) Receive ingress buffer overflow.
+ *
+ * @rmac_xgmii_err_sym: Count of the number of symbol errors in the received
+ * XGMII data (i.e. PHY indicates "Receive Error" on the XGMII). Only includes
+ * symbol errors that are observed between the XGMII Start Frame Delimiter
+ * and End Frame Delimiter, inclusive. And only increments the count by one for
+ * each frame.
+ *
+ * @rmac_frms_q0: Count of number of frames that pass through queue 0 of receive
+ * buffer.
+ * @rmac_frms_q1: Count of number of frames that pass through queue 1 of receive
+ * buffer.
+ * @rmac_frms_q2: Count of number of frames that pass through queue 2 of receive
+ * buffer.
+ * @rmac_frms_q3: Count of number of frames that pass through queue 3 of receive
+ * buffer.
+ * @rmac_frms_q4: Count of number of frames that pass through queue 4 of receive
+ * buffer.
+ * @rmac_frms_q5: Count of number of frames that pass through queue 5 of receive
+ * buffer.
+ * @rmac_frms_q6: Count of number of frames that pass through queue 6 of receive
+ * buffer.
+ * @rmac_frms_q7: Count of number of frames that pass through queue 7 of receive
+ * buffer.
+ * @rmac_full_q0: Count of number of times that receive buffer queue 0 has
+ * filled up. If a queue is size 0, then this stat is incremented to a value of
+ * 1 when MAC receives its first frame.
+ *
+ * @rmac_full_q1: Count of number of times that receive buffer queue 1 has
+ * filled up. If a queue is size 0, then this stat is incremented to a value of
+ * 1 when MAC receives its first frame.
+ *
+ * @rmac_full_q2: Count of number of times that receive buffer queue 2 has
+ * filled up. If a queue is size 0, then this stat is incremented to a value of
+ * 1 when MAC receives its first frame.
+ *
+ * @rmac_full_q3: Count of number of times that receive buffer queue 3 has
+ * filled up. If a queue is size 0, then this stat is incremented to a value of
+ * 1 when MAC receives its first frame.
+ *
+ * @rmac_full_q4: Count of number of times that receive buffer queue 4 has
+ * filled up. If a queue is size 0, then this stat is incremented to a value of
+ * 1 when MAC receives its first frame.
+ *
+ * @rmac_full_q5: Count of number of times that receive buffer queue 5 has
+ * filled up. If a queue is size 0, then this stat is incremented to a value of
+ * 1 when MAC receives its first frame.
+ *
+ * @rmac_full_q6: Count of number of times that receive buffer queue 6 has
+ * filled up. If a queue is size 0, then this stat is incremented to a value of
+ * 1 when MAC receives its first frame.
+ *
+ * @rmac_full_q7: Count of number of times that receive buffer queue 7 has
+ * filled up. If a queue is size 0, then this stat is incremented to a value of
+ * 1 when MAC receives its first frame.
+ *
+ * @rmac_pause_cnt: Count of number of pause quanta that the MAC has been in the
+ * paused state. Recall, one pause quantum equates to 512 bit times.
+ * @reserved_9: Reserved.
+ * @rmac_xgmii_data_err_cnt: This counter is incremented when either 1) The
+ * Reconcilliation Sublayer (RS) is expecting one control character and gets
+ * another (i.e. expecting Start control character and gets another control
+ * character); 2) Start control character is not in lane 0 or lane 4; 3) The RS
+ * gets a Start control character, but the start frame delimiter is not found in
+ * the correct location.
+ * @rmac_xgmii_ctrl_err_cnt: Maintains a count of unexpected or
+ * misplaced control characters occuring outside of normal data transmission
+ * (i.e. not included in RMAC_XGMII_DATA_ERR_CNT).
+ *
+ * @rmac_accepted_ip: Count of received IP datagrams that were passed to the
+ * system.
+ *
+ * @rmac_err_tcp: Count of received TCP segments containing errors. For example,
+ * bad TCP checksum.
+ *
+ * PCI (bus) Statistics:
+ * @rd_req_cnt: Counts the total number of read requests made by the device.
+ * @new_rd_req_cnt: Counts the requests made for a new read sequence (request
+ * made for the same sequence after a retry or disconnect response are not
+ * counted).
+ * @new_rd_req_rtry_cnt: Counts the Retry responses received on the start of
+ * the new read sequences.
+ * @rd_rtry_cnt: Counts the Retry responses received for read requests.
+ * @wr_rtry_rd_ack_cnt: Increments whenever a read request is accepted by
+ * the target after a write request was terminated with retry.
+ * @wr_req_cnt: Counts the total number of Write requests made by the device.
+ * @new_wr_req_cnt: Counts the requests made for a new write sequence (request
+ * made for the same sequence after a retry or disconnect response are not
+ * counted).
+ * @new_wr_req_rtry_cnt: Counts the requests made for a new write sequence
+ * (request made for the same sequence after a retry or disconnect response are
+ * not counted).
+ *
+ * @wr_rtry_cnt: Counts the Retry responses received for write requests.
+ * @wr_disc_cnt: Write Disconnect. Counts the target initiated disconnects
+ * on write transactions.
+ * @rd_rtry_wr_ack_cnt: Increments whenever a write request is accepted by the
+ * target after a read request was terminated with retry.
+ *
+ * @txp_wr_cnt: Counts the host write transactions to the Tx Pointer
+ * FIFOs.
+ * @txd_rd_cnt: Count of the Transmit Descriptor (TxD) read requests.
+ * @txd_wr_cnt: Count of the TxD write requests.
+ * @rxd_rd_cnt: Count of the Receive Descriptor (RxD) read requests.
+ * @rxd_wr_cnt: Count of the RxD write requests.
+ * @txf_rd_cnt: Count of transmit frame read requests. This will not
+ * equal the number of frames transmitted, as frame data is typically spread
+ * across multiple PCI transactions.
+ * @rxf_wr_cnt: Count of receive frame write requests.
+ *
+ * @tmac_frms_oflow: tbd
+ * @tmac_data_octets_oflow: tbd
+ * @tmac_mcst_frms_oflow: tbd
+ * @tmac_bcst_frms_oflow: tbd
+ * @tmac_ttl_octets_oflow: tbd
+ * @tmac_ucst_frms_oflow: tbd
+ * @tmac_nucst_frms_oflow: tbd
+ * @tmac_any_err_frms_oflow: tbd
+ * @tmac_vlan_frms: tbd
+ * @tmac_vld_ip_oflow: tbd
+ * @tmac_drop_ip_oflow: tbd
+ * @tmac_icmp_oflow: tbd
+ * @tmac_rst_tcp_oflow: tbd
+ * @tmac_udp_oflow: tbd
+ * @reserved_10: tbd
+ * @tpa_unknown_protocol: tbd
+ * @tpa_parse_failure: tbd
+ * @rmac_vld_frms_oflow: tbd
+ * @rmac_data_octets_oflow: tbd
+ * @rmac_vld_mcst_frms_oflow: tbd
+ * @rmac_vld_bcst_frms_oflow: tbd
+ * @rmac_ttl_octets_oflow: tbd
+ * @rmac_accepted_ucst_frms_oflow: tbd
+ * @rmac_accepted_nucst_frms_oflow: tbd
+ * @rmac_discarded_frms_oflow: tbd
+ * @rmac_drop_events_oflow: tbd
+ * @rmac_usized_frms_oflow: tbd
+ * @rmac_osized_frms_oflow: tbd
+ * @rmac_frag_frms_oflow: tbd
+ * @rmac_jabber_frms_oflow: tbd
+ * @rmac_ip_oflow: tbd
+ * @rmac_drop_ip_oflow: tbd
+ * @rmac_icmp_oflow: tbd
+ * @rmac_udp_oflow: tbd
+ * @reserved_11: tbd
+ * @rmac_err_drp_udp_oflow: tbd
+ * @rmac_pause_cnt_oflow: tbd
+ * @rmac_ttl_1519_4095_frms: tbd
+ * @rmac_ttl_4096_8191_frms: tbd
+ * @rmac_ttl_8192_max_frms: tbd
+ * @rmac_ttl_gt_max_frms: tbd
+ * @rmac_osized_alt_frms: tbd
+ * @rmac_jabber_alt_frms: tbd
+ * @rmac_gt_max_alt_frms: tbd
+ * @rmac_vlan_frms: tbd
+ * @rmac_fcs_discard: tbd
+ * @rmac_len_discard: tbd
+ * @rmac_da_discard: tbd
+ * @rmac_pf_discard: tbd
+ * @rmac_rts_discard: tbd
+ * @rmac_wol_discard: tbd
+ * @rmac_red_discard: tbd
+ * @rmac_ingm_full_discard: tbd
+ * @rmac_accepted_ip_oflow: tbd
+ * @reserved_12: tbd
+ * @link_fault_cnt: TBD
+ * @reserved_13: tbd
+ * Xframe hardware statistics.
+ */
+typedef struct xge_hal_stats_hw_info_t {
+#ifdef  XGE_OS_HOST_BIG_ENDIAN
+/* Tx MAC statistics counters. */
+	u32 tmac_frms;
+	u32 tmac_data_octets;
+	u64 tmac_drop_frms;
+	u32 tmac_mcst_frms;
+	u32 tmac_bcst_frms;
+	u64 tmac_pause_ctrl_frms;
+	u32 tmac_ttl_octets;
+	u32 tmac_ucst_frms;
+	u32 tmac_nucst_frms;
+	u32 tmac_any_err_frms;
+	u64 tmac_ttl_less_fb_octets;
+	u64 tmac_vld_ip_octets;
+	u32 tmac_vld_ip;
+	u32 tmac_drop_ip;
+	u32 tmac_icmp;
+	u32 tmac_rst_tcp;
+	u64 tmac_tcp;
+	u32 tmac_udp;
+	u32 reserved_0;
+
+/* Rx MAC Statistics counters. */
+	u32 rmac_vld_frms;
+	u32 rmac_data_octets;
+	u64 rmac_fcs_err_frms;
+	u64 rmac_drop_frms;
+	u32 rmac_vld_mcst_frms;
+	u32 rmac_vld_bcst_frms;
+	u32 rmac_in_rng_len_err_frms;
+	u32 rmac_out_rng_len_err_frms;
+	u64 rmac_long_frms;
+	u64 rmac_pause_ctrl_frms;
+	u64 rmac_unsup_ctrl_frms;
+	u32 rmac_ttl_octets;
+	u32 rmac_accepted_ucst_frms;
+	u32 rmac_accepted_nucst_frms;
+	u32 rmac_discarded_frms;
+	u32 rmac_drop_events;
+	u32 reserved_1;
+	u64 rmac_ttl_less_fb_octets;
+	u64 rmac_ttl_frms;
+	u64 reserved_2;
+	u32 reserved_3;
+	u32 rmac_usized_frms;
+	u32 rmac_osized_frms;
+	u32 rmac_frag_frms;
+	u32 rmac_jabber_frms;
+	u32 reserved_4;
+	u64 rmac_ttl_64_frms;
+	u64 rmac_ttl_65_127_frms;
+	u64 reserved_5;
+	u64 rmac_ttl_128_255_frms;
+	u64 rmac_ttl_256_511_frms;
+	u64 reserved_6;
+	u64 rmac_ttl_512_1023_frms;
+	u64 rmac_ttl_1024_1518_frms;
+	u32 reserved_7;
+	u32 rmac_ip;
+	u64 rmac_ip_octets;
+	u32 rmac_hdr_err_ip;
+	u32 rmac_drop_ip;
+	u32 rmac_icmp;
+	u32 reserved_8;
+	u64 rmac_tcp;
+	u32 rmac_udp;
+	u32 rmac_err_drp_udp;
+	u64 rmac_xgmii_err_sym;
+	u64 rmac_frms_q0;
+	u64 rmac_frms_q1;
+	u64 rmac_frms_q2;
+	u64 rmac_frms_q3;
+	u64 rmac_frms_q4;
+	u64 rmac_frms_q5;
+	u64 rmac_frms_q6;
+	u64 rmac_frms_q7;
+	u16 rmac_full_q0;
+	u16 rmac_full_q1;
+	u16 rmac_full_q2;
+	u16 rmac_full_q3;
+	u16 rmac_full_q4;
+	u16 rmac_full_q5;
+	u16 rmac_full_q6;
+	u16 rmac_full_q7;
+	u32 rmac_pause_cnt;
+	u32 reserved_9;
+	u64 rmac_xgmii_data_err_cnt;
+	u64 rmac_xgmii_ctrl_err_cnt;
+	u32 rmac_accepted_ip;
+	u32 rmac_err_tcp;
+
+/* PCI/PCI-X Read transaction statistics. */
+	u32 rd_req_cnt;
+	u32 new_rd_req_cnt;
+	u32 new_rd_req_rtry_cnt;
+	u32 rd_rtry_cnt;
+	u32 wr_rtry_rd_ack_cnt;
+
+/* PCI/PCI-X write transaction statistics. */
+	u32 wr_req_cnt;
+	u32 new_wr_req_cnt;
+	u32 new_wr_req_rtry_cnt;
+	u32 wr_rtry_cnt;
+	u32 wr_disc_cnt;
+	u32 rd_rtry_wr_ack_cnt;
+
+/*	DMA Transaction statistics. */
+	u32 txp_wr_cnt;
+	u32 txd_rd_cnt;
+	u32 txd_wr_cnt;
+	u32 rxd_rd_cnt;
+	u32 rxd_wr_cnt;
+	u32 txf_rd_cnt;
+	u32 rxf_wr_cnt;
+
+/* Enhanced Herc statistics */
+	u32 tmac_frms_oflow;
+	u32 tmac_data_octets_oflow;
+	u32 tmac_mcst_frms_oflow;
+	u32 tmac_bcst_frms_oflow;
+	u32 tmac_ttl_octets_oflow;
+	u32 tmac_ucst_frms_oflow;
+	u32 tmac_nucst_frms_oflow;
+	u32 tmac_any_err_frms_oflow;
+	u64 tmac_vlan_frms;
+	u32 tmac_vld_ip_oflow;
+	u32 tmac_drop_ip_oflow;
+	u32 tmac_icmp_oflow;
+	u32 tmac_rst_tcp_oflow;
+	u32 tmac_udp_oflow;
+	u32 tpa_unknown_protocol;
+	u32 tpa_parse_failure;
+	u32 reserved_10;
+	u32 rmac_vld_frms_oflow;
+	u32 rmac_data_octets_oflow;
+	u32 rmac_vld_mcst_frms_oflow;
+	u32 rmac_vld_bcst_frms_oflow;
+	u32 rmac_ttl_octets_oflow;
+	u32 rmac_accepted_ucst_frms_oflow;
+	u32 rmac_accepted_nucst_frms_oflow;
+	u32 rmac_discarded_frms_oflow;
+	u32 rmac_drop_events_oflow;
+	u32 rmac_usized_frms_oflow;
+	u32 rmac_osized_frms_oflow;
+	u32 rmac_frag_frms_oflow;
+	u32 rmac_jabber_frms_oflow;
+	u32 rmac_ip_oflow;
+	u32 rmac_drop_ip_oflow;
+	u32 rmac_icmp_oflow;
+	u32 rmac_udp_oflow;
+	u32 rmac_err_drp_udp_oflow;
+	u32 rmac_pause_cnt_oflow;
+	u32 reserved_11;
+	u64 rmac_ttl_1519_4095_frms;
+	u64 rmac_ttl_4096_8191_frms;
+	u64 rmac_ttl_8192_max_frms;
+	u64 rmac_ttl_gt_max_frms;
+	u64 rmac_osized_alt_frms;
+	u64 rmac_jabber_alt_frms;
+	u64 rmac_gt_max_alt_frms;
+	u64 rmac_vlan_frms;
+	u32 rmac_fcs_discard;
+	u32 rmac_len_discard;
+	u32 rmac_da_discard;
+	u32 rmac_pf_discard;
+	u32 rmac_rts_discard;
+	u32 rmac_wol_discard;
+	u32 rmac_red_discard;
+	u32 rmac_ingm_full_discard;
+	u32 rmac_accepted_ip_oflow;
+	u32 reserved_12;
+	u32 link_fault_cnt;
+	u32 reserved_13;
+#else
+/* Tx MAC statistics counters. */
+	u32 tmac_data_octets;
+	u32 tmac_frms;
+	u64 tmac_drop_frms;
+	u32 tmac_bcst_frms;
+	u32 tmac_mcst_frms;
+	u64 tmac_pause_ctrl_frms;
+	u32 tmac_ucst_frms;
+	u32 tmac_ttl_octets;
+	u32 tmac_any_err_frms;
+	u32 tmac_nucst_frms;
+	u64 tmac_ttl_less_fb_octets;
+	u64 tmac_vld_ip_octets;
+	u32 tmac_drop_ip;
+	u32 tmac_vld_ip;
+	u32 tmac_rst_tcp;
+	u32 tmac_icmp;
+	u64 tmac_tcp;
+	u32 reserved_0;
+	u32 tmac_udp;
+
+/* Rx MAC Statistics counters. */
+	u32 rmac_data_octets;
+	u32 rmac_vld_frms;
+	u64 rmac_fcs_err_frms;
+	u64 rmac_drop_frms;
+	u32 rmac_vld_bcst_frms;
+	u32 rmac_vld_mcst_frms;
+	u32 rmac_out_rng_len_err_frms;
+	u32 rmac_in_rng_len_err_frms;
+	u64 rmac_long_frms;
+	u64 rmac_pause_ctrl_frms;
+	u64 rmac_unsup_ctrl_frms;
+	u32 rmac_accepted_ucst_frms;
+	u32 rmac_ttl_octets;
+	u32 rmac_discarded_frms;
+	u32 rmac_accepted_nucst_frms;
+	u32 reserved_1;
+	u32 rmac_drop_events;
+	u64 rmac_ttl_less_fb_octets;
+	u64 rmac_ttl_frms;
+	u64 reserved_2;
+	u32 rmac_usized_frms;
+	u32 reserved_3;
+	u32 rmac_frag_frms;
+	u32 rmac_osized_frms;
+	u32 reserved_4;
+	u32 rmac_jabber_frms;
+	u64 rmac_ttl_64_frms;
+	u64 rmac_ttl_65_127_frms;
+	u64 reserved_5;
+	u64 rmac_ttl_128_255_frms;
+	u64 rmac_ttl_256_511_frms;
+	u64 reserved_6;
+	u64 rmac_ttl_512_1023_frms;
+	u64 rmac_ttl_1024_1518_frms;
+	u32 rmac_ip;
+	u32 reserved_7;
+	u64 rmac_ip_octets;
+	u32 rmac_drop_ip;
+	u32 rmac_hdr_err_ip;
+	u32 reserved_8;
+	u32 rmac_icmp;
+	u64 rmac_tcp;
+	u32 rmac_err_drp_udp;
+	u32 rmac_udp;
+	u64 rmac_xgmii_err_sym;
+	u64 rmac_frms_q0;
+	u64 rmac_frms_q1;
+	u64 rmac_frms_q2;
+	u64 rmac_frms_q3;
+	u64 rmac_frms_q4;
+	u64 rmac_frms_q5;
+	u64 rmac_frms_q6;
+	u64 rmac_frms_q7;
+	u16 rmac_full_q3;
+	u16 rmac_full_q2;
+	u16 rmac_full_q1;
+	u16 rmac_full_q0;
+	u16 rmac_full_q7;
+	u16 rmac_full_q6;
+	u16 rmac_full_q5;
+	u16 rmac_full_q4;
+	u32 reserved_9;
+	u32 rmac_pause_cnt;
+	u64 rmac_xgmii_data_err_cnt;
+	u64 rmac_xgmii_ctrl_err_cnt;
+	u32 rmac_err_tcp;
+	u32 rmac_accepted_ip;
+
+/* PCI/PCI-X Read transaction statistics. */
+	u32 new_rd_req_cnt;
+	u32 rd_req_cnt;
+	u32 rd_rtry_cnt;
+	u32 new_rd_req_rtry_cnt;
+
+/* PCI/PCI-X Write/Read transaction statistics. */
+	u32 wr_req_cnt;
+	u32 wr_rtry_rd_ack_cnt;
+	u32 new_wr_req_rtry_cnt;
+	u32 new_wr_req_cnt;
+	u32 wr_disc_cnt;
+	u32 wr_rtry_cnt;
+
+/*	PCI/PCI-X Write / DMA Transaction statistics. */
+	u32 txp_wr_cnt;
+	u32 rd_rtry_wr_ack_cnt;
+	u32 txd_wr_cnt;
+	u32 txd_rd_cnt;
+	u32 rxd_wr_cnt;
+	u32 rxd_rd_cnt;
+	u32 rxf_wr_cnt;
+	u32 txf_rd_cnt;
+
+/* Enhanced Herc statistics */
+	u32 tmac_data_octets_oflow;
+	u32 tmac_frms_oflow;
+	u32 tmac_bcst_frms_oflow;
+	u32 tmac_mcst_frms_oflow;
+	u32 tmac_ucst_frms_oflow;
+	u32 tmac_ttl_octets_oflow;
+	u32 tmac_any_err_frms_oflow;
+	u32 tmac_nucst_frms_oflow;
+	u64 tmac_vlan_frms;
+	u32 tmac_drop_ip_oflow;
+	u32 tmac_vld_ip_oflow;
+	u32 tmac_rst_tcp_oflow;
+	u32 tmac_icmp_oflow;
+	u32 tpa_unknown_protocol;
+	u32 tmac_udp_oflow;
+	u32 reserved_10;
+	u32 tpa_parse_failure;
+	u32 rmac_data_octets_oflow;
+	u32 rmac_vld_frms_oflow;
+	u32 rmac_vld_bcst_frms_oflow;
+	u32 rmac_vld_mcst_frms_oflow;
+	u32 rmac_accepted_ucst_frms_oflow;
+	u32 rmac_ttl_octets_oflow;
+	u32 rmac_discarded_frms_oflow;
+	u32 rmac_accepted_nucst_frms_oflow;
+	u32 rmac_usized_frms_oflow;
+	u32 rmac_drop_events_oflow;
+	u32 rmac_frag_frms_oflow;
+	u32 rmac_osized_frms_oflow;
+	u32 rmac_ip_oflow;
+	u32 rmac_jabber_frms_oflow;
+	u32 rmac_icmp_oflow;
+	u32 rmac_drop_ip_oflow;
+	u32 rmac_err_drp_udp_oflow;
+	u32 rmac_udp_oflow;
+	u32 reserved_11;
+	u32 rmac_pause_cnt_oflow;
+	u64 rmac_ttl_1519_4095_frms;
+	u64 rmac_ttl_4096_8191_frms;
+	u64 rmac_ttl_8192_max_frms;
+	u64 rmac_ttl_gt_max_frms;
+	u64 rmac_osized_alt_frms;
+	u64 rmac_jabber_alt_frms;
+	u64 rmac_gt_max_alt_frms;
+	u64 rmac_vlan_frms;
+	u32 rmac_len_discard;
+	u32 rmac_fcs_discard;
+	u32 rmac_pf_discard;
+	u32 rmac_da_discard;
+	u32 rmac_wol_discard;
+	u32 rmac_rts_discard;
+	u32 rmac_ingm_full_discard;
+	u32 rmac_red_discard;
+	u32 reserved_12;
+	u32 rmac_accepted_ip_oflow;
+	u32 reserved_13;
+	u32 link_fault_cnt;
+#endif
+} xge_hal_stats_hw_info_t;
+
+/**
+ * struct xge_hal_stats_channel_into_t - HAL channel statistics.
+ * @full_cnt: TBD
+ * @usage_max: TBD
+ * @reserve_free_swaps_cnt: Reserve/free swap counter. Internal usage.
+ * @max_compl_per_intr_cnt: Maximum number of completions per interrupt.
+ * @avg_compl_per_intr_cnt: Average number of completions per interrupt.
+ *           Note that a total number of completed descriptors
+ *           for the given channel can be calculated as
+ *           (@traffic_intr_cnt * @avg_compl_per_intr_cnt).
+ * @total_compl_cnt: Total completion count.
+ *        @total_compl_cnt == (@traffic_intr_cnt * @avg_compl_per_intr_cnt).
+ * @total_posts: Total number of descriptor postings on the channel.
+ *        Counts the number of xge_hal_ring_dtr_post()
+ *        or xge_hal_fifo_dtr_post() calls by ULD, for ring and fifo
+ *        channel, respectively.
+ * @total_posts_many: Total number of posts on the channel that involved
+ *        more than one descriptor. Counts the number of
+ *        xge_hal_fifo_dtr_post_many() calls performed by ULD.
+ * @total_buffers: Total number of buffers posted on the channel.
+ * @copied_frags: TBD
+ * @copied_buffers: TBD
+ * @avg_buffers_per_post: Average number of buffers transferred in a single
+ *        post operation.
+ *        Calculated as @total_buffers/@total_posts.
+ * @avg_buffer_size: Average buffer size transferred by a single post
+ *       operation on a fifo channel. The counter is not supported for a ring
+ *       channel. Calculated as a total number of transmitted octets divided
+ *       by @total_buffers.
+ * @avg_post_size: Average amount of data transferred by a single post.
+ *       Calculated as a total number of transmitted octets divided by
+ *       @total_posts.
+ * @ring_bump_cnt: Ring "bump" count. Number of times the hardware could
+ *       not post receive data (and had to continue keeping it on-board)
+ *       because of unavailable receive descriptor(s).
+ * @total_posts_dtrs_many: Total number of posts on the channel that involving
+ *       more than one descriptor.
+ * @total_posts_frags_many: Total number of fragments posted on the channel
+ *	 during post requests of multiple descriptors.
+ * @total_posts_dang_dtrs: Total number of posts on the channel involving
+ *       dangling descriptors.
+ * @total_posts_dang_frags: Total number of dangling fragments posted on the channel
+ *	 during post request containing multiple descriptors.
+ *
+ * HAL channel counters.
+ * See also: xge_hal_stats_device_info_t{}.
+ */
+typedef struct xge_hal_stats_channel_info_t {
+	u32	full_cnt;
+	u32	usage_max;
+	u32	reserve_free_swaps_cnt;
+	u32	avg_compl_per_intr_cnt;
+	u32	total_compl_cnt;
+	u32	total_posts;
+	u32	total_posts_many;
+	u32	total_buffers;
+	u32	copied_frags;
+	u32	copied_buffers;
+	u32	avg_buffers_per_post;
+	u32	avg_buffer_size;
+	u32	avg_post_size;
+	u32	ring_bump_cnt;
+	u32	total_posts_dtrs_many;
+	u32	total_posts_frags_many;
+	u32	total_posts_dang_dtrs;
+	u32	total_posts_dang_frags;
+} xge_hal_stats_channel_info_t;
+
+/**
+ * struct xge_hal_xpak_counter_t - HAL xpak error counters
+ * @excess_temp: excess transceiver_temperature count
+ * @excess_bias_current: excess laser_bias_current count
+ * @excess_laser_output: excess laser_output_power count
+ * @tick_period: tick count for each cycle
+ */
+typedef struct xge_hal_xpak_counter_t {
+        u32     excess_temp;
+        u32     excess_bias_current;
+        u32     excess_laser_output;
+        u32     tick_period;
+} xge_hal_xpak_counter_t;
+
+/**
+ * struct xge_hal_stats_xpak_t - HAL xpak stats
+ * @alarm_transceiver_temp_high: alarm_transceiver_temp_high count value
+ * @alarm_transceiver_temp_low : alarm_transceiver_temp_low count value
+ * @alarm_laser_bias_current_high: alarm_laser_bias_current_high count value
+ * @alarm_laser_bias_current_low: alarm_laser_bias_current_low count value
+ * @alarm_laser_output_power_high: alarm_laser_output_power_high count value
+ * @alarm_laser_output_power_low: alarm_laser_output_power_low count value
+ * @warn_transceiver_temp_high: warn_transceiver_temp_high count value
+ * @warn_transceiver_temp_low: warn_transceiver_temp_low count value
+ * @warn_laser_bias_current_high: warn_laser_bias_current_high count value
+ * @warn_laser_bias_current_low: warn_laser_bias_current_low count value
+ * @warn_laser_output_power_high: warn_laser_output_power_high count value
+ * @warn_laser_output_power_low: warn_laser_output_power_low count value
+ */
+typedef struct xge_hal_stats_xpak_t {
+        u16     alarm_transceiver_temp_high;
+        u16     alarm_transceiver_temp_low;
+        u16     alarm_laser_bias_current_high;
+        u16     alarm_laser_bias_current_low;
+        u16     alarm_laser_output_power_high;
+        u16     alarm_laser_output_power_low;
+        u16     warn_transceiver_temp_high;
+        u16     warn_transceiver_temp_low;
+        u16     warn_laser_bias_current_high;
+        u16     warn_laser_bias_current_low;
+        u16     warn_laser_output_power_high;
+        u16     warn_laser_output_power_low;
+} xge_hal_stats_xpak_t;
+
+
+
+/**
+ * struct xge_hal_stats_sw_err_t - HAL device error statistics.
+ * @sm_err_cnt: TBD
+ * @single_ecc_err_cnt: TBD
+ * @double_ecc_err_cnt: TBD
+ * @ecc_err_cnt: ECC error count.
+ * @parity_err_cnt: Parity error count.
+ * @serr_cnt: Number of exceptions indicated to the host via PCI SERR#.
+ * @rxd_t_code_err_cnt: Array of receive transfer codes. The position
+ * (index) in this array reflects the transfer code type, for instance
+ * 0x7 - for "invalid receive buffer size", or 0x8 - for ECC.
+ * Value rxd_t_code_err_cnt[i] reflects the
+ * number of times the corresponding transfer code was encountered.
+ *
+ * @txd_t_code_err_cnt: Array of transmit transfer codes. The position
+ * (index) in this array reflects the transfer code type, for instance
+ * 0xA - "loss of link".
+ * Value txd_t_code_err_cnt[i] reflects the
+ * number of times the corresponding transfer code was encountered.
+ * @stats_xpak: TBD
+ * @xpak_counter: TBD
+ */
+typedef struct xge_hal_stats_sw_err_t {
+	u32     sm_err_cnt;
+	u32     single_ecc_err_cnt;
+	u32     double_ecc_err_cnt;
+	u32     ecc_err_cnt;
+	u32     parity_err_cnt;
+	u32     serr_cnt;
+	u32     rxd_t_code_err_cnt[16];
+	u32     txd_t_code_err_cnt[16];
+	xge_hal_stats_xpak_t    stats_xpak;
+	xge_hal_xpak_counter_t  xpak_counter;
+} xge_hal_stats_sw_err_t;
+
+/**
+ * struct xge_hal_stats_device_info_t - HAL own per-device statistics.
+ *
+ * @rx_traffic_intr_cnt: TBD
+ * @tx_traffic_intr_cnt: TBD
+ * @txpic_intr_cnt: TBD
+ * @txdma_intr_cnt: TBD
+ * @txmac_intr_cnt: TBD
+ * @txxgxs_intr_cnt: TBD
+ * @rxpic_intr_cnt: TBD
+ * @rxdma_intr_cnt: TBD
+ * @rxmac_intr_cnt: TBD
+ * @rxxgxs_intr_cnt: TBD
+ * @mc_intr_cnt: TBD
+ * @not_traffic_intr_cnt: Number of times the host was interrupted
+ *                        without new completions.
+ *                        "Non-traffic interrupt counter".
+ * @not_xge_intr_cnt: TBD
+ * @traffic_intr_cnt: Number of traffic interrupts for the device.
+ * @total_intr_cnt: Total number of traffic interrupts for the device.
+ *                  @total_intr_cnt == @traffic_intr_cnt +
+ *                              @not_traffic_intr_cnt
+ * @soft_reset_cnt: Number of times soft reset is done on this device.
+ * @rxufca_hi_adjust_cnt: TODO
+ * @rxufca_lo_adjust_cnt: TODO
+ * @bimodal_hi_adjust_cnt: TODO
+ * @bimodal_lo_adjust_cnt: TODO
+ *
+ * @tot_frms_lroised: TBD
+ * @tot_lro_sessions: TBD
+ * @lro_frm_len_exceed_cnt: TBD
+ * @lro_sg_exceed_cnt: TBD
+ * @lro_out_of_seq_pkt_cnt: TBD
+ * @lro_dup_pkt_cnt: TBD
+ *
+ * HAL per-device statistics.
+ * See also: xge_hal_stats_channel_info_t{}.
+ */
+typedef struct xge_hal_stats_device_info_t {
+	u32				rx_traffic_intr_cnt;
+	u32				tx_traffic_intr_cnt;
+	u32				txpic_intr_cnt;
+	u32				txdma_intr_cnt;
+	u32				pfc_err_cnt;
+	u32				tda_err_cnt;
+	u32				pcc_err_cnt;
+	u32				tti_err_cnt;
+	u32				lso_err_cnt;
+	u32				tpa_err_cnt;
+	u32				sm_err_cnt;
+	u32				txmac_intr_cnt;
+	u32				mac_tmac_err_cnt;
+	u32				txxgxs_intr_cnt;
+	u32				xgxs_txgxs_err_cnt;
+	u32				rxpic_intr_cnt;
+	u32				rxdma_intr_cnt;
+	u32				rc_err_cnt;
+	u32				rpa_err_cnt;
+	u32				rda_err_cnt;
+	u32				rti_err_cnt;
+	u32				rxmac_intr_cnt;
+	u32				mac_rmac_err_cnt;
+	u32				rxxgxs_intr_cnt;
+	u32				xgxs_rxgxs_err_cnt;
+	u32				mc_intr_cnt;
+	u32				not_traffic_intr_cnt;
+	u32				not_xge_intr_cnt;
+	u32				traffic_intr_cnt;
+	u32				total_intr_cnt;
+	u32				soft_reset_cnt;
+	u32				rxufca_hi_adjust_cnt;
+	u32				rxufca_lo_adjust_cnt;
+	u32				bimodal_hi_adjust_cnt;
+	u32				bimodal_lo_adjust_cnt;
+#ifdef XGE_HAL_CONFIG_LRO
+	u32				tot_frms_lroised;
+	u32				tot_lro_sessions;
+	u32				lro_frm_len_exceed_cnt;
+	u32				lro_sg_exceed_cnt;
+	u32				lro_out_of_seq_pkt_cnt;
+	u32				lro_dup_pkt_cnt;
+#endif
+} xge_hal_stats_device_info_t;
+
+#ifdef XGEHAL_RNIC
+
+/**
+ * struct xge_hal_vp_statistics_t - Virtual Path Statistics
+ *
+ * @no_nces: Number of NCEs on Adapter in this VP
+ * @no_sqs: Number of SQs on Adapter in this VP
+ * @no_srqs: Number of SRQs on Adapter in this VP
+ * @no_cqrqs: Number of CQRQs on Adapter in this VP
+ * @no_tcp_sessions: Number of TCP sessions on Adapter in this VP
+ * @no_lro_sessions: Number of LRO sessions on Adapter in this VP
+ * @no_spdm_sessions: Number of SPDM sessions on Adapter in this VP
+ *
+ * This structure contains fields to keep statistics of virtual path
+ */
+typedef struct xge_hal_vp_statistics_t {
+	u32				no_nces;
+	u32				no_sqs;
+	u32				no_srqs;
+	u32				no_cqrqs;
+	u32				no_tcp_sessions;
+	u32				no_lro_sessions;
+	u32				no_spdm_sessions;
+}xge_hal_vp_statistics_t;
+
+#endif
+
+
+/* ========================== XFRAME ER STATISTICS ======================== */
+#define XGE_HAL_MAC_LINKS	3
+#define XGE_HAL_MAC_AGGREGATORS	2
+#define XGE_HAL_VPATHS		17
+/**
+ * struct xge_hal_stats_link_info_t - XGMAC statistics for a link
+ *
+ * @tx_frms: Count of transmitted MAC frames for mac the link.
+ * @tx_ttl_eth_octets: Count of total octets of transmitted frames
+ * for mac the link.
+ * @tx_data_octets: Count of data and padding octets of transmitted
+ * frames for mac the link.
+ * @tx_mcst_frms: Count of multicast MAC frames for mac the link.
+ * @tx_bcst_frms: Count of broadcast MAC frames for mac the link.
+ * @tx_ucst_frms: Count of unicast MAC frames for mac the link.
+ * @tx_tagged_frms: Count of transmitted frames containing a VLAN tag
+ * for mac the link.
+ * @tx_vld_ip: Count of transmitted IP datagrams for mac the link.
+ * @tx_vld_ip_octets: Count of transmitted IP octets for mac the link.
+ * @tx_icmp: Count of transmitted ICMP messages for mac the link.
+ * @tx_tcp: Count of transmitted TCP segments for mac the link.
+ * @tx_rst_tcp: Count of transmitted TCP segments containing the RST
+ * flag mac the link.
+ * @tx_udp: Count of transmitted UDP datagrams for mac the link.
+ * @tx_unknown_protocol: Count of transmitted packets of unknown
+ * protocol for mac the link.
+ * @tx_parse_error: Count of transmitted packets with parsing errors
+ * for mac the link.
+ * @tx_pause_ctrl_frms: Count of MAC PAUSE control frames for mac
+ * the link.
+ * @tx_lacpdu_frms: Count of LACPDUs transmitted for mac the link.
+ * @tx_marker_pdu_frms: Count of Marker PDUs transmitted for mac the
+ * link.
+ * @tx_marker_resp_pdu_frms: Count of Marker Response PDUs transmitted
+ * for mac the link.
+ * @tx_drop_ip: Count of dropped IP packets from the transmission path
+ * for mac the link.
+ * @tx_xgmii_char1_match: Count of the number of transmitted XGMII
+ * characters that match first pattern, for mac the link.
+ * @tx_xgmii_char2_match: Count of the number of transmitted XGMII
+ * characters that match second pattern, for mac the link.
+ * @tx_xgmii_column1_match: Count of the number of transmitted XGMII
+ * columns that match first pattern, for mac the link.
+ * @tx_xgmii_column2_match: Count of the number of transmitted XGMII
+ * columns that match second pattern, for mac the link.
+ * @tx_drop_frms: Count of frames dropped due to internal errors during
+ * transmission for mac the link.
+ * @tx_any_err_frms: Count of frames dropped due to any error during
+ * transmission for mac the link.
+ * @rx_ttl_frms: Count of all received MAC frames for mac the link.
+ * @rx_vld_frms: Count of all successfully received MAC frames for mac
+ * the link.
+ * @rx_offld_frms: Count of all offloaded received MAC frames for mac
+ * the link.
+ * @rx_ttl_eth_octets: Count of total octets of received frames, not
+ * including framing characters for mac the link.
+ * @rx_data_octets: Count of data and padding octets of successfully
+ * received frames for mac the link.
+ * @rx_offld_octets: Count of total octets, not including framing
+ * characters, of offloaded received frames for mac the link.
+ * @rx_vld_mcst_frms: Count of successfully received multicast MAC
+ * frames for mac the link.
+ * @rx_vld_bcst_frms: Count of successfully received broadcast MAC
+ * frames for mac the link.
+ * @rx_accepted_ucst_frms: Count of successfully received unicast MAC
+ * frames for mac the link.
+ * @rx_accepted_nucst_frms: Count of successfully received non-unicast
+ * MAC frames for mac the link.
+ * @rx_tagged_frms: Count of received frames containing a VLAN tag for
+ * mac the link.
+ * @rx_long_frms: Count of received frames that are longer than
+ * RX_MAX_PYLD_LEN + 18 bytes (+ 22 bytes if VLAN-tagged) for mac the link.
+ * @rx_usized_frms: Count of received frames of length less than 64
+ * octets, for mac the link.
+ * @rx_osized_frms:  Count of received frames of length more than 1518
+ * octets for mac the link.
+ * @rx_frag_frms:  Count of received frames of length less than 64
+ * octets that had bad FCS, for mac the link.
+ * @rx_jabber_frms:  Count of received frames of length more than 1518
+ * octets that had bad FCS, for mac the link.
+ * @rx_ttl_64_frms: Count of all received MAC frames with length of
+ * exactly 64 octets, for mac the link.
+ * @rx_ttl_65_127_frms: Count of all received MAC frames with length
+ * of between 65 and 127 octets inclusive, for mac the link.
+ * @rx_ttl_128_255_frms: Count of all received MAC frames with length
+ * of between 128 and 255 octets inclusive, for mac the link.
+ * @rx_ttl_256_511_frms: Count of all received MAC frames with length
+ * of between 246 and 511 octets inclusive, for mac the link.
+ * @rx_ttl_512_1023_frms: Count of all received MAC frames with length
+ * of between 512 and 1023 octets inclusive, for mac the link.
+ * @rx_ttl_1024_1518_frms: Count of all received MAC frames with length
+ * of between 1024 and 1518 octets inclusive, for mac the link.
+ * @rx_ttl_1519_4095_frms: Count of all received MAC frames with length
+ * of between 1519 and 4095 octets inclusive, for mac the link.
+ * @rx_ttl_40956_8191_frms: Count of all received MAC frames with length
+ * of between 4096 and 8191 octets inclusive, for mac the link.
+ * @rx_ttl_8192_max_frms: Count of all received MAC frames with length
+ * of between 8192 and RX_MAX_PYLD_LEN+18 octets inclusive, for mac the link.
+ * @rx_ttl_gt_max_frms: Count of all received MAC frames with length
+ * exceeding RX_MAX_PYLD_LEN+18 octets inclusive, for mac the link.
+ * @rx_ip:  Count of received IP datagrams, for mac the link.
+ * @rx_accepted_ip:  Count of received  and accepted IP datagrams,
+ * for mac the link.
+ * @rx_ip_octets: Count of number of octets in received IP datagrams,
+ * for mac the link.
+ * @rx_hdr_err_ip: Count of received IP datagrams that are discarded
+ * due to IP header errors, for mac the link.
+ * @rx_icmp: Count of received ICMP messages for mac the link.
+ * @rx_tcp: Count of received TCP segments for mac the link.
+ * @rx_udp: Count of received UDP datagrams for mac the link.
+ * @rx_err_tcp: Count of received TCP segments containing errors for
+ * mac the link.
+ * @rx_pause_cnt: Count of number of pause quanta that the MAC has
+ * been in the paused state, for mac the link.
+ * @rx_pause_ctrl_frms: Count of received MAC PAUSE control frames for
+ * mac the link.
+ * @rx_unsup_ctrl_frms: Count of received MAC control frames that do
+ * not contain the PAUSE opcode for mac the link.
+ * @rx_fcs_err_frms: Count of received MAC frames that do not pass FCS
+ * for mac the link.
+ * @rx_in_rng_len_err_frms: Count of received frames with a length/type
+ * field value between 46 and 1500 inclusive, that does not match the number
+ * of data octets received, for mac the link.
+ * @rx_out_rng_len_err_frms: Count of received frames with length/type
+ * field between 1501 and 1535 decimal, inclusive. for mac the link.
+ * @rx_drop_frms: Count of dropped frames from receive path for mac
+ * the link.
+ * @rx_discarded_frms: Count of discarded frames from receive path for
+ * mac the link.
+ * @rx_drop_ip: Count of droppen IP datagrams from receive path for
+ * mac the link.
+ * @rx_err_drp_udp: Count of droppen UDP datagrams from receive path
+ * for mac the link.
+ * @rx_lacpdu_frms: Count of valid LACPDUs received for mac the link.
+ * @rx_marker_pdu_frms: Count of valid Marker PDUs received for mac
+ * the link.
+ * @rx_marker_resp_pdu_frms: Count of valid Marker Response PDUs
+ * received for mac the link.
+ * @rx_unknown_pdu_frms: Count of unknown PDUs received for mac the link.
+ * @rx_illegal_pdu_frms: Count of illegal PDUs received for mac the link.
+ * @rx_fcs_discard: Count of discarded PDUs received for mac the link.
+ * @rx_len_discard: Count of received frames that were discarded
+ * because of an invalid frame length, for mac the link.
+ * @rx_len_discard: Count of received frames that were discarded
+ * because of an invalid destination MAC address, for mac the link.
+ * @rx_pf_discard: Count of received frames that were discarded for
+ * mac the link.
+ * @rx_trash_discard: Count of received frames that were steered to the
+ * trash queue for mac the link.
+ * @rx_rts_discard: Count of received frames that were discarded by RTS
+ * logic for mac the link.
+ * @rx_wol_discard: Count of received frames that were discarded by WOL
+ * logic for mac the link.
+ * @rx_red_discard: Count of received frames that were discarded by RED
+ * logic for mac the link.
+ * @rx_ingm_full_discard: Count of received frames that were discarded
+ * because the internal ingress memory was full for mac the link.
+ * @rx_xgmii_data_err_cnt: Count of unexpected control characters
+ * during normal data transmission for mac the link.
+ * @rx_xgmii_ctrl_err_cnt: Count of unexpected or misplaced control
+ * characters occuring between times of normal data transmission for mac
+ * the link.
+ * @rx_xgmii_err_sym: Count of the number of symbol errors in the
+ * received XGMII data for mac the link.
+ * @rx_xgmii_char1_match: Count of the number of XGMII characters
+ * that match first pattern defined in MAC_STATS_RX_XGMII_CHAR_LINK_N.
+ * @rx_xgmii_char2_match: Count of the number of XGMII characters
+ * that match second pattern defined in MAC_STATS_RX_XGMII_CHAR_LINK_N.
+ * @rx_xgmii_column1_match: Count of the number of XGMII columns
+ * that match a pattern defined in MAC_STATS_RX_XGMII_COLUMN1_LINK_N.
+ * @rx_xgmii_column2_match: Count of the number of XGMII columns
+ * that match a pattern defined in MAC_STATS_RX_XGMII_COLUMN1_LINK_N.
+ * @rx_local_fault: Count of the number of local faults for mac the link.
+ * @rx_remote_fault: Count of the number of remote faults for mac the
+ * link.
+ * @rx_queue_full: Count of the number of frame destined for a full
+ * queue for mac the link.
+ */
+typedef struct xge_hal_stats_link_info_t {
+	u64	tx_frms;
+	u64	tx_ttl_eth_octets;
+	u64	tx_data_octets;
+	u64	tx_mcst_frms;
+	u64	tx_bcst_frms;
+	u64	tx_ucst_frms;
+	u64	tx_tagged_frms;
+	u64	tx_vld_ip;
+	u64	tx_vld_ip_octets;
+	u64	tx_icmp;
+	u64	tx_tcp;
+	u64	tx_rst_tcp;
+	u64	tx_udp;
+	u64	tx_unknown_protocol;
+	u64	tx_parse_error;
+	u64	tx_pause_ctrl_frms;
+	u64	tx_lacpdu_frms;
+	u64	tx_marker_pdu_frms;
+	u64	tx_marker_resp_pdu_frms;
+	u64	tx_drop_ip;
+	u64	tx_xgmii_char1_match;
+	u64	tx_xgmii_char2_match;
+	u64	tx_xgmii_column1_match;
+	u64	tx_xgmii_column2_match;
+	u64	tx_drop_frms;
+	u64	tx_any_err_frms;
+	u64	rx_ttl_frms;
+	u64	rx_vld_frms;
+	u64	rx_offld_frms;
+	u64	rx_ttl_eth_octets;
+	u64	rx_data_octets;
+	u64	rx_offld_octets;
+	u64	rx_vld_mcst_frms;
+	u64	rx_vld_bcst_frms;
+	u64	rx_accepted_ucst_frms;
+	u64	rx_accepted_nucst_frms;
+	u64	rx_tagged_frms;
+	u64	rx_long_frms;
+	u64	rx_usized_frms;
+	u64	rx_osized_frms;
+	u64	rx_frag_frms;
+	u64	rx_jabber_frms;
+	u64	rx_ttl_64_frms;
+	u64	rx_ttl_65_127_frms;
+	u64	rx_ttl_128_255_frms;
+	u64	rx_ttl_256_511_frms;
+	u64	rx_ttl_512_1023_frms;
+	u64	rx_ttl_1024_1518_frms;
+	u64	rx_ttl_1519_4095_frms;
+	u64	rx_ttl_40956_8191_frms;
+	u64	rx_ttl_8192_max_frms;
+	u64	rx_ttl_gt_max_frms;
+	u64	rx_ip;
+	u64	rx_ip_octets;
+	u64	rx_hdr_err_ip;
+	u64	rx_icmp;
+	u64	rx_tcp;
+	u64	rx_udp;
+	u64	rx_err_tcp;
+	u64	rx_pause_cnt;
+	u64	rx_pause_ctrl_frms;
+	u64	rx_unsup_ctrl_frms;
+	u64	rx_in_rng_len_err_frms;
+	u64	rx_out_rng_len_err_frms;
+	u64	rx_drop_frms;
+	u64	rx_discarded_frms;
+	u64	rx_drop_ip;
+	u64	rx_err_drp_udp;
+	u64	rx_lacpdu_frms;
+	u64	rx_marker_pdu_frms;
+	u64	rx_marker_resp_pdu_frms;
+	u64	rx_unknown_pdu_frms;
+	u64	rx_illegal_pdu_frms;
+	u64	rx_fcs_discard;
+	u64	rx_len_discard;
+	u64	rx_pf_discard;
+	u64	rx_trash_discard;
+	u64	rx_rts_discard;
+	u64	rx_wol_discard;
+	u64	rx_red_discard;
+	u64	rx_ingm_full_discard;
+	u64	rx_xgmii_data_err_cnt;
+	u64	rx_xgmii_ctrl_err_cnt;
+	u64	rx_xgmii_err_sym;
+	u64	rx_xgmii_char1_match;
+	u64	rx_xgmii_char2_match;
+	u64	rx_xgmii_column1_match;
+	u64	rx_xgmii_column2_match;
+	u64	rx_local_fault;
+	u64	rx_remote_fault;
+	u64	rx_queue_full;
+}xge_hal_stats_link_info_t;
+
+/**
+ * struct xge_hal_stats_aggr_info_t - XGMAC statistics for an aggregator
+ *
+ * @tx_frms: Count of data frames transmitted for the aggregator.
+ * @tx_mcst_frms: Count of multicast data frames transmitted for
+ * the aggregator.
+ * @tx_bcst_frms: Count of broadcast data frames transmitted for
+ * the aggregator.
+ * @tx_discarded_frms: Count of discarded data frames transmitted for
+ * the aggregator.
+ * @tx_errored_frms: Count of errored data frames transmitted for
+ * the aggregator.
+ * @rx_frms: Count of received frames for aggregators
+ * @rx_data_octets: Count of data and padding octets of frames received
+ * the aggregator.
+ * @rx_mcst_frms: Count of multicast frames received the aggregator.
+ * @rx_bcst_frms: Count of broadast frames received the aggregator.
+ * @rx_discarded_frms: Count of discarded frames received the aggregator.
+ * @rx_errored_frms: Count of errored frames received the aggregator.
+ * @rx_unknown_protocol_frms: Count of unknown protocol frames received
+ * the aggregator.
+*/
+typedef struct xge_hal_stats_aggr_info_t {
+	u64	tx_frms;
+	u64	tx_mcst_frms;
+	u64	tx_bcst_frms;
+	u64	tx_discarded_frms;
+	u64	tx_errored_frms;
+	u64	rx_frms;
+	u64	rx_data_octets;
+	u64	rx_mcst_frms;
+	u64	rx_bcst_frms;
+	u64	rx_discarded_frms;
+	u64	rx_errored_frms;
+	u64	rx_unknown_protocol_frms;
+}xge_hal_stats_aggr_info_t;
+
+/**
+ * struct xge_hal_stats_vpath_info_t - XGMAC statistics for a vpath.
+ *
+ * @tx_frms: Count of transmitted MAC frames for the vpath.
+ * @tx_ttl_eth_octets: Count of total octets of transmitted frames
+ * for the vpath.
+ * @tx_data_octets: Count of data and padding octets of transmitted
+ * frames for the vpath.
+ * @tx_mcst_frms: Count of multicast MAC frames for the vpath.
+ * @tx_bcst_frms: Count of broadcast MAC frames for the vpath.
+ * @tx_ucst_frms: Count of unicast MAC frames for the vpath.
+ * @tx_tagged_frms: Count of transmitted frames containing a VLAN
+ * tag for the vpath.
+ * @tx_vld_ip: Count of transmitted IP datagrams for the vpath.
+ * @tx_vld_ip_octets: Count of transmitted IP octets for the vpath.
+ * @tx_icmp: Count of transmitted ICMP messages for the vpath.
+ * @tx_tcp: Count of transmitted TCP segments for the vpath.
+ * @tx_rst_tcp: Count of transmitted TCP segments containing the RST
+ * flag the vpath.
+ * @tx_udp: Count of transmitted UDP datagrams for the vpath.
+ * @tx_unknown_protocol: Count of transmitted packets of unknown
+ * protocol for the vpath.
+ * @tx_parse_error: Count of transmitted packets with parsing errors
+ * for the vpath.
+ * @rx_ttl_frms: Count of all received MAC frames for the vpath.
+ * @rx_vld_frms: Count of all successfully received MAC frames for
+ * the vpath.
+ * @rx_offld_frms: Count of all offloaded received MAC frames for
+ * the vpath.
+ * @rx_ttl_eth_octets: Count of total octets of received frames, not
+ * including framing characters for the vpath.
+ * @rx_data_octets: Count of data and padding octets of successfully
+ * received frames for the vpath.
+ * @rx_offld_octets: Count of total octets, not including framing
+ * characters, of offloaded received frames for the vpath.
+ * @rx_vld_mcst_frms: Count of successfully received multicast MAC
+ * frames for the vpath.
+ * @rx_vld_bcst_frms: Count of successfully received broadcast MAC
+ * frames for the vpath.
+ * @rx_accepted_ucst_frms: Count of successfully received unicast
+ * MAC frames for the vpath.
+ * @rx_accepted_nucst_frms: Count of successfully received
+ * non-unicast MAC frames for the vpath.
+ * @rx_tagged_frms: Count of received frames containing a VLAN tag
+ * for the vpath.
+ * @rx_long_frms: Count of received frames that are longer than
+ * RX_MAX_PYLD_LEN + 18 bytes (+ 22 bytes if VLAN-tagged) for the vpath.
+ * @rx_usized_frms: Count of received frames of length less than 64
+ * octets, for the vpath.
+ * @rx_usized_frms: Count of received frames of length more than
+ * 1518 octets, for the vpath.
+ * @rx_osized_frms:  Count of received frames of length more than
+ * 1518 octets for the vpath.
+ * @rx_frag_frms:  Count of received frames of length less than 64
+ * octets that had bad FCS, for the vpath.
+ * @rx_jabber_frms:  Count of received frames of length more than
+ * 1518 octets that had bad FCS, for the vpath.
+ * @rx_ttl_64_frms: Count of all received MAC frames with length of
+ * exactly 64 octets, for the vpath.
+ * @rx_ttl_65_127_frms: Count of all received MAC frames with length
+ * of between 65 and 127 octets inclusive, for the vpath.
+ * @rx_ttl_128_255_frms: Count of all received MAC frames with
+ * length of between 128 and 255 octets inclusive, for the vpath.
+ * @rx_ttl_256_511_frms: Count of all received MAC frames with
+ * length of between 246 and 511 octets inclusive, for the vpath.
+ * @rx_ttl_512_1023_frms: Count of all received MAC frames with
+ * length of between 512 and 1023 octets inclusive, for the vpath.
+ * @rx_ttl_1024_1518_frms: Count of all received MAC frames with
+ * length of between 1024 and 1518 octets inclusive, for the vpath.
+ * @rx_ttl_1519_4095_frms: Count of all received MAC frames with
+ * length of between 1519 and 4095 octets inclusive, for the vpath.
+ * @rx_ttl_40956_8191_frms: Count of all received MAC frames with
+ * of between 4096 and 8191 octets inclusive, for the vpath.
+ * @rx_ttl_8192_max_frms: Count of all received MAC frames with
+ * length of between 8192 and RX_MAX_PYLD_LEN+18 octets inclusive, for the
+ * vpath.
+ * @rx_ttl_gt_max_frms: Count of all received MAC frames with length
+ * exceeding RX_MAX_PYLD_LEN+18 octets inclusive, for the vpath.
+ * @rx_ip:  Count of received IP datagrams, for the vpath.
+ * @rx_accepted_ip: Count of received  and accepted IP datagrams,
+ * for the vpath.
+ * @rx_ip_octets: Count of number of octets in received IP datagrams
+ * for the vpath.
+ * @rx_hdr_err_ip: Count of received IP datagrams that are discarded
+ * due to IP header errors, for the vpath.
+ * @rx_icmp: Count of received ICMP messages for the vpath.
+ * @rx_tcp: Count of received TCP segments for the vpath.
+ * @rx_udp: Count of received UDP datagrams for the vpath.
+ * @rx_err_tcp: Count of received TCP segments containing errors for
+ * the vpath.
+ * @rx_mpa_ok_frms: Count of received frames that pass the MPA
+ * checks for vptah.
+ * @rx_mpa_crc_fail_frms: Count of received frames that fail the MPA
+ * CRC check for the vpath.
+ * @rx_mpa_mrk_fail_frms: Count of received frames that fail the
+ * MPA marker check for the vpath.
+ * @rx_mpa_len_fail_frms: Count of received frames that fail the MPA
+ * length check for the vpath.
+ * @rx_wol_frms: Count of received "magic packet" frames for
+ * the vpath.
+ */
+typedef struct xge_hal_stats_vpath_info_t {
+	u64	tx_frms;
+	u64	tx_ttl_eth_octets;
+	u64	tx_data_octets;
+	u64	tx_mcst_frms;
+	u64	tx_bcst_frms;
+	u64	tx_ucst_frms;
+	u64	tx_tagged_frms;
+	u64	tx_vld_ip;
+	u64	tx_vld_ip_octets;
+	u64	tx_icmp;
+	u64	tx_tcp;
+	u64	tx_rst_tcp;
+	u64	tx_udp;
+	u64	tx_unknown_protocol;
+	u64	tx_parse_error;
+	u64	rx_ttl_frms;
+	u64	rx_vld_frms;
+	u64	rx_offld_frms;
+	u64	rx_ttl_eth_octets;
+	u64	rx_data_octets;
+	u64	rx_offld_octets;
+	u64	rx_vld_mcst_frms;
+	u64	rx_vld_bcst_frms;
+	u64	rx_accepted_ucst_frms;
+	u64	rx_accepted_nucst_frms;
+	u64	rx_tagged_frms;
+	u64	rx_long_frms;
+	u64	rx_usized_frms;
+	u64	rx_osized_frms;
+	u64	rx_frag_frms;
+	u64	rx_jabber_frms;
+	u64	rx_ttl_64_frms;
+	u64	rx_ttl_65_127_frms;
+	u64	rx_ttl_128_255_frms;
+	u64	rx_ttl_256_511_frms;
+	u64	rx_ttl_512_1023_frms;
+	u64	rx_ttl_1024_1518_frms;
+	u64	rx_ttl_1519_4095_frms;
+	u64	rx_ttl_40956_8191_frms;
+	u64	rx_ttl_8192_max_frms;
+	u64	rx_ttl_gt_max_frms;
+	u64	rx_ip;
+	u64	rx_accepted_ip;
+	u64	rx_ip_octets;
+	u64	rx_hdr_err_ip;
+	u64	rx_icmp;
+	u64	rx_tcp;
+	u64	rx_udp;
+	u64	rx_err_tcp;
+	u64	rx_mpa_ok_frms;
+	u64	rx_mpa_crc_fail_frms;
+	u64	rx_mpa_mrk_fail_frms;
+	u64	rx_mpa_len_fail_frms;
+	u64	rx_wol_frms;
+}xge_hal_stats_vpath_info_t;
+
+/**
+ * struct xge_hal_stats_pcim_info_t - Contains PCIM statistics
+ *
+ * @link_info: PCIM links info for link 0, 1, and 2.
+ * @aggr_info: PCIM aggregators info for aggregator 0 and 1.
+ * See also: xge_hal_stats_link_info_t{}, xge_hal_stats_aggr_info_t{}.
+ */
+typedef struct xge_hal_stats_pcim_info_t {
+	xge_hal_stats_link_info_t	link_info[XGE_HAL_MAC_LINKS];
+	xge_hal_stats_aggr_info_t	aggr_info[XGE_HAL_MAC_AGGREGATORS];
+}xge_hal_stats_pcim_info_t;
+
+/**
+ * struct xge_hal_stats_t - Contains HAL per-device statistics,
+ * including hw.
+ * @devh: HAL device handle.
+ * @dma_addr: DMA addres of the %hw_info. Given to device to fill-in the stats.
+ * @hw_info_dmah: DMA handle used to map hw statistics onto the device memory
+ *                space.
+ * @hw_info_dma_acch: One more DMA handle used subsequently to free the
+ *                    DMA object. Note that this and the previous handle have
+ *                    physical meaning for Solaris; on Windows and Linux the
+ *                    corresponding value will be simply pointer to PCI device.
+ *
+ * @hw_info: Xframe statistics maintained by the hardware.
+ * @hw_info_saved: TBD
+ * @hw_info_latest: TBD
+ * @pcim_info: Xframe PCIM statistics maintained by the hardware.
+ * @pcim_info_saved: TBD
+ * @pcim_info_latest: TBD
+ * @sw_dev_info_stats: HAL's "soft" device informational statistics, e.g. number
+ *                     of completions per interrupt.
+ * @sw_dev_err_stats: HAL's "soft" device error statistics.
+ *
+ * @is_initialized: True, if all the subordinate structures are allocated and
+ *                  initialized.
+ * @is_enabled: True, if device stats collection is enabled.
+ *
+ * Structure-container of HAL per-device statistics. Note that per-channel
+ * statistics are kept in separate structures under HAL's fifo and ring
+ * channels.
+ * See also: xge_hal_stats_hw_info_t{}, xge_hal_stats_sw_err_t{},
+ * xge_hal_stats_device_info_t{}.
+ * See also: xge_hal_stats_channel_info_t{}.
+ */
+typedef struct xge_hal_stats_t {
+        /* handles */
+	xge_hal_device_h		devh;
+	dma_addr_t			dma_addr;
+	pci_dma_h			hw_info_dmah;
+	pci_dma_acc_h			hw_info_dma_acch;
+
+        /* HAL device hardware statistics */
+	xge_hal_stats_hw_info_t		*hw_info;
+	xge_hal_stats_hw_info_t		hw_info_saved;
+	xge_hal_stats_hw_info_t		hw_info_latest;
+
+	/* HAL device hardware statistics for XFRAME ER */
+	xge_hal_stats_pcim_info_t	*pcim_info;
+	xge_hal_stats_pcim_info_t	*pcim_info_saved;
+	xge_hal_stats_pcim_info_t	*pcim_info_latest;
+
+        /* HAL device "soft" stats */
+	xge_hal_stats_sw_err_t          sw_dev_err_stats;
+	xge_hal_stats_device_info_t     sw_dev_info_stats;
+
+        /* flags */
+	int				is_initialized;
+	int				is_enabled;
+} xge_hal_stats_t;
+
+/* ========================== STATS PRIVATE API ========================= */
+
+xge_hal_status_e __hal_stats_initialize(xge_hal_stats_t *stats,
+			xge_hal_device_h devh);
+
+void __hal_stats_terminate(xge_hal_stats_t *stats);
+
+void __hal_stats_enable(xge_hal_stats_t *stats);
+
+void __hal_stats_disable(xge_hal_stats_t *stats);
+
+void __hal_stats_soft_reset(xge_hal_device_h devh, int reset_all);
+
+/* ========================== STATS PUBLIC API ========================= */
+
+xge_hal_status_e xge_hal_stats_hw(xge_hal_device_h devh,
+			xge_hal_stats_hw_info_t	**hw_info);
+
+xge_hal_status_e xge_hal_stats_pcim(xge_hal_device_h devh,
+			xge_hal_stats_pcim_info_t	**pcim_info);
+
+xge_hal_status_e xge_hal_stats_device(xge_hal_device_h devh,
+			xge_hal_stats_device_info_t **device_info);
+
+xge_hal_status_e xge_hal_stats_channel(xge_hal_channel_h channelh,
+			xge_hal_stats_channel_info_t **channel_info);
+
+xge_hal_status_e xge_hal_stats_reset(xge_hal_device_h devh);
+
+
+__EXTERN_END_DECLS
+
+#endif /* XGE_HAL_STATS_H */
diff --git a/sys/dev/nxge/include/xgehal-types.h b/sys/dev/nxge/include/xgehal-types.h
new file mode 100644
index 0000000..ec1942b
--- /dev/null
+++ b/sys/dev/nxge/include/xgehal-types.h
@@ -0,0 +1,626 @@
+/*-
+ * Copyright (c) 2002-2007 Neterion, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ *  FileName :    xgehal-types.h
+ *
+ *  Description:  HAL commonly used types and enumerations
+ *
+ *  Created:      19 May 2004
+ */
+
+#ifndef XGE_HAL_TYPES_H
+#define XGE_HAL_TYPES_H
+
+#include <dev/nxge/include/xge-os-pal.h>
+
+__EXTERN_BEGIN_DECLS
+
+/*
+ * BIT(loc) - set bit at offset
+ */
+#define BIT(loc)		(0x8000000000000000ULL >> (loc))
+
+/*
+ * vBIT(val, loc, sz) - set bits at offset
+ */
+#define vBIT(val, loc, sz)	(((u64)(val)) << (64-(loc)-(sz)))
+#define vBIT32(val, loc, sz)	(((u32)(val)) << (32-(loc)-(sz)))
+
+/*
+ * bVALx(bits, loc) - Get the value of x bits at location
+ */
+#define bVAL1(bits, loc)	((((u64)bits) >> (64-(loc+1))) & 0x1)
+#define bVAL2(bits, loc)	((((u64)bits) >> (64-(loc+2))) & 0x3)
+#define bVAL3(bits, loc)	((((u64)bits) >> (64-(loc+3))) & 0x7)
+#define bVAL4(bits, loc)	((((u64)bits) >> (64-(loc+4))) & 0xF)
+#define bVAL5(bits, loc)	((((u64)bits) >> (64-(loc+5))) & 0x1F)
+#define bVAL6(bits, loc)	((((u64)bits) >> (64-(loc+6))) & 0x3F)
+#define bVAL7(bits, loc)	((((u64)bits) >> (64-(loc+7))) & 0x7F)
+#define bVAL8(bits, loc)	((((u64)bits) >> (64-(loc+8))) & 0xFF)
+#define bVAL12(bits, loc)	((((u64)bits) >> (64-(loc+12))) & 0xFFF)
+#define bVAL14(bits, loc)	((((u64)bits) >> (64-(loc+14))) & 0x3FFF)
+#define bVAL16(bits, loc)	((((u64)bits) >> (64-(loc+16))) & 0xFFFF)
+#define bVAL20(bits, loc)	((((u64)bits) >> (64-(loc+20))) & 0xFFFFF)
+#define bVAL22(bits, loc)	((((u64)bits) >> (64-(loc+22))) & 0x3FFFFF)
+#define bVAL24(bits, loc)	((((u64)bits) >> (64-(loc+24))) & 0xFFFFFF)
+#define bVAL28(bits, loc)	((((u64)bits) >> (64-(loc+28))) & 0xFFFFFFF)
+#define bVAL32(bits, loc)	((((u64)bits) >> (64-(loc+32))) & 0xFFFFFFFF)
+#define bVAL36(bits, loc)	((((u64)bits) >> (64-(loc+36))) & 0xFFFFFFFFF)
+#define bVAL40(bits, loc)	((((u64)bits) >> (64-(loc+40))) & 0xFFFFFFFFFF)
+#define bVAL44(bits, loc)	((((u64)bits) >> (64-(loc+44))) & 0xFFFFFFFFFFF)
+#define bVAL48(bits, loc)	((((u64)bits) >> (64-(loc+48))) & 0xFFFFFFFFFFFF)
+#define bVAL52(bits, loc)	((((u64)bits) >> (64-(loc+52))) & 0xFFFFFFFFFFFFF)
+#define bVAL56(bits, loc)	((((u64)bits) >> (64-(loc+56))) & 0xFFFFFFFFFFFFFF)
+#define bVAL60(bits, loc)	((((u64)bits) >> (64-(loc+60))) & 0xFFFFFFFFFFFFFFF)
+
+#define XGE_HAL_BASE_INF		100
+#define XGE_HAL_BASE_ERR		200
+#define XGE_HAL_BASE_BADCFG	        300
+
+#define XGE_HAL_ALL_FOXES   0xFFFFFFFFFFFFFFFFULL
+
+/**
+ * enum xge_hal_status_e - HAL return codes.
+ * @XGE_HAL_OK: Success.
+ * @XGE_HAL_FAIL: Failure.
+ * @XGE_HAL_COMPLETIONS_REMAIN: There are more completions on a channel.
+ *      (specific to polling mode completion processing).
+ * @XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS: No more completed
+ * descriptors. See xge_hal_fifo_dtr_next_completed().
+ * @XGE_HAL_INF_OUT_OF_DESCRIPTORS: Out of descriptors. Channel
+ * descriptors
+ *           are reserved (via xge_hal_fifo_dtr_reserve(),
+ *           xge_hal_fifo_dtr_reserve())
+ *           and not yet freed (via xge_hal_fifo_dtr_free(),
+ *           xge_hal_ring_dtr_free()).
+ * @XGE_HAL_INF_CHANNEL_IS_NOT_READY: Channel is not ready for
+ * operation.
+ * @XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING: Indicates that host needs to
+ * poll until PIO is executed.
+ * @XGE_HAL_INF_STATS_IS_NOT_READY: Cannot retrieve statistics because
+ * HAL and/or device is not yet initialized.
+ * @XGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS: No descriptors left to
+ * reserve. Internal use only.
+ * @XGE_HAL_INF_IRQ_POLLING_CONTINUE: Returned by the ULD channel
+ * callback when instructed to exit descriptor processing loop
+ * prematurely. Typical usage: polling mode of processing completed
+ * descriptors.
+ *           Upon getting LRO_ISED, ll driver shall
+ *           1) initialise lro struct with mbuf if sg_num == 1.
+ *           2) else it will update m_data_ptr_of_mbuf to tcp pointer and
+ *           append the new mbuf to the tail of mbuf chain in lro struct.
+ *
+ * @XGE_HAL_INF_LRO_BEGIN: Returned by ULD LRO module, when new LRO is
+ * being initiated.
+ * @XGE_HAL_INF_LRO_CONT: Returned by ULD LRO module, when new frame
+ * is appended at the end of existing LRO.
+ * @XGE_HAL_INF_LRO_UNCAPABLE: Returned by ULD LRO module, when new
+ * frame is not LRO capable.
+ * @XGE_HAL_INF_LRO_END_1: Returned by ULD LRO module, when new frame
+ * triggers LRO flush.
+ * @XGE_HAL_INF_LRO_END_2: Returned by ULD LRO module, when new
+ * frame triggers LRO flush. Lro frame should be flushed first then
+ * new frame should be flushed next.
+ * @XGE_HAL_INF_LRO_END_3: Returned by ULD LRO module, when new
+ * frame triggers close of current LRO session and opening of new LRO session
+ * with the frame.
+ * @XGE_HAL_INF_LRO_SESSIONS_XCDED: Returned by ULD LRO module, when no
+ * more LRO sessions can be added.
+ * @XGE_HAL_INF_NOT_ENOUGH_HW_CQES: TBD
+ * @XGE_HAL_ERR_DRIVER_NOT_INITIALIZED: HAL is not initialized.
+ * @XGE_HAL_ERR_OUT_OF_MEMORY: Out of memory (example, when and
+ * allocating descriptors).
+ * @XGE_HAL_ERR_CHANNEL_NOT_FOUND: xge_hal_channel_open will return this
+ * error if corresponding channel is not configured.
+ * @XGE_HAL_ERR_WRONG_IRQ: Returned by HAL's ISR when the latter is
+ * invoked not because of the Xframe-generated interrupt.
+ * @XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES: Returned when user tries to
+ * configure more than XGE_HAL_MAX_MAC_ADDRESSES  mac addresses.
+ * @XGE_HAL_ERR_BAD_DEVICE_ID: Unknown device PCI ID.
+ * @XGE_HAL_ERR_OUT_ALIGNED_FRAGS: Too many unaligned fragments
+ * in a scatter-gather list.
+ * @XGE_HAL_ERR_DEVICE_NOT_INITIALIZED: Device is not initialized.
+ * Typically means wrong sequence of API calls.
+ * @XGE_HAL_ERR_SWAPPER_CTRL: Error during device initialization: failed
+ * to set Xframe byte swapper in accordnace with the host
+ * endian-ness.
+ * @XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT: Failed to restore the device to
+ * a "quiescent" state.
+ * @XGE_HAL_ERR_INVALID_MTU_SIZE: Returned when MTU size specified by
+ * caller is not in the (64, 9600) range.
+ * @XGE_HAL_ERR_OUT_OF_MAPPING: Failed to map DMA-able memory.
+ * @XGE_HAL_ERR_BAD_SUBSYSTEM_ID: Bad PCI subsystem ID. (Currently we
+ * check for zero/non-zero only.)
+ * @XGE_HAL_ERR_INVALID_BAR_ID: Invalid BAR ID. Xframe supports two Base
+ * Address Register Spaces: BAR0 (id=0) and BAR1 (id=1).
+ * @XGE_HAL_ERR_INVALID_OFFSET: Invalid offset. Example, attempt to read
+ * register value (with offset) outside of the BAR0 space.
+ * @XGE_HAL_ERR_INVALID_DEVICE: Invalid device. The HAL device handle
+ * (passed by ULD) is invalid.
+ * @XGE_HAL_ERR_OUT_OF_SPACE: Out-of-provided-buffer-space. Returned by
+ * management "get" routines when the retrieved information does
+ * not fit into the provided buffer.
+ * @XGE_HAL_ERR_INVALID_VALUE_BIT_SIZE: Invalid bit size.
+ * @XGE_HAL_ERR_VERSION_CONFLICT: Upper-layer driver and HAL (versions)
+ * are not compatible.
+ * @XGE_HAL_ERR_INVALID_MAC_ADDRESS: Invalid MAC address.
+ * @XGE_HAL_ERR_SPDM_NOT_ENABLED: SPDM support is not enabled.
+ * @XGE_HAL_ERR_SPDM_TABLE_FULL: SPDM table is full.
+ * @XGE_HAL_ERR_SPDM_INVALID_ENTRY: Invalid SPDM entry.
+ * @XGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND: Unable to locate the entry in the
+ * SPDM table.
+ * @XGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT: Local SPDM table is not in
+ * synch ith the actual one.
+ * @XGE_HAL_ERR_INVALID_PCI_INFO: Invalid or unrecognized PCI frequency,
+ * and or width, and or mode (Xframe-II only, see UG on PCI_INFO register).
+ * @XGE_HAL_ERR_CRITICAL: Critical error. Returned by HAL APIs
+ * (including xge_hal_device_handle_tcode()) on: ECC, parity, SERR.
+ * Also returned when PIO read does not go through ("all-foxes")
+ * because of "slot-freeze".
+ * @XGE_HAL_ERR_RESET_FAILED: Failed to soft-reset the device.
+ * Returned by xge_hal_device_reset(). One circumstance when it could
+ * happen: slot freeze by the system (see @XGE_HAL_ERR_CRITICAL).
+ * @XGE_HAL_ERR_TOO_MANY: This error is returned if there were laready
+ * maximum number of sessions or queues allocated
+ * @XGE_HAL_ERR_PKT_DROP: TBD
+ * @XGE_HAL_BADCFG_TX_URANGE_A: Invalid Tx link utilization range A. See
+ * the structure xge_hal_tti_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_TX_UFC_A: Invalid frame count for Tx link utilization
+ * range A. See the structure xge_hal_tti_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_TX_URANGE_B: Invalid Tx link utilization range B. See
+ * the structure xge_hal_tti_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_TX_UFC_B: Invalid frame count for Tx link utilization
+ * range B. See the strucuture  xge_hal_tti_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_TX_URANGE_C: Invalid Tx link utilization range C. See
+ * the structure  xge_hal_tti_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_TX_UFC_C: Invalid frame count for Tx link utilization
+ * range C. See the structure xge_hal_tti_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_TX_UFC_D: Invalid frame count for Tx link utilization
+ * range D. See the structure  xge_hal_tti_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_TX_TIMER_VAL: Invalid Tx timer value. See the
+ * structure xge_hal_tti_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_TX_TIMER_CI_EN: Invalid Tx timer continuous interrupt
+ * enable. See the structure xge_hal_tti_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_RX_URANGE_A: Invalid Rx link utilization range A. See
+ * the structure xge_hal_rti_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_RX_UFC_A: Invalid frame count for Rx link utilization
+ * range A. See the structure xge_hal_rti_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_RX_URANGE_B: Invalid Rx link utilization range B. See
+ * the structure xge_hal_rti_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_RX_UFC_B: Invalid frame count for Rx link utilization
+ * range B. See the structure xge_hal_rti_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_RX_URANGE_C: Invalid Rx link utilization range C. See
+ * the structure xge_hal_rti_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_RX_UFC_C: Invalid frame count for Rx link utilization
+ * range C. See the structure xge_hal_rti_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_RX_UFC_D: Invalid frame count for Rx link utilization
+ * range D. See the structure xge_hal_rti_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_RX_TIMER_VAL:  Invalid Rx timer value. See the
+ * structure xge_hal_rti_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH: Invalid initial fifo queue
+ * length. See the structure xge_hal_fifo_queue_t for valid values.
+ * @XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH: Invalid fifo queue max length.
+ * See the structure xge_hal_fifo_queue_t for valid values.
+ * @XGE_HAL_BADCFG_FIFO_QUEUE_INTR: Invalid fifo queue interrupt mode.
+ * See the structure xge_hal_fifo_queue_t for valid values.
+ * @XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS: Invalid Initial number of
+ * RxD blocks for the ring. See the structure xge_hal_ring_queue_t for
+ * valid values.
+ * @XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS: Invalid maximum number of RxD
+ * blocks for the ring. See the structure xge_hal_ring_queue_t for
+ * valid values.
+ * @XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE: Invalid ring buffer mode. See
+ * the structure xge_hal_ring_queue_t for valid values.
+ * @XGE_HAL_BADCFG_RING_QUEUE_SIZE: Invalid ring queue size. See the
+ * structure xge_hal_ring_queue_t for valid values.
+ * @XGE_HAL_BADCFG_BACKOFF_INTERVAL_US: Invalid backoff timer interval
+ * for the ring. See the structure xge_hal_ring_queue_t for valid values.
+ * @XGE_HAL_BADCFG_MAX_FRM_LEN: Invalid ring max frame length. See the
+ * structure xge_hal_ring_queue_t for valid values.
+ * @XGE_HAL_BADCFG_RING_PRIORITY: Invalid ring priority. See the
+ * structure xge_hal_ring_queue_t for valid values.
+ * @XGE_HAL_BADCFG_TMAC_UTIL_PERIOD: Invalid tmac util period. See the
+ * structure xge_hal_mac_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_RMAC_UTIL_PERIOD: Invalid rmac util period. See the
+ * structure xge_hal_mac_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_RMAC_BCAST_EN: Invalid rmac brodcast enable. See the
+ * structure xge_hal_mac_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_RMAC_HIGH_PTIME: Invalid rmac pause time. See the
+ * structure xge_hal_mac_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3: Invalid threshold for pause
+ * frame generation for queues 0 through 3. See the structure
+ * xge_hal_mac_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7:Invalid threshold for pause
+ * frame generation for queues 4 through 7. See the structure
+ * xge_hal_mac_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_FIFO_FRAGS: Invalid fifo max fragments length. See
+ * the structure xge_hal_fifo_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD: Invalid fifo reserve
+ * threshold. See the structure xge_hal_fifo_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE: Invalid fifo descriptors memblock
+ * size. See the structure xge_hal_fifo_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE: Invalid ring descriptors memblock
+ * size. See the structure xge_hal_ring_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_MAX_MTU: Invalid max mtu for the device. See the
+ * structure xge_hal_device_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_ISR_POLLING_CNT: Invalid isr polling count. See the
+ * structure xge_hal_device_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_LATENCY_TIMER: Invalid Latency timer. See the
+ * structure xge_hal_device_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_MAX_SPLITS_TRANS: Invalid maximum  number of pci-x
+ * split transactions. See the structure xge_hal_device_config_t{} for valid
+ * values.
+ * @XGE_HAL_BADCFG_MMRB_COUNT: Invalid mmrb count.  See the structure
+ * xge_hal_device_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_SHARED_SPLITS: Invalid number of outstanding split
+ * transactions that is shared by Tx and Rx requests. See the structure
+ * xge_hal_device_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_STATS_REFRESH_TIME: Invalid time interval for
+ * automatic statistics transfer to the host. See the structure
+ * xge_hal_device_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_PCI_FREQ_MHERZ:  Invalid pci clock frequency. See the
+ * structure xge_hal_device_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_PCI_MODE: Invalid pci mode. See the structure
+ * xge_hal_device_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_INTR_MODE: Invalid interrupt mode. See the structure
+ * xge_hal_device_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_SCHED_TIMER_US: Invalid scheduled timer interval to
+ * generate interrupt. See the structure  xge_hal_device_config_t{}
+ * for valid values.
+ * @XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT: Invalid scheduled timer one
+ * shot. See the structure xge_hal_device_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL: Invalid driver queue initial
+ * size. See the structure xge_hal_driver_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_QUEUE_SIZE_MAX: Invalid driver queue max size.  See
+ * the structure xge_hal_driver_config_t{} for valid values.
+ * @XGE_HAL_BADCFG_RING_RTH_EN: Invalid value of RTH-enable. See
+ * the structure xge_hal_ring_queue_t for valid values.
+ * @XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS: Invalid value configured for
+ * indicate_max_pkts variable.
+ * @XGE_HAL_BADCFG_TX_TIMER_AC_EN: Invalid value for Tx timer
+ * auto-cancel. See xge_hal_tti_config_t{}.
+ * @XGE_HAL_BADCFG_RX_TIMER_AC_EN: Invalid value for Rx timer
+ * auto-cancel. See xge_hal_rti_config_t{}.
+ * @XGE_HAL_BADCFG_RXUFCA_INTR_THRES: TODO
+ * @XGE_HAL_BADCFG_RXUFCA_LO_LIM: TODO
+ * @XGE_HAL_BADCFG_RXUFCA_HI_LIM: TODO
+ * @XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD: TODO
+ * @XGE_HAL_BADCFG_TRACEBUF_SIZE: Bad configuration: the size of the circular
+ * (in memory) trace buffer either too large or too small. See the
+ * the corresponding header file or README for the acceptable range.
+ * @XGE_HAL_BADCFG_LINK_VALID_CNT: Bad configuration: the link-valid
+ * counter cannot have the specified value. Note that the link-valid
+ * counting is done only at device-open time, to determine with the
+ * specified certainty that the link is up. See the
+ * the corresponding header file or README for the acceptable range.
+ * See also @XGE_HAL_BADCFG_LINK_RETRY_CNT.
+ * @XGE_HAL_BADCFG_LINK_RETRY_CNT: Bad configuration: the specified
+ * link-up retry count is out of the valid range. Note that the link-up
+ * retry counting is done only at device-open time.
+ * See also xge_hal_device_config_t{}.
+ * @XGE_HAL_BADCFG_LINK_STABILITY_PERIOD: Invalid link stability period.
+ * @XGE_HAL_BADCFG_DEVICE_POLL_MILLIS: Invalid device poll interval.
+ * @XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN: TBD
+ * @XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN: TBD
+ * @XGE_HAL_BADCFG_MEDIA: TBD
+ * @XGE_HAL_BADCFG_NO_ISR_EVENTS: TBD
+ * See the structure xge_hal_device_config_t{} for valid values.
+ * @XGE_HAL_EOF_TRACE_BUF: End of the circular (in memory) trace buffer.
+ * Returned by xge_hal_mgmt_trace_read(), when user tries to read the trace
+ * past the buffer limits. Used to enable user to load the trace in two
+ * or more reads.
+ * @XGE_HAL_BADCFG_RING_RTS_MAC_EN: Invalid value of RTS_MAC_EN enable. See
+ * the structure xge_hal_ring_queue_t for valid values.
+ * @XGE_HAL_BADCFG_LRO_SG_SIZE : Invalid value of LRO scatter gatter size.
+ * See the structure xge_hal_device_config_t for valid values.
+ * @XGE_HAL_BADCFG_LRO_FRM_LEN : Invalid value of LRO frame length.
+ * See the structure xge_hal_device_config_t for valid values.
+ * @XGE_HAL_BADCFG_WQE_NUM_ODS: TBD
+ * @XGE_HAL_BADCFG_BIMODAL_INTR: Invalid value to configure bimodal interrupts
+ * Enumerates status and error codes returned by HAL public
+ * API functions.
+ * @XGE_HAL_BADCFG_BIMODAL_TIMER_LO_US: TBD
+ * @XGE_HAL_BADCFG_BIMODAL_TIMER_HI_US: TBD
+ * @XGE_HAL_BADCFG_BIMODAL_XENA_NOT_ALLOWED: TBD
+ * @XGE_HAL_BADCFG_RTS_QOS_EN: TBD
+ * @XGE_HAL_BADCFG_FIFO_QUEUE_INTR_VECTOR: TBD
+ * @XGE_HAL_BADCFG_RING_QUEUE_INTR_VECTOR: TBD
+ * @XGE_HAL_BADCFG_RTS_PORT_EN: TBD
+ * @XGE_HAL_BADCFG_RING_RTS_PORT_EN: TBD
+ *
+ */
+typedef enum xge_hal_status_e {
+	XGE_HAL_OK				= 0,
+	XGE_HAL_FAIL				= 1,
+	XGE_HAL_COMPLETIONS_REMAIN		= 2,
+
+	XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS = XGE_HAL_BASE_INF + 1,
+	XGE_HAL_INF_OUT_OF_DESCRIPTORS		= XGE_HAL_BASE_INF + 2,
+	XGE_HAL_INF_CHANNEL_IS_NOT_READY	= XGE_HAL_BASE_INF + 3,
+	XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING	= XGE_HAL_BASE_INF + 4,
+	XGE_HAL_INF_STATS_IS_NOT_READY		= XGE_HAL_BASE_INF + 5,
+	XGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS	= XGE_HAL_BASE_INF + 6,
+	XGE_HAL_INF_IRQ_POLLING_CONTINUE	= XGE_HAL_BASE_INF + 7,
+	XGE_HAL_INF_LRO_BEGIN			= XGE_HAL_BASE_INF + 8,
+	XGE_HAL_INF_LRO_CONT			= XGE_HAL_BASE_INF + 9,
+	XGE_HAL_INF_LRO_UNCAPABLE		= XGE_HAL_BASE_INF + 10,
+	XGE_HAL_INF_LRO_END_1			= XGE_HAL_BASE_INF + 11,
+	XGE_HAL_INF_LRO_END_2			= XGE_HAL_BASE_INF + 12,
+	XGE_HAL_INF_LRO_END_3			= XGE_HAL_BASE_INF + 13,
+	XGE_HAL_INF_LRO_SESSIONS_XCDED		= XGE_HAL_BASE_INF + 14,
+	XGE_HAL_INF_NOT_ENOUGH_HW_CQES		= XGE_HAL_BASE_INF + 15,
+	XGE_HAL_ERR_DRIVER_NOT_INITIALIZED	= XGE_HAL_BASE_ERR + 1,
+	XGE_HAL_ERR_OUT_OF_MEMORY		= XGE_HAL_BASE_ERR + 4,
+	XGE_HAL_ERR_CHANNEL_NOT_FOUND		= XGE_HAL_BASE_ERR + 5,
+	XGE_HAL_ERR_WRONG_IRQ			= XGE_HAL_BASE_ERR + 6,
+	XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES	= XGE_HAL_BASE_ERR + 7,
+	XGE_HAL_ERR_SWAPPER_CTRL		= XGE_HAL_BASE_ERR + 8,
+	XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT	= XGE_HAL_BASE_ERR + 9,
+	XGE_HAL_ERR_INVALID_MTU_SIZE		= XGE_HAL_BASE_ERR + 10,
+	XGE_HAL_ERR_OUT_OF_MAPPING		= XGE_HAL_BASE_ERR + 11,
+	XGE_HAL_ERR_BAD_SUBSYSTEM_ID		= XGE_HAL_BASE_ERR + 12,
+	XGE_HAL_ERR_INVALID_BAR_ID		= XGE_HAL_BASE_ERR + 13,
+	XGE_HAL_ERR_INVALID_OFFSET		= XGE_HAL_BASE_ERR + 14,
+	XGE_HAL_ERR_INVALID_DEVICE		= XGE_HAL_BASE_ERR + 15,
+	XGE_HAL_ERR_OUT_OF_SPACE		= XGE_HAL_BASE_ERR + 16,
+	XGE_HAL_ERR_INVALID_VALUE_BIT_SIZE	= XGE_HAL_BASE_ERR + 17,
+	XGE_HAL_ERR_VERSION_CONFLICT		= XGE_HAL_BASE_ERR + 18,
+	XGE_HAL_ERR_INVALID_MAC_ADDRESS		= XGE_HAL_BASE_ERR + 19,
+	XGE_HAL_ERR_BAD_DEVICE_ID		= XGE_HAL_BASE_ERR + 20,
+        XGE_HAL_ERR_OUT_ALIGNED_FRAGS           = XGE_HAL_BASE_ERR + 21,
+	XGE_HAL_ERR_DEVICE_NOT_INITIALIZED	= XGE_HAL_BASE_ERR + 22,
+	XGE_HAL_ERR_SPDM_NOT_ENABLED		= XGE_HAL_BASE_ERR + 23,
+	XGE_HAL_ERR_SPDM_TABLE_FULL		= XGE_HAL_BASE_ERR + 24,
+	XGE_HAL_ERR_SPDM_INVALID_ENTRY		= XGE_HAL_BASE_ERR + 25,
+	XGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND	= XGE_HAL_BASE_ERR + 26,
+	XGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT= XGE_HAL_BASE_ERR + 27,
+	XGE_HAL_ERR_INVALID_PCI_INFO		= XGE_HAL_BASE_ERR + 28,
+	XGE_HAL_ERR_CRITICAL		        = XGE_HAL_BASE_ERR + 29,
+	XGE_HAL_ERR_RESET_FAILED		= XGE_HAL_BASE_ERR + 30,
+	XGE_HAL_ERR_TOO_MANY			= XGE_HAL_BASE_ERR + 32,
+	XGE_HAL_ERR_PKT_DROP		        = XGE_HAL_BASE_ERR + 33,
+
+	XGE_HAL_BADCFG_TX_URANGE_A		= XGE_HAL_BASE_BADCFG + 1,
+	XGE_HAL_BADCFG_TX_UFC_A			= XGE_HAL_BASE_BADCFG + 2,
+	XGE_HAL_BADCFG_TX_URANGE_B		= XGE_HAL_BASE_BADCFG + 3,
+	XGE_HAL_BADCFG_TX_UFC_B			= XGE_HAL_BASE_BADCFG + 4,
+	XGE_HAL_BADCFG_TX_URANGE_C		= XGE_HAL_BASE_BADCFG + 5,
+	XGE_HAL_BADCFG_TX_UFC_C			= XGE_HAL_BASE_BADCFG + 6,
+	XGE_HAL_BADCFG_TX_UFC_D			= XGE_HAL_BASE_BADCFG + 8,
+	XGE_HAL_BADCFG_TX_TIMER_VAL		= XGE_HAL_BASE_BADCFG + 9,
+	XGE_HAL_BADCFG_TX_TIMER_CI_EN		= XGE_HAL_BASE_BADCFG + 10,
+	XGE_HAL_BADCFG_RX_URANGE_A		= XGE_HAL_BASE_BADCFG + 11,
+	XGE_HAL_BADCFG_RX_UFC_A			= XGE_HAL_BASE_BADCFG + 12,
+	XGE_HAL_BADCFG_RX_URANGE_B		= XGE_HAL_BASE_BADCFG + 13,
+	XGE_HAL_BADCFG_RX_UFC_B			= XGE_HAL_BASE_BADCFG + 14,
+	XGE_HAL_BADCFG_RX_URANGE_C		= XGE_HAL_BASE_BADCFG + 15,
+	XGE_HAL_BADCFG_RX_UFC_C			= XGE_HAL_BASE_BADCFG + 16,
+	XGE_HAL_BADCFG_RX_UFC_D			= XGE_HAL_BASE_BADCFG + 17,
+	XGE_HAL_BADCFG_RX_TIMER_VAL		= XGE_HAL_BASE_BADCFG + 18,
+	XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH= XGE_HAL_BASE_BADCFG +	19,
+	XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH    = XGE_HAL_BASE_BADCFG + 20,
+	XGE_HAL_BADCFG_FIFO_QUEUE_INTR		= XGE_HAL_BASE_BADCFG + 21,
+	XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS=XGE_HAL_BASE_BADCFG +	22,
+	XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS	= XGE_HAL_BASE_BADCFG +	23,
+	XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE	= XGE_HAL_BASE_BADCFG +	24,
+	XGE_HAL_BADCFG_RING_QUEUE_SIZE		= XGE_HAL_BASE_BADCFG + 25,
+	XGE_HAL_BADCFG_BACKOFF_INTERVAL_US	= XGE_HAL_BASE_BADCFG + 26,
+	XGE_HAL_BADCFG_MAX_FRM_LEN		= XGE_HAL_BASE_BADCFG + 27,
+	XGE_HAL_BADCFG_RING_PRIORITY		= XGE_HAL_BASE_BADCFG + 28,
+	XGE_HAL_BADCFG_TMAC_UTIL_PERIOD		= XGE_HAL_BASE_BADCFG + 29,
+	XGE_HAL_BADCFG_RMAC_UTIL_PERIOD		= XGE_HAL_BASE_BADCFG + 30,
+	XGE_HAL_BADCFG_RMAC_BCAST_EN		= XGE_HAL_BASE_BADCFG + 31,
+	XGE_HAL_BADCFG_RMAC_HIGH_PTIME		= XGE_HAL_BASE_BADCFG + 32,
+	XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3	= XGE_HAL_BASE_BADCFG +33,
+	XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7	= XGE_HAL_BASE_BADCFG +	34,
+	XGE_HAL_BADCFG_FIFO_FRAGS		= XGE_HAL_BASE_BADCFG + 35,
+	XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD	= XGE_HAL_BASE_BADCFG +	37,
+	XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE	= XGE_HAL_BASE_BADCFG + 38,
+	XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE	= XGE_HAL_BASE_BADCFG +	39,
+	XGE_HAL_BADCFG_MAX_MTU			= XGE_HAL_BASE_BADCFG + 40,
+	XGE_HAL_BADCFG_ISR_POLLING_CNT		= XGE_HAL_BASE_BADCFG + 41,
+	XGE_HAL_BADCFG_LATENCY_TIMER		= XGE_HAL_BASE_BADCFG + 42,
+	XGE_HAL_BADCFG_MAX_SPLITS_TRANS		= XGE_HAL_BASE_BADCFG + 43,
+	XGE_HAL_BADCFG_MMRB_COUNT		= XGE_HAL_BASE_BADCFG + 44,
+	XGE_HAL_BADCFG_SHARED_SPLITS		= XGE_HAL_BASE_BADCFG + 45,
+	XGE_HAL_BADCFG_STATS_REFRESH_TIME	= XGE_HAL_BASE_BADCFG +	46,
+	XGE_HAL_BADCFG_PCI_FREQ_MHERZ		= XGE_HAL_BASE_BADCFG + 47,
+	XGE_HAL_BADCFG_PCI_MODE			= XGE_HAL_BASE_BADCFG + 48,
+	XGE_HAL_BADCFG_INTR_MODE		= XGE_HAL_BASE_BADCFG + 49,
+	XGE_HAL_BADCFG_SCHED_TIMER_US		= XGE_HAL_BASE_BADCFG + 50,
+	XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT	= XGE_HAL_BASE_BADCFG + 51,
+	XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL	= XGE_HAL_BASE_BADCFG + 52,
+	XGE_HAL_BADCFG_QUEUE_SIZE_MAX		= XGE_HAL_BASE_BADCFG + 53,
+	XGE_HAL_BADCFG_RING_RTH_EN		= XGE_HAL_BASE_BADCFG + 54,
+	XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS	= XGE_HAL_BASE_BADCFG + 55,
+	XGE_HAL_BADCFG_TX_TIMER_AC_EN		= XGE_HAL_BASE_BADCFG +	56,
+	XGE_HAL_BADCFG_RX_TIMER_AC_EN		= XGE_HAL_BASE_BADCFG +	57,
+	XGE_HAL_BADCFG_RXUFCA_INTR_THRES	= XGE_HAL_BASE_BADCFG + 58,
+	XGE_HAL_BADCFG_RXUFCA_LO_LIM		= XGE_HAL_BASE_BADCFG + 59,
+	XGE_HAL_BADCFG_RXUFCA_HI_LIM		= XGE_HAL_BASE_BADCFG + 60,
+	XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD	= XGE_HAL_BASE_BADCFG + 61,
+	XGE_HAL_BADCFG_TRACEBUF_SIZE		= XGE_HAL_BASE_BADCFG + 62,
+	XGE_HAL_BADCFG_LINK_VALID_CNT		= XGE_HAL_BASE_BADCFG + 63,
+	XGE_HAL_BADCFG_LINK_RETRY_CNT		= XGE_HAL_BASE_BADCFG + 64,
+	XGE_HAL_BADCFG_LINK_STABILITY_PERIOD	= XGE_HAL_BASE_BADCFG + 65,
+	XGE_HAL_BADCFG_DEVICE_POLL_MILLIS       = XGE_HAL_BASE_BADCFG + 66,
+	XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN	= XGE_HAL_BASE_BADCFG + 67,
+	XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN	= XGE_HAL_BASE_BADCFG + 68,
+	XGE_HAL_BADCFG_MEDIA			= XGE_HAL_BASE_BADCFG + 69,
+	XGE_HAL_BADCFG_NO_ISR_EVENTS		= XGE_HAL_BASE_BADCFG + 70,
+	XGE_HAL_BADCFG_RING_RTS_MAC_EN		= XGE_HAL_BASE_BADCFG + 71,
+	XGE_HAL_BADCFG_LRO_SG_SIZE		= XGE_HAL_BASE_BADCFG + 72,
+	XGE_HAL_BADCFG_LRO_FRM_LEN		= XGE_HAL_BASE_BADCFG + 73,
+	XGE_HAL_BADCFG_WQE_NUM_ODS		= XGE_HAL_BASE_BADCFG + 74,
+	XGE_HAL_BADCFG_BIMODAL_INTR		= XGE_HAL_BASE_BADCFG + 75,
+	XGE_HAL_BADCFG_BIMODAL_TIMER_LO_US	= XGE_HAL_BASE_BADCFG + 76,
+	XGE_HAL_BADCFG_BIMODAL_TIMER_HI_US	= XGE_HAL_BASE_BADCFG + 77,
+	XGE_HAL_BADCFG_BIMODAL_XENA_NOT_ALLOWED	= XGE_HAL_BASE_BADCFG + 78,
+	XGE_HAL_BADCFG_RTS_QOS_EN		= XGE_HAL_BASE_BADCFG + 79,
+	XGE_HAL_BADCFG_FIFO_QUEUE_INTR_VECTOR	= XGE_HAL_BASE_BADCFG + 80,
+	XGE_HAL_BADCFG_RING_QUEUE_INTR_VECTOR	= XGE_HAL_BASE_BADCFG + 81,
+	XGE_HAL_BADCFG_RTS_PORT_EN		= XGE_HAL_BASE_BADCFG + 82,
+	XGE_HAL_BADCFG_RING_RTS_PORT_EN		= XGE_HAL_BASE_BADCFG + 83,
+	XGE_HAL_BADCFG_TRACEBUF_TIMESTAMP	= XGE_HAL_BASE_BADCFG + 84,
+	XGE_HAL_EOF_TRACE_BUF			= -1
+} xge_hal_status_e;
+
+#define XGE_HAL_ETH_ALEN				6
+typedef u8 macaddr_t[XGE_HAL_ETH_ALEN];
+
+#define XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE		0x100
+
+/* frames sizes */
+#define XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE		14
+#define XGE_HAL_HEADER_802_2_SIZE			3
+#define XGE_HAL_HEADER_SNAP_SIZE			5
+#define XGE_HAL_HEADER_VLAN_SIZE			4
+#define XGE_HAL_MAC_HEADER_MAX_SIZE \
+			(XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE + \
+			 XGE_HAL_HEADER_802_2_SIZE + \
+			 XGE_HAL_HEADER_SNAP_SIZE)
+
+#define XGE_HAL_TCPIP_HEADER_MAX_SIZE			(64 + 64)
+
+/* 32bit alignments */
+#define XGE_HAL_HEADER_ETHERNET_II_802_3_ALIGN		2
+#define XGE_HAL_HEADER_802_2_SNAP_ALIGN			2
+#define XGE_HAL_HEADER_802_2_ALIGN			3
+#define XGE_HAL_HEADER_SNAP_ALIGN			1
+
+#define XGE_HAL_L3_CKSUM_OK				0xFFFF
+#define XGE_HAL_L4_CKSUM_OK				0xFFFF
+#define XGE_HAL_MIN_MTU					46
+#define XGE_HAL_MAX_MTU					9600
+#define XGE_HAL_DEFAULT_MTU				1500
+
+#define XGE_HAL_SEGEMENT_OFFLOAD_MAX_SIZE	81920
+
+#define XGE_HAL_PCISIZE_XENA			26 /* multiples of dword */
+#define XGE_HAL_PCISIZE_HERC			64 /* multiples of dword */
+
+#define XGE_HAL_MAX_MSIX_MESSAGES	64
+#define XGE_HAL_MAX_MSIX_MESSAGES_WITH_ADDR XGE_HAL_MAX_MSIX_MESSAGES * 2
+/*  Highest level interrupt blocks */
+#define XGE_HAL_TX_PIC_INTR     (0x0001<<0)
+#define XGE_HAL_TX_DMA_INTR     (0x0001<<1)
+#define XGE_HAL_TX_MAC_INTR     (0x0001<<2)
+#define XGE_HAL_TX_XGXS_INTR    (0x0001<<3)
+#define XGE_HAL_TX_TRAFFIC_INTR (0x0001<<4)
+#define XGE_HAL_RX_PIC_INTR     (0x0001<<5)
+#define XGE_HAL_RX_DMA_INTR     (0x0001<<6)
+#define XGE_HAL_RX_MAC_INTR     (0x0001<<7)
+#define XGE_HAL_RX_XGXS_INTR    (0x0001<<8)
+#define XGE_HAL_RX_TRAFFIC_INTR (0x0001<<9)
+#define XGE_HAL_MC_INTR         (0x0001<<10)
+#define XGE_HAL_SCHED_INTR      (0x0001<<11)
+#define XGE_HAL_ALL_INTRS       (XGE_HAL_TX_PIC_INTR   | \
+                               XGE_HAL_TX_DMA_INTR     | \
+                               XGE_HAL_TX_MAC_INTR     | \
+                               XGE_HAL_TX_XGXS_INTR    | \
+                               XGE_HAL_TX_TRAFFIC_INTR | \
+                               XGE_HAL_RX_PIC_INTR     | \
+                               XGE_HAL_RX_DMA_INTR     | \
+                               XGE_HAL_RX_MAC_INTR     | \
+                               XGE_HAL_RX_XGXS_INTR    | \
+                               XGE_HAL_RX_TRAFFIC_INTR | \
+                               XGE_HAL_MC_INTR	       | \
+			       XGE_HAL_SCHED_INTR)
+#define XGE_HAL_GEN_MASK_INTR    (0x0001<<12)
+
+/* Interrupt masks for the general interrupt mask register */
+#define XGE_HAL_ALL_INTRS_DIS   0xFFFFFFFFFFFFFFFFULL
+
+#define XGE_HAL_TXPIC_INT_M     BIT(0)
+#define XGE_HAL_TXDMA_INT_M     BIT(1)
+#define XGE_HAL_TXMAC_INT_M     BIT(2)
+#define XGE_HAL_TXXGXS_INT_M    BIT(3)
+#define XGE_HAL_TXTRAFFIC_INT_M BIT(8)
+#define XGE_HAL_PIC_RX_INT_M    BIT(32)
+#define XGE_HAL_RXDMA_INT_M     BIT(33)
+#define XGE_HAL_RXMAC_INT_M     BIT(34)
+#define XGE_HAL_MC_INT_M        BIT(35)
+#define XGE_HAL_RXXGXS_INT_M    BIT(36)
+#define XGE_HAL_RXTRAFFIC_INT_M BIT(40)
+
+/* MSI level Interrupts */
+#define XGE_HAL_MAX_MSIX_VECTORS	(16)
+
+typedef struct xge_hal_ipv4 {
+	u32 addr;
+}xge_hal_ipv4;
+
+typedef struct xge_hal_ipv6 {
+	u64 addr[2];
+}xge_hal_ipv6;
+
+typedef union xge_hal_ipaddr_t {
+	xge_hal_ipv4 ipv4;
+	xge_hal_ipv6 ipv6;
+}xge_hal_ipaddr_t;
+
+/* DMA level Interrupts */
+#define XGE_HAL_TXDMA_PFC_INT_M	BIT(0)
+
+/*  PFC block interrupts */
+#define XGE_HAL_PFC_MISC_ERR_1	BIT(0)   /* Interrupt to indicate FIFO
+full */
+
+/* basic handles */
+typedef void* xge_hal_device_h;
+typedef void* xge_hal_dtr_h;
+typedef void* xge_hal_channel_h;
+#ifdef XGEHAL_RNIC
+typedef void* xge_hal_towi_h;
+typedef void* xge_hal_hw_wqe_h;
+typedef void* xge_hal_hw_cqe_h;
+typedef void* xge_hal_lro_wqe_h;
+typedef void* xge_hal_lro_cqe_h;
+typedef void* xge_hal_up_msg_h;
+typedef void* xge_hal_down_msg_h;
+typedef void* xge_hal_channel_callback_fh;
+typedef void* xge_hal_msg_queueh;
+typedef void* xge_hal_pblist_h;
+#endif
+/*
+ * I2C device id. Used in I2C control register for accessing EEPROM device
+ * memory.
+ */
+#define XGE_DEV_ID		5
+
+typedef enum xge_hal_xpak_alarm_type_e {
+	XGE_HAL_XPAK_ALARM_EXCESS_TEMP = 1,
+	XGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT = 2,
+	XGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT = 3,
+} xge_hal_xpak_alarm_type_e;
+
+
+__EXTERN_END_DECLS
+
+#endif /* XGE_HAL_TYPES_H */
diff --git a/sys/dev/nxge/include/xgehal.h b/sys/dev/nxge/include/xgehal.h
new file mode 100644
index 0000000..4c3c08a
--- /dev/null
+++ b/sys/dev/nxge/include/xgehal.h
@@ -0,0 +1,53 @@
+/*-
+ * Copyright (c) 2002-2007 Neterion, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ *  FileName :    xgehal.h
+ *
+ *  Description:  Consolidated header. Upper layers should include it to
+ *                avoid include order problems.
+ *
+ *  Created:      14 May 2004
+ */
+
+#ifndef XGE_HAL_H
+#define XGE_HAL_H
+
+#include <dev/nxge/include/xge-defs.h>
+#include <dev/nxge/include/xge-os-pal.h>
+#include <dev/nxge/include/xge-debug.h>
+#include <dev/nxge/include/xgehal-types.h>
+#include <dev/nxge/include/xgehal-driver.h>
+#include <dev/nxge/include/xgehal-config.h>
+#include <dev/nxge/include/xgehal-device.h>
+#include <dev/nxge/include/xgehal-channel.h>
+#include <dev/nxge/include/xgehal-fifo.h>
+#include <dev/nxge/include/xgehal-ring.h>
+#include <dev/nxge/include/xgehal-mgmt.h>
+
+#endif /* XGE_HAL_H */