diff options
| author | yongari <yongari@FreeBSD.org> | 2010-04-30 18:58:55 +0000 |
|---|---|---|
| committer | yongari <yongari@FreeBSD.org> | 2010-04-30 18:58:55 +0000 |
| commit | 7a0b6f8a32672cdf476aaff405247a7f4a38d97e (patch) | |
| tree | 23c6257c679ff60ea3d99cacf673d808a6926c83 /sys/dev/msk | |
| parent | 90bf77c71267bf38221fa717f6fac628910d2a8e (diff) | |
| download | FreeBSD-src-7a0b6f8a32672cdf476aaff405247a7f4a38d97e.zip FreeBSD-src-7a0b6f8a32672cdf476aaff405247a7f4a38d97e.tar.gz | |
Add basic support for Marvell 88E8059 Yukon Optima.
Tested by: James LaLagna < jameslalagna <> gmail dot com >
MFC after: 5 days
Diffstat (limited to 'sys/dev/msk')
| -rw-r--r-- | sys/dev/msk/if_msk.c | 20 | ||||
| -rw-r--r-- | sys/dev/msk/if_mskreg.h | 6 |
2 files changed, 23 insertions, 3 deletions
diff --git a/sys/dev/msk/if_msk.c b/sys/dev/msk/if_msk.c index fbae30b..e15ccfe 100644 --- a/sys/dev/msk/if_msk.c +++ b/sys/dev/msk/if_msk.c @@ -223,6 +223,8 @@ static struct msk_product { "Marvell Yukon 88E8072 Gigabit Ethernet" }, { VENDORID_MARVELL, DEVICEID_MRVL_4380, "Marvell Yukon 88E8057 Gigabit Ethernet" }, + { VENDORID_MARVELL, DEVICEID_MRVL_4381, + "Marvell Yukon 88E8059 Gigabit Ethernet" }, { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, "D-Link 550SX Gigabit Ethernet" }, { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX, @@ -239,7 +241,9 @@ static const char *model_name[] = { "Yukon FE", "Yukon FE+", "Yukon Supreme", - "Yukon Ultra 2" + "Yukon Ultra 2", + "Yukon Unknown", + "Yukon Optima", }; static int mskc_probe(device_t); @@ -1229,6 +1233,7 @@ msk_phy_power(struct msk_softc *sc, int mode) case CHIP_ID_YUKON_EX: case CHIP_ID_YUKON_FE_P: case CHIP_ID_YUKON_UL_2: + case CHIP_ID_YUKON_OPT: CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF); /* Enable all clocks. */ @@ -1372,6 +1377,10 @@ mskc_reset(struct msk_softc *sc) GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | GMC_BYP_RETR_ON); } + if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) { + /* Disable PCIe PHY powerdown(reg 0x80, bit7). */ + CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080); + } CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); /* LED On. */ @@ -1705,8 +1714,9 @@ mskc_attach(device_t dev) sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; /* Bail out if chip is not recognized. */ if (sc->msk_hw_id < CHIP_ID_YUKON_XL || - sc->msk_hw_id > CHIP_ID_YUKON_UL_2 || - sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { + sc->msk_hw_id > CHIP_ID_YUKON_OPT || + sc->msk_hw_id == CHIP_ID_YUKON_SUPR || + sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) { device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", sc->msk_hw_id, sc->msk_hw_rev); mtx_destroy(&sc->msk_mtx); @@ -1819,6 +1829,10 @@ mskc_attach(device_t dev) sc->msk_clock = 125; /* 125 MHz */ sc->msk_pflags |= MSK_FLAG_JUMBO; break; + case CHIP_ID_YUKON_OPT: + sc->msk_clock = 125; /* 125 MHz */ + sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2; + break; default: sc->msk_clock = 156; /* 156 MHz */ break; diff --git a/sys/dev/msk/if_mskreg.h b/sys/dev/msk/if_mskreg.h index 3e8ae47..3b05b9b 100644 --- a/sys/dev/msk/if_mskreg.h +++ b/sys/dev/msk/if_mskreg.h @@ -145,6 +145,7 @@ #define DEVICEID_MRVL_436B 0x436B #define DEVICEID_MRVL_436C 0x436C #define DEVICEID_MRVL_4380 0x4380 +#define DEVICEID_MRVL_4381 0x4381 /* * D-Link gigabit ethernet device ID @@ -828,6 +829,9 @@ #define Y2_IS_CHK_RX2 BIT_10 /* Descriptor error Rx 2 */ #define Y2_IS_CHK_TXS2 BIT_9 /* Descriptor error TXS 2 */ #define Y2_IS_CHK_TXA2 BIT_8 /* Descriptor error TXA 2 */ +#define Y2_IS_PSM_ACK BIT_7 /* PSM Ack (Yukon Optima) */ +#define Y2_IS_PTP_TIST BIT_6 /* PTP TIme Stamp (Yukon Optima) */ +#define Y2_IS_PHY_QLNK BIT_5 /* PHY Quick Link (Yukon Optima) */ #define Y2_IS_IRQ_PHY1 BIT_4 /* Interrupt from PHY 1 */ #define Y2_IS_IRQ_MAC1 BIT_3 /* Interrupt from MAC 1 */ #define Y2_IS_CHK_RX1 BIT_2 /* Descriptor error Rx 1 */ @@ -894,6 +898,8 @@ #define CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */ #define CHIP_ID_YUKON_SUPR 0xb9 /* Chip ID for YUKON-2 Supreme */ #define CHIP_ID_YUKON_UL_2 0xba /* Chip ID for YUKON-2 Ultra 2 */ +#define CHIP_ID_YUKON_UNKNOWN 0xbb +#define CHIP_ID_YUKON_OPT 0xbc /* Chip ID for YUKON-2 Optima */ #define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */ #define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */ |
