Make phy respond only at address 0. This makes phy driver attached

only at address 0 which is supposed to be the only valid phy address
on Marvell PHY. The more correct solution would be masking PHY
address ranges allowable in PHY probe routine. Unfortunately,
FreeBSD has no way to retrict the PHY address ranges or to pass special
flags to PHY driver.
This change assumes that PHY hardwares attached to msk(4) would be
Marvell made 88E11xx PHY.

With this changes the phantom phys attached on 88E8036(Yukon FE)
should disappear.

Reported by:	Oleg Lomaka  < oleg AT lomaka DOT org DOT ua >
Tested by:	Oleg Lomaka  < oleg AT lomaka DOT org DOT ua >

2 files changed, 16 insertions, 22 deletions

diff --git a/sys/dev/msk/if_msk.c b/sys/dev/msk/if_msk.c
index a83edec..41fb2b7 100644
--- a/sys/dev/msk/if_msk.c
+++ b/sys/dev/msk/if_msk.c
@@ -367,6 +367,9 @@ msk_miibus_readreg(device_t dev, int phy, int reg)
 {
 	struct msk_if_softc *sc_if;
 
+	if (phy != PHY_ADDR_MARV)
+		return (0);
+
 	sc_if = device_get_softc(dev);
 
 	return (msk_phy_readreg(sc_if, phy, reg));
@@ -405,6 +408,9 @@ msk_miibus_writereg(device_t dev, int phy, int reg, int val)
 {
 	struct msk_if_softc *sc_if;
 
+	if (phy != PHY_ADDR_MARV)
+		return (0);
+
 	sc_if = device_get_softc(dev);
 
 	return (msk_phy_writereg(sc_if, phy, reg, val));
@@ -516,17 +522,14 @@ msk_link_task(void *arg, int pending)
 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac);
 
 		/* Enable PHY interrupt for FIFO underrun/overflow. */
-		if (sc->msk_marvell_phy)
-			msk_phy_writereg(sc_if, PHY_ADDR_MARV,
-			    PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR);
+		msk_phy_writereg(sc_if, PHY_ADDR_MARV,
+		    PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR);
 	} else {
 		/*
 		 * Link state changed to down.
 		 * Disable PHY interrupts.
 		 */
-		if (sc->msk_marvell_phy)
-			msk_phy_writereg(sc_if, PHY_ADDR_MARV,
-			    PHY_MARV_INT_MASK, 0);
+		msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
 		/* Disable Rx/Tx MAC. */
 		gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
 		gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
@@ -1503,10 +1506,6 @@ msk_attach(device_t dev)
 		error = ENXIO;
 		goto fail;
 	}
-	/* Check whether PHY Id is MARVELL. */
-	if (msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_ID0)
-	    == PHY_MARV_ID0_VAL)
-		sc->msk_marvell_phy = 1;
 
 fail:
 	if (error != 0) {
@@ -3158,15 +3157,12 @@ msk_intr_phy(struct msk_if_softc *sc_if)
 {
 	uint16_t status;
 
-	if (sc_if->msk_softc->msk_marvell_phy) {
-		msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT);
-		status = msk_phy_readreg(sc_if, PHY_ADDR_MARV,
-		    PHY_MARV_INT_STAT);
-		/* Handle FIFO Underrun/Overflow? */
-		if ((status & PHY_M_IS_FIFO_ERROR))
-			device_printf(sc_if->msk_if_dev,
-			    "PHY FIFO underrun/overflow.\n");
-	}
+	msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT);
+	status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT);
+	/* Handle FIFO Underrun/Overflow? */
+	if ((status & PHY_M_IS_FIFO_ERROR))
+		device_printf(sc_if->msk_if_dev,
+		    "PHY FIFO underrun/overflow.\n");
 }
 
 static void
@@ -3974,8 +3970,7 @@ msk_stop(struct msk_if_softc *sc_if)
 	/* Disable all GMAC interrupt. */
 	CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0);
 	/* Disable PHY interrupt. */
-	if (sc->msk_marvell_phy)
-		msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
+	msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
 
 	/* Disable the RAM Interface Arbiter. */
 	CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB);
diff --git a/sys/dev/msk/if_mskreg.h b/sys/dev/msk/if_mskreg.h
index b0edd39..0813ffc 100644
--- a/sys/dev/msk/if_mskreg.h
+++ b/sys/dev/msk/if_mskreg.h
@@ -2306,7 +2306,6 @@ struct msk_softc {
 	uint32_t		msk_intrhwemask;
 	int			msk_suspended;
 	int			msk_clock;
-	int			msk_marvell_phy;
 	int			msk_msi;
 	struct msk_if_softc	*msk_if[2];
 	device_t		msk_devs[2];