Various fixes for EC Ultra.

 o Enable jumbo frame support for EC Ultra and disable jumbo frame
   for FE.
 o Enable store and forward mode for standard MTU sized frame.
 o Enable TSO for EC Ultra. However TSO/checksum offload is disabled
   for jumbo frame case. Because EC Ultra can't use store and forward
   mode for jumbo frame TSO/checksum offload is not available.
 o Adjust Tx GMAC almost empty threshold value and add a jumbo frame
   water mark. The maic value was obtained from Marvell's sk98lin
   driver.
 o Fix EC Ultra chip revision number.

2 files changed, 37 insertions, 19 deletions

diff --git a/sys/dev/msk/if_msk.c b/sys/dev/msk/if_msk.c
index 1ebe895..5020357 100644
--- a/sys/dev/msk/if_msk.c
+++ b/sys/dev/msk/if_msk.c
@@ -916,7 +916,7 @@ msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 			error = EINVAL;
 			break;
 		}
-		if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U &&
+		if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE &&
 		    ifr->ifr_mtu > MSK_MAX_FRAMELEN) {
 			error = EINVAL;
 			break;
@@ -983,6 +983,16 @@ msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 			else
 				ifp->if_hwassist &= ~CSUM_TSO;
 		}
+		if (sc_if->msk_framesize > MSK_MAX_FRAMELEN &&
+		    sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
+			/*
+			 * In Yukon EC Ultra, TSO & checksum offload is not
+			 * supported for jumbo frame.
+			 */
+			ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO);
+			ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM);
+		}
+
 		VLAN_CAPABILITIES(ifp);
 		MSK_IF_UNLOCK(sc_if);
 		break;
@@ -1453,13 +1463,8 @@ msk_attach(device_t dev)
 	 * compute the checksum? I think there is no reason to spend time to
 	 * make Rx checksum offload work on Yukon II hardware.
 	 */
-	ifp->if_capabilities = IFCAP_TXCSUM;
-	ifp->if_hwassist = MSK_CSUM_FEATURES;
-	if (sc->msk_hw_id != CHIP_ID_YUKON_EC_U) {
-		/* It seems Yukon EC Ultra doesn't support TSO. */
-		ifp->if_capabilities |= IFCAP_TSO4;
-		ifp->if_hwassist |= CSUM_TSO;
-	}
+	ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4;
+	ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO;
 	ifp->if_capenable = ifp->if_capabilities;
 	ifp->if_ioctl = msk_ioctl;
 	ifp->if_start = msk_start;
@@ -1505,6 +1510,9 @@ msk_attach(device_t dev)
 	 */
         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
 
+	sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN +
+	    ETHER_VLAN_ENCAP_LEN;
+
 	/*
 	 * Do miibus setup.
 	 */
@@ -3706,6 +3714,15 @@ msk_init_locked(struct msk_if_softc *sc_if)
 
 	sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN +
 	    ETHER_VLAN_ENCAP_LEN;
+	if (sc_if->msk_framesize > MSK_MAX_FRAMELEN &&
+	    sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
+		/*
+		 * In Yukon EC Ultra, TSO & checksum offload is not
+		 * supported for jumbo frame.
+		 */
+		ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO);
+		ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM);
+	}
 
 	/*
 	 * Initialize GMAC first.
@@ -3796,9 +3813,6 @@ msk_init_locked(struct msk_if_softc *sc_if)
 	/* Configure hardware VLAN tag insertion/stripping. */
 	msk_setvlan(sc_if, ifp);
 
-	/* XXX It seems STFW is requried for all cases. */
-	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), TX_STFW_ENA);
-
 	if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
 		/* Set Rx Pause threshould. */
 		CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),
@@ -3807,16 +3821,17 @@ msk_init_locked(struct msk_if_softc *sc_if)
 		    MSK_ECU_ULPP);
 		if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) {
 			/*
-			 * Can't sure the following code is needed as Yukon
-			 * Yukon EC Ultra may not support jumbo frames.
-			 *
 			 * Set Tx GMAC FIFO Almost Empty Threshold.
 			 */
 			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
-			    MSK_ECU_AE_THR);
+			    MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
 			/* Disable Store & Forward mode for Tx. */
 			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
-			    TX_STFW_DIS);
+			    TX_JUMBO_ENA | TX_STFW_DIS);
+		} else {
+			/* Enable Store & Forward mode for Tx. */
+			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
+			    TX_JUMBO_DIS | TX_STFW_ENA);
 		}
 	}
 
diff --git a/sys/dev/msk/if_mskreg.h b/sys/dev/msk/if_mskreg.h
index 8d90401..cc324e9 100644
--- a/sys/dev/msk/if_mskreg.h
+++ b/sys/dev/msk/if_mskreg.h
@@ -836,8 +836,8 @@
 #define CHIP_REV_YU_EC_A2	1 /* Chip Rev. for Yukon-EC A2 */
 #define CHIP_REV_YU_EC_A3	2 /* Chip Rev. for Yukon-EC A3 */
 
-#define	CHIP_REV_YU_EC_U_A0	0
-#define	CHIP_REV_YU_EC_U_A1	1
+#define	CHIP_REV_YU_EC_U_A0	1
+#define	CHIP_REV_YU_EC_U_A1	2
 
 /*	B2_Y2_CLK_GATE	 8 bit	Clock Gating (Yukon-2 only) */
 #define Y2_STATUS_LNK2_INAC	BIT_7	/* Status Link 2 inactiv (0 = activ) */
@@ -1082,8 +1082,9 @@
 /* Threshold values for Yukon-EC Ultra */
 #define	MSK_ECU_ULPP	0x0080	/* Upper Pause Threshold (multiples of 8) */
 #define	MSK_ECU_LLPP	0x0060	/* Lower Pause Threshold (multiples of 8) */
-#define	MSK_ECU_AE_THR	0x0180  /* Almost Empty Threshold */
+#define	MSK_ECU_AE_THR	0x0070  /* Almost Empty Threshold */
 #define	MSK_ECU_TXFF_LEV	0x01a0	/* Tx BMU FIFO Level */
+#define	MSK_ECU_JUMBO_WM	0x01
 
 #define MSK_BMU_RX_WM		0x600	/* BMU Rx Watermark */
 #define MSK_BMU_TX_WM		0x600	/* BMU Tx Watermark */
@@ -1863,6 +1864,8 @@
 #define	TX_STFW_ENA	BIT_30	/* Enable Store & Forward (Yukon-EC Ultra) */
 #define TX_VLAN_TAG_ON	BIT_25	/* enable  VLAN tagging */
 #define TX_VLAN_TAG_OFF	BIT_24	/* disable VLAN tagging */
+#define	TX_JUMBO_ENA	BIT_23	/* Enable Jumbo Mode (Yukon-EC Ultra) */
+#define	TX_JUMBO_DIS	BIT_22	/* Disable Jumbo Mode (Yukon-EC Ultra) */
 #define GMF_WSP_TST_ON	BIT_18	/* Write Shadow Pointer Test On */
 #define GMF_WSP_TST_OFF	BIT_17	/* Write Shadow Pointer Test Off */
 #define GMF_WSP_STEP	BIT_16	/* Write Shadow Pointer Step/Increment */