Add support Vitesse VSC8601 PHY that is found on nVidia network

adapters.

Submitted by:	Shigeaki Tagashira < shigeaki AT se DOT hiroshima-u DOT ac DOT jp >
Tested by:	Yuri Pankov < yuri.pankov AT gmail DOT com>,
		Rainer Hurling <rhurlin AT gwdg DOT de >

2 files changed, 30 insertions, 0 deletions

diff --git a/sys/dev/mii/ciphy.c b/sys/dev/mii/ciphy.c
index 07eb5e0..4ad1a6c 100644
--- a/sys/dev/mii/ciphy.c
+++ b/sys/dev/mii/ciphy.c
@@ -91,6 +91,7 @@ static const struct mii_phydesc ciphys[] = {
 	MII_PHY_DESC(CICADA, CS8201),
 	MII_PHY_DESC(CICADA, CS8201A),
 	MII_PHY_DESC(CICADA, CS8201B),
+	MII_PHY_DESC(VITESSE, VSC8601),
 	MII_PHY_END
 };
 
@@ -354,11 +355,28 @@ ciphy_fixup(struct mii_softc *sc)
 {
 	uint16_t		model;
 	uint16_t		status, speed;
+	uint16_t		val;
 
 	model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2));
 	status = PHY_READ(sc, CIPHY_MII_AUXCSR);
 	speed = status & CIPHY_AUXCSR_SPEED;
 
+	if (strcmp(device_get_name(device_get_parent(sc->mii_dev)),
+	    "nfe") == 0) {
+		/* need to set for 2.5V RGMII for NVIDIA adapters */
+		val = PHY_READ(sc, CIPHY_MII_ECTL1);
+		val &= ~(CIPHY_ECTL1_IOVOL | CIPHY_ECTL1_INTSEL);
+		val |= (CIPHY_IOVOL_2500MV | CIPHY_INTSEL_RGMII);
+		PHY_WRITE(sc, CIPHY_MII_ECTL1, val);
+		/* From Linux. */
+		val = PHY_READ(sc, CIPHY_MII_AUXCSR);
+		val |= CIPHY_AUXCSR_MDPPS;
+		PHY_WRITE(sc, CIPHY_MII_AUXCSR, val);
+		val = PHY_READ(sc, CIPHY_MII_10BTCSR);
+		val |= CIPHY_10BTCSR_ECHO;
+		PHY_WRITE(sc, CIPHY_MII_10BTCSR, val);
+	}
+
 	switch (model) {
 	case MII_MODEL_CICADA_CS8201:
 
@@ -396,6 +414,8 @@ ciphy_fixup(struct mii_softc *sc)
 		}
 
 		break;
+	case MII_MODEL_VITESSE_VSC8601:
+		break;
 	default:
 		device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n",
 		    model);
diff --git a/sys/dev/mii/ciphyreg.h b/sys/dev/mii/ciphyreg.h
index 8c0a8a4..3c5c5de 100644
--- a/sys/dev/mii/ciphyreg.h
+++ b/sys/dev/mii/ciphyreg.h
@@ -251,6 +251,16 @@
 /* Extended PHY control register #1 */
 #define CIPHY_MII_ECTL1		0x17
 #define CIPHY_ECTL1_ACTIPHY	0x0020	/* Enable ActiPHY power saving */
+#define CIPHY_ECTL1_IOVOL	0x0e00	/* MAC interface and I/O voltage select */
+#define CIPHY_ECTL1_INTSEL	0xf000	/* select MAC interface */
+
+#define CIPHY_IOVOL_3300MV	0x0000	/* 3.3V for I/O pins */
+#define CIPHY_IOVOL_2500MV	0x0200	/* 2.5V for I/O pins */
+
+#define CIPHY_INTSEL_GMII	0x0000	/* GMII/MII */
+#define CIPHY_INTSEL_RGMII	0x1000
+#define CIPHY_INTSEL_TBI	0x2000
+#define CIPHY_INTSEL_RTBI	0x3000
 
 /* Extended PHY control register #2 */
 #define CIPHY_MII_ECTL2		0x18