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| author | yongari <yongari@FreeBSD.org> | 2008-12-04 01:58:40 +0000 |
|---|---|---|
| committer | yongari <yongari@FreeBSD.org> | 2008-12-04 01:58:40 +0000 |
| commit | 20e7552f469bcf3d64dae25b11f9c4a9ff38f69e (patch) | |
| tree | 2b0e372fc6988f8ed1e2c5f150a610c208a816f2 /sys/dev/jme/if_jmereg.h | |
| parent | 97597606a6bffc7738c740cf9651ca5540888eab (diff) | |
| download | FreeBSD-src-20e7552f469bcf3d64dae25b11f9c4a9ff38f69e.zip FreeBSD-src-20e7552f469bcf3d64dae25b11f9c4a9ff38f69e.tar.gz | |
Add support for newer JMC250/JMC260 revisions.
o Chip full mask revision 2 or later controllers have to
set correct Tx MAC and Tx offload clock depending on negotiated
link speed.
o JMC260 chip full mask revision 2 has a silicon bug that can't
handle 64bit DMA addressing. Add workaround to the bug by
limiting DMA address space to be within 32bit.
o Valid FIFO space of receive control and status register was
changed on chip full mask revision 2 or later controllers. For
these controllers, use default 16QW as it's supposed to be the
safest value for maximum PCIe compatibility. JMicron confirmed
performance will not be reduced even if the FIFO space is set
to 16QW.
o When interface is put into suspend/shutdown state, remove Tx MAC
and Tx offload clock to save more power. We don't need Tx clock
at all in this state.
o Added new register definition for chip full mask revision 2 or
later controllers.
Thanks to JMicron for their continuous support of FreeBSD.
Diffstat (limited to 'sys/dev/jme/if_jmereg.h')
| -rw-r--r-- | sys/dev/jme/if_jmereg.h | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/sys/dev/jme/if_jmereg.h b/sys/dev/jme/if_jmereg.h index d89b2f5..8465355 100644 --- a/sys/dev/jme/if_jmereg.h +++ b/sys/dev/jme/if_jmereg.h @@ -239,8 +239,8 @@ #define RXCSR_FIFO_FTHRESH_MASK 0x30000000 #define RXCSR_FIFO_THRESH_16QW 0x00000000 #define RXCSR_FIFO_THRESH_32QW 0x04000000 -#define RXCSR_FIFO_THRESH_64QW 0x08000000 -#define RXCSR_FIFO_THRESH_128QW 0x0C000000 +#define RXCSR_FIFO_THRESH_64QW 0x08000000 /* JMC250/JMC260 REVFM < 2 */ +#define RXCSR_FIFO_THRESH_128QW 0x0C000000 /* JMC250/JMC260 REVFM < 2 */ #define RXCSR_FIFO_THRESH_MASK 0x0C000000 #define RXCSR_DMA_SIZE_16 0x00000000 #define RXCSR_DMA_SIZE_32 0x01000000 @@ -357,6 +357,16 @@ #define JME_GHC 0x0054 #define GHC_LOOPBACK 0x80000000 #define GHC_RESET 0x40000000 +#define GHC_RX_DMA_PWR_DIS 0x04000000 /* JMC250 REVFM >= 2 */ +#define GHC_FIFO_RD_PWR_DIS 0x02000000 /* JMC250 REVFM >= 2 */ +#define GHC_FIFO_WR_PWR_DIS 0x01000000 /* JMC250 REVFM >= 2 */ +#define GHC_TX_OFFLD_CLK_100 0x00800000 /* JMC250/JMC260 REVFM >= 2 */ +#define GHC_TX_OFFLD_CLK_1000 0x00400000 /* JMC250/JMC260 REVFM >= 2 */ +#define GHC_TX_OFFLD_CLK_DIS 0x00000000 /* JMC250/JMC260 REVFM >= 2 */ +#define GHC_TX_MAC_CLK_100 0x00200000 /* JMC250/JMC260 REVFM >= 2 */ +#define GHC_TX_MAC_CLK_1000 0x00100000 /* JMC250/JMC260 REVFM >= 2 */ +#define GHC_TX_MAC_CLK_DIS 0x00000000 /* JMC250/JMC260 REVFM >= 2 */ +#define GHC_AUTO_PHY_STAT_DIS 0x00000080 /* JMC250/JMC260 REVFM >= 2 */ #define GHC_FULL_DUPLEX 0x00000040 #define GHC_SPEED_UNKNOWN 0x00000000 #define GHC_SPEED_10 0x00000010 @@ -755,6 +765,10 @@ #define CHIPMODE_MODE_128P_MAC 0x00000003 #define CHIPMODE_MODE_128P_DBG 0x00000002 #define CHIPMODE_MODE_128P_PHY 0x00000000 +/* Chip full mask revision. */ +#define CHIPMODE_REVFM(x) ((x) & 0x0F) +/* Chip ECO revision. */ +#define CHIPMODE_REVECO(x) (((x) >> 4) & 0x0F) /* Shadow status base address high/low. */ #define JME_SHBASE_ADDR_HI 0x0848 |
