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author | yongari <yongari@FreeBSD.org> | 2008-12-04 02:16:53 +0000 |
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committer | yongari <yongari@FreeBSD.org> | 2008-12-04 02:16:53 +0000 |
commit | 153b44ab56e4c7bd7ae849aab8fa4723070bb637 (patch) | |
tree | d9ccffec741961154ecb1c477296af5042a9490b /sys/dev/jme/if_jmereg.h | |
parent | 20e7552f469bcf3d64dae25b11f9c4a9ff38f69e (diff) | |
download | FreeBSD-src-153b44ab56e4c7bd7ae849aab8fa4723070bb637.zip FreeBSD-src-153b44ab56e4c7bd7ae849aab8fa4723070bb637.tar.gz |
Add HW MAC counter support for newer JMC250/JMC260 revisions.
Diffstat (limited to 'sys/dev/jme/if_jmereg.h')
-rw-r--r-- | sys/dev/jme/if_jmereg.h | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/sys/dev/jme/if_jmereg.h b/sys/dev/jme/if_jmereg.h index 8465355..482c65f 100644 --- a/sys/dev/jme/if_jmereg.h +++ b/sys/dev/jme/if_jmereg.h @@ -199,6 +199,7 @@ #define TXMAC_IFG2_DEFAULT 0x40000000 #define TXMAC_IFG1_MASK 0x30000000 #define TXMAC_IFG1_DEFAULT 0x20000000 +#define TXMAC_PAUSE_CNT_MASK 0x00FF0000 #define TXMAC_THRESH_1_PKT 0x00000300 #define TXMAC_THRESH_1_2_PKT 0x00000200 #define TXMAC_THRESH_1_4_PKT 0x00000100 @@ -403,6 +404,44 @@ #define PMCS_MAGIC_FRAME_ENB 0x00000001 #define PMCS_WOL_ENB_MASK 0x0000FFFF +/* + * Statistic registers control and status. + * These statistics registers are valid only for JMC250/JMC260 REVFM >= 2. + */ +#define JME_STATCSR 0x0064 +#define STATCSR_RXMPT_DIS 0x00000080 +#define STATCSR_OFLOW_DIS 0x00000040 +#define STATCSR_MIIRXER_DIS 0x00000020 +#define STATCSR_CRCERR_DIS 0x00000010 +#define STATCSR_RXBAD_DIS 0x00000008 +#define STATCSR_RXGOOD_DIS 0x00000004 +#define STATCSR_TXBAD_DIS 0x00000002 +#define STATCSR_TXGOOD_DIS 0x00000001 + +#define JME_STAT_TXGOOD 0x0068 + +#define JME_STAT_RXGOOD 0x006C + +#define JME_STAT_CRCMII 0x0070 +#define STAT_RX_CRC_ERR_MASK 0xFFFF0000 +#define STAT_RX_MII_ERR_MASK 0x0000FFFF +#define STAT_RX_CRC_ERR_SHIFT 16 +#define STAT_RX_MII_ERR_SHIFT 0 + +#define JME_STAT_RXERR 0x0074 +#define STAT_RXERR_OFLOW_MASK 0xFFFF0000 +#define STAT_RXERR_MPTY_MASK 0x0000FFFF +#define STAT_RXERR_OFLOW_SHIFT 16 +#define STAT_RXERR_MPTY_SHIFT 0 + +#define JME_STAT_RESERVED1 0x0078 + +#define JME_STAT_FAIL 0x007C +#define STAT_FAIL_RX_MASK 0xFFFF0000 +#define STAT_FAIL_TX_MASK 0x0000FFFF +#define STAT_FAIL_RX_SHIFT 16 +#define STAT_FAIL_TX_SHIFT 0 + /* Giga PHY & EEPROM registers. */ #define JME_PHY_EEPROM_BASE_ADDR 0x0400 |