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| author | mjacob <mjacob@FreeBSD.org> | 2001-01-15 18:37:14 +0000 |
|---|---|---|
| committer | mjacob <mjacob@FreeBSD.org> | 2001-01-15 18:37:14 +0000 |
| commit | f04fea5b5ff3e4d384723bc24dee8d1c2cbb9cba (patch) | |
| tree | 5ddc9b69e618fb3552fba1c22516e2b330a8b5ac /sys/dev/isp | |
| parent | 0f7d4019f8dfdc993dd6b148e678410aff584b10 (diff) | |
| download | FreeBSD-src-f04fea5b5ff3e4d384723bc24dee8d1c2cbb9cba.zip FreeBSD-src-f04fea5b5ff3e4d384723bc24dee8d1c2cbb9cba.tar.gz | |
Put in offset definitions for FPM and FBM registers, plus just enough
bits defined so we can reset them.
Diffstat (limited to 'sys/dev/isp')
| -rw-r--r-- | sys/dev/isp/ispreg.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/sys/dev/isp/ispreg.h b/sys/dev/isp/ispreg.h index 0dd517b..d50cdf7 100644 --- a/sys/dev/isp/ispreg.h +++ b/sys/dev/isp/ispreg.h @@ -350,6 +350,19 @@ #define MAX_MAILBOX 8 /* + * Fibre Protocol Module and Frame Buffer Register Offsets/Definitions (2X00). + * NB: The RISC processor must be paused and the appropriate register + * bank selected via BIU2100_CSR bits. + */ + +#define FPM_DIAG_CONFIG (BIU_BLOCK + 0x96) +#define FPM_SOFT_RESET 0x0100 + +#define FBM_CMD (BIU_BLOCK + 0xB8) +#define FBMCMD_FIFO_RESET_ALL 0xA000 + + +/* * SXP Block Register Offsets */ #define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */ @@ -601,6 +614,10 @@ #define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ #define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ #define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ +#define HCCR_2X00_DISABLE_PARITY_PAUSE 0x4001 /* + * Disable RISC pause on FPM + * parity error. + */ #define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ #define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ #define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ |
