sys/dev: minor spelling fixes.

Most affect comments, very few have user-visible effects.

2 files changed, 3 insertions, 3 deletions

diff --git a/sys/dev/ichiic/ig4_iic.c b/sys/dev/ichiic/ig4_iic.c
index 23bdb7d..ff27da2 100644
--- a/sys/dev/ichiic/ig4_iic.c
+++ b/sys/dev/ichiic/ig4_iic.c
@@ -659,7 +659,7 @@ ig4iic_smb_callback(device_t dev, int index, void *data)
 /*
  * Quick command.  i.e. START + cmd + R/W + STOP and no data.  It is
  * unclear to me how I could implement this with the intel i2c controller
- * because the controler sends STARTs and STOPs automatically with data.
+ * because the controller sends STARTs and STOPs automatically with data.
  */
 int
 ig4iic_smb_quick(device_t dev, u_char slave, int how)
diff --git a/sys/dev/ichiic/ig4_reg.h b/sys/dev/ichiic/ig4_reg.h
index c87d1d1..33976c0 100644
--- a/sys/dev/ichiic/ig4_reg.h
+++ b/sys/dev/ichiic/ig4_reg.h
@@ -185,7 +185,7 @@
  *	RESTART		- RW This bit controls whether a forced RESTART is
  *			  issued before the byte is sent or received.
  *
- *		0	  If not set a RESTART is only issued if the tranfer
+ *		0	  If not set a RESTART is only issued if the transfer
  *			  direction is changing from the previous command.
  *
  *		1	  A RESTART is issued before the byte is sent or
@@ -271,7 +271,7 @@
  *			cleared by HW when the buffer level goes above
  *			the threshold.
  *
- *	TX_OVER		Indicates that the processer attempted to write
+ *	TX_OVER		Indicates that the processor attempted to write
  *			to the TX FIFO while the TX FIFO was full.  Cleared
  *			by reading CLR_TX_OVER.
  *