diff options
| author | marius <marius@FreeBSD.org> | 2017-01-18 23:25:46 +0000 |
|---|---|---|
| committer | marius <marius@FreeBSD.org> | 2017-01-18 23:25:46 +0000 |
| commit | 008ff9eee5f55c6da4d42a6c3f1201b8dc98a726 (patch) | |
| tree | d306e45fdb4593bce5b7b0663eec831e6982472c /sys/dev/ichiic | |
| parent | dc0b18d57b66d178dc4334057db897f1e0535169 (diff) | |
| download | FreeBSD-src-008ff9eee5f55c6da4d42a6c3f1201b8dc98a726.zip FreeBSD-src-008ff9eee5f55c6da4d42a6c3f1201b8dc98a726.tar.gz | |
MFC: r310309, r310340-310341, r311664, r311793-r311794
o sdhci/mmc: Minor whitespace cleanups
o Add Braswell PCI IDs for Intel Cherryview
o mmc: Accept even lower voltage for Cherryview
And HP x2 210, per DragonFlyBSD 240bd9cd58f8259c12c14a8006837e698.
o In mmcsd_task(), bio_resid was not being set to 0 on a successful read
or write, resulting in random short-read and short-write returns for
requests. Fixing this fixes nominal block I/O via mmcsd(4).
Obtained from: DragonFlyBSD (fd4b97583be1a1e57234713c25f6e81bc0411cb0)
o Add support for Intel Apollo Lake and Bay Trail eMMC PCI controllers.
o Flesh out the support for Intel Braswell eMMC controllers further.
o In sdhci_init_slot(), use the right capability field for determining
the announced bus width based on MMC_CAP_*_BIT_DATA.
Diffstat (limited to 'sys/dev/ichiic')
| -rw-r--r-- | sys/dev/ichiic/ig4_pci.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/sys/dev/ichiic/ig4_pci.c b/sys/dev/ichiic/ig4_pci.c index 2cc468d..04e31d6 100644 --- a/sys/dev/ichiic/ig4_pci.c +++ b/sys/dev/ichiic/ig4_pci.c @@ -68,6 +68,12 @@ static int ig4iic_pci_detach(device_t dev); #define PCI_CHIP_LYNXPT_LP_I2C_1 0x9c618086 #define PCI_CHIP_LYNXPT_LP_I2C_2 0x9c628086 +#define PCI_CHIP_BRASWELL_I2C_1 0x22c18086 +#define PCI_CHIP_BRASWELL_I2C_2 0x22c28086 +#define PCI_CHIP_BRASWELL_I2C_3 0x22c38086 +#define PCI_CHIP_BRASWELL_I2C_5 0x22c58086 +#define PCI_CHIP_BRASWELL_I2C_6 0x22c68086 +#define PCI_CHIP_BRASWELL_I2C_7 0x22c78086 static int ig4iic_pci_probe(device_t dev) @@ -79,6 +85,24 @@ ig4iic_pci_probe(device_t dev) case PCI_CHIP_LYNXPT_LP_I2C_2: device_set_desc(dev, "Intel Lynx Point-LP I2C Controller-2"); break; + case PCI_CHIP_BRASWELL_I2C_1: + device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 1"); + break; + case PCI_CHIP_BRASWELL_I2C_2: + device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 2"); + break; + case PCI_CHIP_BRASWELL_I2C_3: + device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 3"); + break; + case PCI_CHIP_BRASWELL_I2C_5: + device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 5"); + break; + case PCI_CHIP_BRASWELL_I2C_6: + device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 6"); + break; + case PCI_CHIP_BRASWELL_I2C_7: + device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 7"); + break; default: return (ENXIO); } |
