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| author | jkoshy <jkoshy@FreeBSD.org> | 2007-11-29 06:43:58 +0000 |
|---|---|---|
| committer | jkoshy <jkoshy@FreeBSD.org> | 2007-11-29 06:43:58 +0000 |
| commit | f8b4b9845d4d1c8d6d9480645cca2c21d22928fc (patch) | |
| tree | aa064ec313b11ec59da0a177ae229265bf62cf76 /sys/dev/hwpmc | |
| parent | 8e9baed5537acc943e5fd7641e69438a2466c1ad (diff) | |
| download | FreeBSD-src-f8b4b9845d4d1c8d6d9480645cca2c21d22928fc.zip FreeBSD-src-f8b4b9845d4d1c8d6d9480645cca2c21d22928fc.tar.gz | |
Revert revision 1.4.
Intel CPUs with family 0x6, model 0xE and later (i.e., Intel Core(TM))
have a PMC architecture that differs somewhat from previous CPUs in
family 0x6. Even though the basic programming model is similar, the
documented set of legal values that may be loaded into their PMC MSRs
differs from that of the previous PMCs in family 0x6 and reusing bit
values valid for the older PMCs could result in undefined behaviour in
the general case.
Diffstat (limited to 'sys/dev/hwpmc')
| -rw-r--r-- | sys/dev/hwpmc/hwpmc_x86.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sys/dev/hwpmc/hwpmc_x86.c b/sys/dev/hwpmc/hwpmc_x86.c index 9b00b63..cb6db23 100644 --- a/sys/dev/hwpmc/hwpmc_x86.c +++ b/sys/dev/hwpmc/hwpmc_x86.c @@ -82,7 +82,7 @@ pmc_intel_initialize(void) case 0x7: case 0x8: case 0xA: case 0xB: cputype = PMC_CPU_INTEL_PIII; break; - case 0x9: case 0xD: case 0xE: + case 0x9: case 0xD: cputype = PMC_CPU_INTEL_PM; break; } |
