- Support for uncore counting events: one fixed PMC with the uncore

  domain clock, 8 programmable PMC.
- Westmere based CPU (Xeon 5600, Corei7 980X) support.
- New man pages with events list for core and uncore.
- Updated Corei7 events with Intel 253669-033US December 2009 doc.
  There is some removed events in the documentation, they have been
  kept in the code but documented in the man page as obsolete.
- Offcore response events can be setup with rsp token.

Sponsored by: NETASQ

1 files changed, 40 insertions, 1 deletions

diff --git a/sys/dev/hwpmc/hwpmc_intel.c b/sys/dev/hwpmc/hwpmc_intel.c
index e953f68..82d5079 100644
--- a/sys/dev/hwpmc/hwpmc_intel.c
+++ b/sys/dev/hwpmc/hwpmc_intel.c
@@ -133,8 +133,14 @@ pmc_intel_initialize(void)
 		case 0x1A:
 		case 0x1E:	/* Per Intel document 253669-032 9/2009, pages A-2 and A-57 */
 		case 0x1F:	/* Per Intel document 253669-032 9/2009, pages A-2 and A-57 */
+		case 0x2E:
 			cputype = PMC_CPU_INTEL_COREI7;
-			nclasses = 3;
+			nclasses = 5;
+			break;
+		case 0x25:	/* Per Intel document 253669-033US 12/2009. */
+		case 0x2C:	/* Per Intel document 253669-033US 12/2009. */
+			cputype = PMC_CPU_INTEL_WESTMERE;
+			nclasses = 5;
 			break;
 		}
 		break;
@@ -176,6 +182,7 @@ pmc_intel_initialize(void)
 	case PMC_CPU_INTEL_CORE2:
 	case PMC_CPU_INTEL_CORE2EXTREME:
 	case PMC_CPU_INTEL_COREI7:
+	case PMC_CPU_INTEL_WESTMERE:
 		error = pmc_core_initialize(pmc_mdep, ncpus);
 		break;
 
@@ -226,6 +233,22 @@ pmc_intel_initialize(void)
 		KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__));
 	}
 
+	/*
+	 * Init the uncore class.
+	 */
+#if	defined(__i386__) || defined(__amd64__)
+	switch (cputype) {
+		/*
+		 * Intel Corei7 and Westmere processors.
+		 */
+	case PMC_CPU_INTEL_COREI7:
+	case PMC_CPU_INTEL_WESTMERE:
+		error = pmc_uncore_initialize(pmc_mdep, ncpus);
+		break;
+	default:
+		break;
+	}
+#endif
 
   error:
 	if (error) {
@@ -247,6 +270,8 @@ pmc_intel_finalize(struct pmc_mdep *md)
 	case PMC_CPU_INTEL_CORE:
 	case PMC_CPU_INTEL_CORE2:
 	case PMC_CPU_INTEL_CORE2EXTREME:
+	case PMC_CPU_INTEL_COREI7:
+	case PMC_CPU_INTEL_WESTMERE:
 		pmc_core_finalize(md);
 		break;
 
@@ -269,4 +294,18 @@ pmc_intel_finalize(struct pmc_mdep *md)
 	default:
 		KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__));
 	}
+
+	/*
+	 * Uncore.
+	 */
+#if	defined(__i386__) || defined(__amd64__)
+	switch (md->pmd_cputype) {
+	case PMC_CPU_INTEL_COREI7:
+	case PMC_CPU_INTEL_WESTMERE:
+		pmc_uncore_finalize(md);
+		break;
+	default:
+		break;
+	}
+#endif
 }